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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
CARDBUS POWER-INTERFACE SWITCHES FOR SERIAL PCMCIA CONTROLLERS
FEATURES
* Single-Slot Switch: TPS2220A Dual-Slot Switches: TPS2223A, TPS2224A, TPS2226A Fast Current Limit Response Time Fully Integrated VCC and VPP Switching for 3.3 V, 5 V, and 12 V (no 12 V on TPS2223A) Meets Current PC CardTM Standards Vpp Output Selection Independent of VCC 12-V and 5-V Supplies Can Be Disabled TTL-Logic Compatible Inputs Short-Circuit and Thermal Protection 24-Pin HTSSOP, 24- or 30-Pin SSOP 140-A (Typical) Quiescent Current from 3.3-V Input Break-Before-Make Switching Power-On Reset 40C to 85C Operating Ambient Temperature Range
APPLICATIONS
* * * * * Notebook and Desktop Computers Bar Code Scanners Digital Cameras Set-Top Boxes PDAs
TPS2223A, TPS2224A DB OR PWP PACKAGE (TOP VIEW) 5V 5V DATA CLOCK LATCH NC 12V AVPP AVCC AVCC GND RESET 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 5V NC NC SHDN 12V BVPP BVCC BVCC NC OC 3.3V 3.3V
* * * * * * * * * * * *
NC - No internal connection Pin 7 and 20 are NC for
TPS2223A.
DESCRIPTION
The TPS2223A, TPS2224A, and TPS2226A CardBusTM power-interface switches provide an integrated power-management solution for two PC Card sockets. The TPS2220A is a single-slot option for this family of devices. These devices allow the controlled distribution of 3.3 V, 5 V, and 12 V to each card slot. The current-limiting and thermal-protection features eliminate the need for fuses. Current-limit reporting helps the user isolate a system fault. The switch rDS(on) and current-limit values have been set for the peak and average current requirements stated in the PC Card specification, and optimized for cost. A faster maximum current limit response time is the only difference between the TPS2223A, TPS2224A, and TPS2226A and the TPS2223, TPS2224, and TPS2226. Like the TPS2214 and TPS2214A and the TPS2216 and TPS2216A, this family of devices supports independent VPP/VCC switching; however, the standby and interface-mode pins are not supported. Shutdown mode is now supported independently on SHDN as well as in the serial interface. Optimized for lower power implementation, the TPS2223A does not support 12-V switching to VPP. See the available options table for pin-compatible device information.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PC Card, CardBus are trademarks of PCMCIA (Personal Computer Memory Card International Association). PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2002-2004, Texas Instruments Incorporated
TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS
PACKAGED DEVICES TA PLASTIC SMALL OUTLINE DB-24 TPS2223ADB, TPS2224ADB -40C to 85C Pin compatibles TPS2214, TPS2214A TPS2220ADB DB-30 TPS2226ADB Pin compatibles TPS2216, TPS2216A, TPS2206 TPS2223APWP, TPS2224APWP TPS2220APWP PowerPADTM PLASTIC SMALL OUTLINE (PWP-24) (1)
(1)
The DB and PWP packages are alsoavailable taped and reeled. Add R suffix to device type (e.g., TPS2223APWPR)for taped and reeled.
LEAD (PB-FREE) ORDERING INFORMATION
TA SOIC(D) TPS2220D -40C to 85C TPS2223D TPS2224D TPS2226D (1) STATUS Active Active Active Active
(1)
MSOP(DGN) TPS2220DGN TPS2223DGN TPS2224DGN TPS2226DGN
STATUS (1) Active Preview Preview Preview
ECO-STATUS (2)
Green
(2)
The marketing statusvalues are defined as follows: * ACTIVE: This device recommended for new designs. * LIFEBUY: TI has announced that the device will bediscontinued, and a lifetime-buy period is in effect. * NRND: Notrecommended for new designs. Device is in production to support existingcustomers, but TI does not recommend using this part in a newdesign. * PREVIEW: Device has been announced but is not inproduction. Samples may or may not be available. * OBSOLETE: TI hasdiscontinued production of the device. Eco-Status Information - Additionaldetails including specific material content can be accessed atwww.ti.com/leadfree * N/A: Not yet available Lead (Pb)-free, for estimatedconversion dates go to www.ti.com/leadfree. * Pb-Free: TIdefines "Lead (Pb)-Free" or "Pb-Free" to mean RoHS compatible, including a leadconcentration that does not exceed 0.1% of total product weight, and, ifdesigned to be soldered, suitable for use in specified lead-free solderingprocesses. * Green: TI devices "Green" to mean Lead (Pb)-Free andin addition, uses package materials that do not contain halogens, includingbromine (Br), or antimony (Sb) above 0.1% of total productweight.
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
TPA222xA VI(3.3V) VI Input voltage range for card power Logic input/output voltage VO Output voltage Continuous total power dissipation IO TJ Tstg Output current Operating virtual junction temperature range Storage temperature range Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds) OC sink current (1) (2) IO(xVCC) IO(xVPP) VO(xVCC) VO(xVPP) VI(5V) VI(12V) (2) -0.3 to 5.5 -0.3 to 5.5 -0.3 to 14 -0.3 to 6 -0.3 to 6 -0.3 to 14 See Dissipation Rating Table Internally Limited Internally Limited -40 to 100 -55 to 150 260 10 C C C mA UNIT V V V V V V
Stresses beyond those listed under"absolute maximum ratings" may cause permanent damage to the device. These arestress ratings only, and functional operation of the device at these or anyother conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions forextended periods may affect device reliability. Not applicable forTPS2223A
DISSIPATION RATING TABLE
PACKAGE (1) DB PWP (1) 24 30 24 TA 25C POWER RATING 890 mW 1095 mW 3322 mW DERATING FACTOR ABOVE TA = 25C 8.9 mW/C 10.95 mW/C 33.22 mW/C TA = 70C POWER RATING 489 mW 602 mW 1827 mW TA = 85C POWER RATING 356 mW 438 mW 1329 mW
These devices are mounted on anJEDEC low-k board (2-oz. traces on surface).
RECOMMENDED OPERATING CONDITIONS
MIN Input voltage, VI(3.3V) is required for all circuit operations. 5V and 12V are only required for VI(5V) their respective functions. VI(12V) (2) IO f(clock) Output current Clock frequency Data tw Pulse duration Latch Clock Reset th tsu td(latch) td(clock) TJ (1) (2) Data-to-clock hold time (see Figure 2) Data-to-clock setup time (see Figure 2) Latch delay time (see Figure 2) Clock delay time (see Figure 2) Operating virtual junction temperature (maximum to be calculated at worst case PD at 85C ambient) 200 250 100 100 100 100 100 250 -40 100 ns ns ns ns C ns VI(3.3V) (1) 3 3 7 MAX 3.6 5.5 13.5 1 100 2.5 A mA MHz V UNIT
IO(xVCC) at TJ = 100C IO(xVPP) at TJ = 100C
It is understood that forVI(3.3V) < 3 V, voltages within theabsolute maximum ratings applied to pin 5V or pin 12V do not damage theIC. Not applicable forTPS2223A
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
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ELECTRICAL CHARACTERISTICS
TJ = 25C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V (not applicable for TPS2223A), all outputs unloaded (unless otherwise noted)
PARAMETER POWER SWITCH 3.3V to xVCC (2) 5V to xVCC (2) rDS(on) Static drain-source on-state resistance 3.3V or 5V to xVPP (2) 12V to xVPP (2) Output discharge resistance Discharge at xVCC Discharge at xVPP IO = 750 mA each IO = 750 mA each, TJ = 100C IO = 500 mA each IO = 500 mA each, TJ = 100C IO = 50 mA each IO = 50 mA each, TJ = 100C IO = 50 mA each IO = 50 mA each, TJ = 100C IO(disc) = 1 mA IO(disc) = 1 mA Limit (steady-state value), output powered into a short circuit IOS Short-circuit output current Limit (steady-state value), output powered into a short circuit, TJ = 100C Thermal trip point Hysteresis 5V to xVCC = 5 V, with 100-m short to GND 5V to xVPP = 5 V, with 100-m short to GND II(3.3V) Normal operation II Input current, quiescent Shutdown mode II(5V) II(12V) II(3.3V) II(5V) II(12V) VO(xVCC) = 5 V, VI(5V) = VI(12V) = 0 V Ilkg Leakage current, output off state Shutdown mode VO(xVPP) = 12 V, VI(5V) = VI(12V) = 0 V TJ = 100C TJ = 100C VO(xVCC) = VO(xVPP) = Hi-z VO(xVCC) = VO(xVPP) = 3.3 V and also for RESET = 0 V Rising temperature IOS(xVCC) IOS(xVPP) IOS(xVCC) IOS(xVPP) 0.5 0.2 1 120 1 120 85 110 95 120 0.8 1 2 2.5 0.7 0.4 1.4 200 1.4 200 135 10 10 3 140 8 100 0.3 0.1 0.3 200 12 180 2 2 2 10 50 10 50 A A 110 140 130 160 1 1.3 2.5 3.4 1 0.5 2 300 2 300 k A mA A mA C s m TEST CONDITIONS (1) MIN TYP MAX UNIT
TJ
Thermal shutdown temperature (2)
Current-limit response time (3) (4)
(1) (2) (3) (4)
Pulse-testing techniques maintainjunction temperature close to ambient temperature; thermal effects must betaken into account separately. TPS2223A, TPS2224A, TPS2226A:two switches on. TPS2220A: one switch on. Specified by design; not tested inproduction. From application of short to 110% offinal current limit.
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
TJ = 25C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V (not applicable for TPS2223A), all outputs unloaded (unless otherwise noted)
PARAMETER LOGIC SECTION (CLOCK, DATA, LATCH, RESET, SHDN, OC) II(/RESET)
(5)
TEST CONDITIONS (1)
MIN
TYP
MAX
UNIT
RESET = 5.5 V RESET = 0 V SHDN = 5.5 V SHDN = 0 V LATCH = 5.5 V LATCH = 0 V 0 V to 5.5 V
-1 -30 -1 -50 -20
1 -10 1 -3 50 A
II
Input current, logic
II(/SHDN) (5) II(LATCH) (5) II(CLOCK,
DATA)
-1 -1 2
1 1 V 0.8 V V A
VIH VIL VO(sat) Ilkg VI(3.3V) Vhys(3.3V) VI(5V) Vhys(5V) tdf VI(POR)
High-level input voltage, logic Low-level input voltage, logic Output saturation voltage at OC Leakage current at OC IO = 2 mA VO(/OC) = 5.5 V 3.3-V level below which all switches are Hi-Z
0.14 0
0.4 1
UVLO AND POR (POWER-ON RESET) Input voltage at 3.3V pin, UVLO UVLO hysteresis voltage at VA (6) Input voltage at 5V pin, UVLO UVLO hysteresis voltage at 5V (6) Delay time for falling response, UVLO (6) Input voltage, power-on reset (6) 3.3-V voltage below which POR is asserted causing a RESET internally with all line switches open and all discharge switches closed. 5-V level below which only 5V switches are Hi-Z Delay from voltage hit (step from 3 V to 2.3 V) to Hi-Z control (90% VG to GND) 2.3 2.4 2.7 100 2.5 100 4 1.7 2.9 V mV V mV s V
(5) (6)
LATCH has low-current pulldown.RESET and SHDN have low-current pullup. Specified by design; not tested inproduction.
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
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SWITCHING CHARACTERISTICS
VCC = 5 V, TA = 25C, VI(3.3V) = 3.3 V, VI(5V) = 5 V, VI(12) = 12 V (not applicable for TPS2223A) all outputs unloaded (unless otherwise noted)
PARAMETER (1) LOAD CONDITION CL(xVCC) = 0.1 F, CL(xVPP) = 0.1 F, IO(xVCC) = 0 A, IO(xVPP) = 0 A CL(xVCC) = 150 F, CL(xVPP) = 10 F, IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA CL(xVCC) = 0.1 F, CL(xVPP) = 0.1 F, IO(xVCC) = 0 A, IO(xVPP) = 0 A CL(xVCC) = 150 F, CL(xVPP) = 10 F, IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA TEST CONDITIONS (2) VO(xVCC) = 5 V VO(xVPP) = 12 V VO(xVCC) = 5 V VO(xVPP) = 12 V VO(xVCC) = 5 V, Discharge switches ON VO(xVPP) = 12 V, Discharge switches ON VO(xVCC) = 5 V VO(xVPP) = 12 V Latch to xVPP (12V) (4) Latch to xVPP (5V) CL(xVCC) = 0.1 F, CL(xVPP) = 0.1 F, IO(xVCC) = 0 A, IO(xVPP) = 0 A Latch to xVPP (3.3V) Latch to xVCC (5V) Latch to xVCC (3.3V) tpd Propagation delay times (3) Latch to xVPP (12V) (4) Latch to xVPP (5V) CL(xVCC) = 150 F, CL(xVPP) = 10 F, IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA Latch to xVPP (3.3V) Latch to xVCC (5V) Latch to xVCC (3.3V) tpdon tpdoff tpdon tpdoff tpdon tpdoff tpdon tpdoff tpdon tpdoff tpdon tpdoff tpdon tpdoff tpdon tpdoff tpdon tpdoff tpdon tpdoff MIN TYP MAX 0.9 0.26 1.1 0.6 0.5 0.2 2.35 3.9 2 0.62 0.77 0.51 0.75 0.52 0.3 2.5 0.3 2.8 2.2 0.8 0.8 0.6 0.8 0.6 0.6 2.5 0.5 2.6 ms ms ms ms UNIT
tr
Output rise times (3)
tf
Output fall times
(3)
(1) (2) (3) (4)
Refer to Parameter MeasurementInformation in Figure 1. No card inserted, assumes a0.1-F output capacitor (seeFigure 1). Specified by design; not tested inproduction. Not applicable forTPS2223A
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
FUNCTIONAL BLOCK DIAGRAM OF TPS2223A, TPS2224A and TPS2226A (see Note A)
Power Inputs 3.3V Power Inputs 5V 3.3 V 3.3 V 13 14 S2 CS S5 S3 S6 CS See Note B S4 17 18 See Note B S1 9 10 AVCC AVCC
1 5V 2 5V 5 V 24
BVCC BVCC Power Outputs
See Note C 12 V Power Inputs 12V See Note D
7
S8 S9
See Note B CS S7
8
AVPP
S10
12 V 20 See Note C
S12 S13
See Note B CS S11 Discharge Element
19
BVPP
S14
Control Logic 21 12 3 4 5 SHDN RESET DATA CLOCK LATCH GND
See Note C Current Limit Thermal Limit 11
15
UVLO OC POR
NOTES: A. B. C. D.
Diagram shown for 24-pin DB package. Current sense The two 12-V pins must be externally connected. No connections for TPS2223A.
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
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FUNCTIONAL BLOCK DIAGRAM OF TPS2220A
S2 3.3 V See Note A CS S1 S3 5V S4 S5 5V 12 V See Note B S7 See Note A CS AVPP AVCC AVCC
S6 12 V See Note B Control Logic SHDN RESET DATA CLOCK LATCH GND Thermal Limit Current Limit
UVLO OC POR
NOTES: A. Current sense B. The two 12-V pins must be externally connected.
PIN ASSIGNMENTS
TPS2226A DB PACKAGE (TOP VIEW) 5V 5V DATA CLOCK LATCH NC 12V AVPP AVCC AVCC AVCC GND NC RESET 3.3V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5V NC NC NC NC SHDN 12V BVPP BVCC BVCC BVCC NC OC 3.3V 3.3V 5V 5V DATA CLOCK LATCH NC 12V AVPP AVCC AVCC GND RESET TPS2220A DB OR PWP PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC NC NC SHDN 12V NC NC NC NC OC NC 3.3V
NC - No internal connection
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
PIN ASSIGNMENTS (continued)
Terminal Functions
TERMINAL NAME 3.3V 5V 12V AVCC AVPP BVCC BVPP GND OC SHDN RESET CLOCK DATA LATCH NC NO. TPS2220A TPS2223A TPS2224A TPS2226A 13 1, 2 7, 20 9, 10 8 --11 15 21 12 4 3 5 6, 14, 16, 17, 18, 19, 22, 23, 24 13, 14 1, 2, 24 NA 9, 10 8 17, 18 19 11 15 21 12 4 3 5 6, 7, 16, 20, 22, 23 13, 14 1, 2, 24 7, 20 9, 10 8 17, 18 19 11 15 21 12 4 3 5 6, 16, 22, 23 15, 16, 17 1, 2, 30 7, 24 9, 10, 11 8 20, 21, 22 23 12 18 25 14 4 3 5 6, 13, 19, 26, 27, 28, 29 O I I I I I I I I O O O O 3.3-V input for card power and chip power 5-V input for card power 12-V input for card power (xVPP). The two 12-V pins must be externally connected. Switched output that delivers 3.3 V, 5 V, ground or high impedance to card Switched output that delivers 3.3 V, 5 V, 12 V, ground or high impedance to card (12 V not applicable to TPS2223A) Switched output that delivers 3.3 V, 5 V, ground or high impedance to card Switched output that delivers 3.3 V, 5 V, 12 V, ground or high impedance to card (12 V not applicable for TPS2223A) Ground Open-drain overcurrent reporting output that goes low when an overcurrent condition exists. An external pullup is required. Hi-Z (open) all switches. Identical function to serial D8. Asynchronous active-low command, internal pullup Logic-level RESET input active low. Asynchronous active-low command, internal pullup Logic-level clock for serial data word Logic-level serial data word Logic-level latch for serial data word, internal pulldown No internal connection I/O DESCRIPTION
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
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PARAMETER MEASUREMENT INFORMATION
xVPP IO(xVPP) xVCC IO(xVCC)
LOAD CIRCUIT (xVPP)
LOAD CIRCUIT (xVCC)
LATCH
VDD 50% GND tpd(off) VI(12V/5V/3.3V) 90% 10% GND
LATCH
VDD 50% GND tpd(off) VI(5V/3.3V)
tpd(on) VO(xVPP)
tpd(on) VO(xVCC)
90% 10% GND
Propagation Delay (xVPP) tf VI(12V/5V/3.3V) 90% 10% Rise/Fall Time (xVPP) GND
Propagation Delay (xVCC) tf VI(5V/3.3V) 90% 10% Rise/Fall Time (xVCC) GND
tr VO(xVPP)
tr VO(xVCC)
LATCH
VDD 50% GND ton toff VI(12V/5V/3.3V) 90% 10% Turnon/off Time (xVPP) VOLTAGE WAVEFORMS GND ton VO(xVCC) toff LATCH 50%
VDD GND
VI(5V/3.3V) 90% 10% Turnon/off Time (xVCC) GND
VO(xVPP)
Figure 1. Test Circuits and Voltage Waveforms
DATA
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data Setup Time LATCH
Data Hold Time
Latch Delay Time Clock Delay Time
CLOCK
NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next positive edge of the clock. For definition of D0 to D10, see the control logic table.
Figure 2. Serial-Interface Timing for TPS2226A
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION (continued) Table of Graphs
FIGURE Short-circuit response, short applied to powered-on 5-V xVCC-switch output OC response with ramped overcurrent-limit load on 5-V xVCC-switch output xVCC Turnon propagation delay time (CL = 150 F) xVCC Turnoff propagation delay time (CL = 150 F) xVPP Turnon propagation delay time (CL = 10 F) xVPP Turnoff propagation delay time (CL = 10 F) xVCC Turnon propagation delay time (TJ = 25C) xVCC Turnoff propagation delay time (TJ = 25C) xVPP Turnon propagation delay time (TJ = 25C) xVPP Turnoff propagation delay time (TJ = 25C) xVCC Rise time (CL = 150 F) xVCC Fall time (CL = 150 F) xVPP Rise time (CL = 10 F) xVPP Fall time (CL = 10 F) xVCC Rise time (TJ = 25C) xVCC Fall time (TJ = 25C) xVPP Rise time (TJ = 25C) xVPP Fall time (TJ = 25C) vs Time vs Time vs Junction temperature vs Junction temperature vs Junction temperature vs Junction temperature vs Load capacitance vs Load capacitance vs Load capacitance vs Load capacitance vs Junction temperature vs Junction temperature vs Junction temperature vs Junction temperature vs Load capacitance vs Load capacitance vs Load capacitance vs Load capacitance 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Short-circuit response, short applied to powered-on 12-V xVPP-switch output vs Time OC response with ramped overcurrent-limit load on 12-V xVPP-switch output vs Time
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
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SHORT-CIRCIUT RESPONSE, SHORT APPLIED TO POWERED-ON 5-V xVCC-SWITCH OUTPUT
SHORT-CIRCIUT RESPONSE, SHORT APPLIED TO POWERED-ON 12-V xVPP-SWITCH OUTPUT
VO(/OC) 5 V/div VIN(5V) 2 V/div
VO(/OC) 2 V/div
IO(VCC) 5 A/div 0 100 200 300 400 500
IO(xVPP) 2 A/div 0 1 2 3 4 5
t - Time - s
t - Time - ms
Figure 3. OC RESPONSE WITH RAMPED OVERCURRENT-LIMIT LOAD ON 5-V xVCC-SWITCH OUTPUT
Figure 4. OC RESPONSE WITH RAMPED OVERCURRENT-LIMIT LOAD ON 12-V xVPP-SWITCH OUTPUT
VO(/OC) 5 V/div
VO(/OC) 5 V/div
IO(xVCC) 1 A/div 0 10 20 30 40 50
IO(xVPP) 100 mA/div 0 2 4 6 8 10
t - Time - ms
t - Time - ms
Figure 5.
Figure 6.
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
TURNON PROPAGATION DELAY TIME, xVCC vs JUNCTION TEMPERATURE
t pd(on) - Turnon Propagation Delay Time, xVCC - ms xVCC = 5 V IO = 0.75 A CL = 150 F t pd(off) - Turnoff Propagation Delay Time, xVCC - ms 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 2.6
TURNOFF PROPAGATION DELAY TIME, xVCC vs JUNCTION TEMPERATURE
2.55 2.5
xVCC = 5 V IO = 0.75 A CL = 150 F
2.45 2.4
2.35 2.3 2.25 -50
-20 10 40 70 TJ - Junction Temperature - C
100
-20 10 40 70 TJ - Junction Temperature - C
100
Figure 7. TURNON PROPAGATION DELAY TIME, xVPP vs JUNCTION TEMPERATURE
3 xVPP = 12 V IO = 0.05 A CL = 10 F t pd(off) - Turnoff Propagation Delay Time, xVCC - ms t pd(on) - Turnon Propagation Delay Time, xVPP - ms 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50
Figure 8. TURNON PROPAGATION DELAY TIME, xVPP vs JUNCTION TEMPERATURE
2.5
2
1.5
1
0.5
xVCC = 12 V IO = 0.05 A CL = 10 F
0 -50
-20 10 40 70 TJ - Junction Temperature - C
100
-20 10 40 70 TJ - Junction Temperature - C
100
Figure 9.
Figure 10.
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
www.ti.com
TURNON PROPAGATION DELAY TIME, xVCC vs LOAD CAPACITANCE
0.7 0.6 0.5 xVCC = 5 V IO = 0.75 A TJ = 25C t pd(off) - Turnoff Propagation Delay Time, xVCC - ms t pd(on) - Turnon Propagation Delay Time, xVCC - ms 2.55
TURNON PROPAGATION DELAY TIME, xVCC vs LOAD CAPACITANCE
2.5
xVCC = 5 V IO = 0.75 A TJ = 25C
2.45
0.4 0.3 0.2 0.1 0
2.4
2.35
2.3
0.1
1 10 100 CL - Load Capacitance - F
1000
2.25 0.1
1 10 100 CL - Load Capacitance - F
1000
Figure 11. TURNON PROPAGATION DELAY TIME, xVPP vs LOAD CAPACITANCE
2.25 xVPP = 12 V IO = 0.05 A TJ = 25C t pd(off) - Turnoff Propagation Delay Time, xVPP - ms t pd(on) - Turnon Propagation Delay Time, xVPP - ms 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 xVPP = 12 V IO = 0.05 A TJ = 25C
Figure 12. TURNON PROPAGATION DELAY TIME, xVPP vs LOAD CAPACITANCE
2.2
2.15
2.1
2.05
2
1.95 0.1
1 CL - Load Capacitance - F
10
1 CL - Load Capacitance - F
10
Figure 13.
Figure 14.
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
RISE TIME, xVCC vs JUNCTION TEMPERATURE
1.22 1.2 t r - Rise Time, xVCC - ms 1.18 1.16 1.14 1.12 1.1 1.08 1.06 1.04 -50 -20 10 40 70 TJ - Junction Temperature - C 100 2.35 2.34 -50 xVCC = 5 V IO = 0.75 A CL = 150 F 2.41 2.4 t f - Fall Time xVCC - ms 2.39
FALL TIME, xVCC vs JUNCTION TEMPERATURE
xVCC = 5 V IO = 0.75 A CL = 150 F
2.38 2.37
2.36
-20 10 40 70 TJ - Junction Temperature - C
100
Figure 15. RISE TIME, xVPP vs JUNCTION TEMPERATURE
0.605 xVPP = 12 V IO = 0.05 A CL = 10 F t f - Fall Time, xVPP - ms 4.15 xVPP = 12 V IO = 0.05 A CL = 10 F
Figure 16. FALL TIME, xVPP vs JUNCTION TEMPERATURE
0.6 t r - Rise Time xVPP - ms
4.1
0.595
4.05
0.59
4
0.585
3.95
0.58
3.9
0.575 -50
-20 10 40 70 TJ - Junction Temperature - C
100
3.85 -50
-20 10 40 70 TJ - Junction Temperature - C
100
Figure 17.
Figure 18.
15
TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
www.ti.com
RISE TIME, xVCC vs LOAD CAPACITANCE
1.2 2.5
FALL TIME, xVCC vs LOAD CAPACITANCE
xVCC = 5 V IO = 0.75 A TJ = 25C
t r - Rise Time, xVCC - ms
0.8
t f - Fall Time xVCC - ms xVCC = 5 V IO = 0.75 A TJ = 25C
1
2
1.5
0.6
1
0.4
0.2
0.5
0 0.1
1 10 100 CL - Load Capacitance - F
1000
0 0.1
1 10 100 CL - Load Capacitance - F
1000
Figure 19. RISE TIME, xVPP vs LOAD CAPACITANCE
0.7 xVPP = 12 V IO = 0.05 A TJ = 25C t f - Fall Time, xVPP - ms 4.5 4 3.5 3 2.5 2 1.5 1 0.1 0 0.1 0.5 0 0.1 xVPP = 12 V IO = 0.05 A TJ = 25C
Figure 20. FALL TIME, xVPP vs LOAD CAPACITANCE
0.6 t r - Rise Time, xVPP - ms 0.5
0.4 0.3 0.2
1 CL - Load Capacitance - F
10
1 CL - Load Capacitance - F
10
Figure 21.
Figure 22.
16
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS Table of Graphs
FIGURE Input current, xVCC = 3.3 V II Input current, xVCC = 5 V Input current, xVPP = 12 V Static drain-source on-state resistance, 3.3 V to xVCC switch rDS(on) Static drain-source on-state resistance, 5 V to xVCC switch Static drain-source on-state resistance, 12 V to xVPP switch xVCC switch voltage drop, 3.3-V input VO xVCC switch voltage drop, 5-V input xVPP switch voltage drop, 12-V input Short-circuit current limit, 3.3 V to xVCC IOS Short-circuit current limit, 5 V to xVCC Short-circuit current limit, 12 V to xVPP vs Junction temperature vs Load current vs Junction temperature vs Junction temperature 23 24 25 26 27 28 29 30 31 32 33 34
INPUT CURRENT, xVCC = 3.3 V vs JUNCTION TEMPERATURE
180 160 I I - Input Current, xVCC = 3.3 V - A 140 120 100 80 60 40 20 0 -50 0 -50 I I - Input Current, xVCC = 5 V - A 14 12 10 8 6
INPUT CURRENT, xVCC = 5 V vs JUNCTION TEMPERATURE
4 2
-20 10 40 70 TJ - Junction Temperature - C
100
-20 10 40 70 TJ - Junction Temperature - C
100
Figure 23.
Figure 24.
17
TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
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INPUT CURRENT, xVPP = 12 V vs JUNCTION TEMPERATURE
rDS(on) - Static Drain-Source On-State Resistance, 3.3 V to xVCC Switch - 120
STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 3.3 V TO xVCC SWITCH vs JUNCTION TEMPERATURE
0.12
I I - Input Current, xVPP = 12 V - A
100
0.1
80
0.08
60
0.06
40
0.04
20
0.02
0 -50
-20 10 40 70 TJ - Junction Temperature - C
100
0 -50
-20 10 40 70 TJ - Junction Temperature - C
100
Figure 25. STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 5 V TO xVCC SWITCH vs JUNCTION TEMPERATURE
rDS(on) - Static Drain-Source On-State Resistance, 5 V to xVCC Switch - rDS(on) - Static Drain-Source On-State Resistance, 12 V to xVPP Switch - 0.14
Figure 26. STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 12 V TO xVPP SWITCH vs JUNCTION TEMPERATURE
3
0.12 0.1 0.08
2.5
2
1.5
0.06 0.04 0.02 0 -50
1
0.5
-20 10 40 70 TJ - Junction Temperature - C
100
0 -50
-20 10 40 70 TJ - Junction Temperature - C
100
Figure 27.
Figure 28.
18
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
xVCC SWITCH VOLTAGE DROP, 3.3-V INPUT vs LOAD CURRENT
0.12 VO - xVCC Switch Voltage Drop, 3.3-V Input - V VO - xVCC Switch Voltage Drop, 5-V Input - V 0.14 0.12
xVCC SWITCH VOLTAGE DROP, 5-V INPUT vs LOAD CURRENT
0.1
TJ = 100C TJ = 0C TJ = 25C
TJ = 100C 0.1 TJ = 0C 0.08 TJ = 25C 0.06 TJ = -40C 0.04 TJ = 85C 0.02
0.08
0.06 TJ = -40C 0.04 TJ = 85C 0.02
0
0
0.2
0.4 0.6 IL - Load Current - A
0.8
1
0
0
0.2
0.4 0.6 IL - Load Current - A
0.8
1
Figure 29. xVPP SWITCH VOLTAGE DROP, 12-V INPUT vs LOAD CURRENT
I OS - Short-Circuit Current Limit, 3.3 V to xVCC - A 0.14 VO - xVPP Switch Voltage Drop, 12-V Input - V 0.12 0.1 1.395 1.39 1.385 1.38 1.375 1.37 1.365 1.36 1.355 -50
Figure 30. SHORT-CIRCUIT CURRENT LIMIT, 3.3 V TO xVCC vs JUNCTION TEMPERATURE
TJ = 100C TJ = 0C TJ = 25C
0.08
0.06 0.04
TJ = -40C TJ = 85C
0.02
0
0
0.01
0.02 0.03 IL - Load Current - A
0.04
0.05
-20 10 40 70 TJ - Junction Temperature - C
100
Figure 31.
Figure 32.
19
TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
www.ti.com
SHORT-CIRCUIT CURRENT LIMIT, 5 V TO xVCC vs JUNCTION TEMPERATURE
I OS - Short-Circuit Current Limit, 12 V to xVPP - A 1.435 I OS - Short-Circuit Current Limit, 5 V to xVCC - A 1.43 1.425 1.42 1.415 1.41 1.405 1.4 1.395 1.39 1.385 -50 -20 10 40 70 TJ - Junction Temperature - C 100 0.208 0.206 0.204 0.202
SHORT-CIRCUIT CURRENT LIMIT, 12 V TO xVPP vs JUNCTION TEMPERATURE
xVPP = 12 V 0.2 0.198 0.196 0.194 0.192 0.19 -50 -20 10 40 70 TJ - Junction Temperature - C 100
Figure 33.
Figure 34.
20
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
APPLICATION INFORMATION OVERVIEW
PC Cards were initially introduced as a means to add flash memory to portable computers. The idea of add-in cards quickly took hold, and modems, wireless LANs, global positioning satellite system (GPS), multimedia, and hard-disk versions were soon available. As the number of PC Card applications grew, the engineering community quickly recognized the need for a standard to ensure compatibility across platforms. Therefore, the PCMCIA (Personal Computer Memory Card International Association) was established, comprising members from leading computer, software, PC Card, and semiconductor manufacturers. One key goal was to realize the plug-and-play concept, so that cards and hosts from different vendors would be transparently compatible.
PC CARD POWER SPECIFICATION
System compatibility also means power compatibility. The most current set of specifications (PC Card Standard) set forth by the PCMCIA committee states that power is to be transferred between the host and the card through eight of the 68 terminals of the PC Card connector. This power interface consists of two VCC, two Vpp, and four ground terminals. Multiple VCC and ground terminals minimize connector-terminal and line resistance. The two Vpp terminals were originally specified as separate signals, but are normally tied together in the host to form a single node to minimize voltage losses. Card primary power is supplied through the VCC terminals; flash-memory programming and erase voltage is supplied through the Vpp terminals. Cardbus cards of today typically do not use 12 V, which is now more of an optional requirement in the host.
DESIGNING FOR VOLTAGE REGULATION
The current PCMCIA specification for output voltage regulation, VO(reg), of the 5-V output is 5% (250 mV). In a typical PC power-system design, the power supply has an output-voltage regulation, VPS(reg), of 2% (100 mV). Also, a voltage drop from the power supply to the PC Card results from resistive losses, VPCB, in the PCB traces and the PCMCIA connector. A typical design would limit the total of these resistive losses to less than 1% (50 mV) of the output voltage. Therefore, the allowable voltage drop, VDS, for the TPS2220A, TPS2223A, TPS2224A, and TPS2226A would be the PCMCIA voltage regulation less the power supply regulation and less the PCB and connector resistive drops: V +V -V -V DS O(reg) PS(reg) PCB Typically, this would leave 100 mV for the allowable voltage drop across the 5-V switch. The specification for output voltage regulation of the 3.3-V output is 300 mV; therefore, using the same equation by deducting the voltage drop percentages (2%) for power-supply regulation and PCB resistive loss (1%), the allowable voltage drop for the 3.3-V switch is 200 mV. The voltage drop is the output current multiplied by the switch resistance of the device. Therefore, the maximum output current, IO max, that can be delivered to the PC Card in regulation is the allowable voltage drop across the IC, divided by the output-switch resistance. V I max + r DS O DS(on) The xVCC outputs have been designed to deliver the peak and average currents defined by the PC Card specification within regulation over the operating temperature range. The xVPP outputs of the device have been designed to deliver 100 mA continuously.
OVERCURRENT AND OVERTEMPERATURE PROTECTION
PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection against short-circuited cards that can lead to power-supply or PCB trace damage. Even extremely robust systems can undergo rapid battery discharge into a damaged PC Card, resulting in the sudden and unacceptable loss of system power. In comparison, the reliability of fused systems is poor because blown fuses require troubleshooting and repair, usually by the manufacturer. The TPS2220A, TPS2223A, TPS2224A, and TPS2226A take a two-pronged approach to overcurrent protection, which is designed to activate if an output is shorted or when an overcurrent condition is present when switches are powered up. First, instead of fuses, sense FETs monitor each of the xVCC and xVPP power outputs. Unlike
21
TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
www.ti.com
APPLICATION INFORMATION (continued)
sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore, voltage and power losses are reduced. Overcurrent sensing is applied to each output separately. Excessive current generates an error signal that limits the output current of only the affected output, preventing damage to the host. Each xVCC output overcurrent limits from 1 A to 2.2 A, typically around 1.6 A; the xVPP outputs limit from 100 mA to 250 mA, typically around 200 mA. Second, when an overcurrent condition is detected, the TPS2220A, TPS2223A, TPS2224A, and TPS2226A assert an active low OC signal that can be monitored by the microprocessor or controller to initiate diagnostics and/or send the user a warning message. If an overcurrent condition persists, causing the IC to exceed its maximum junction temperature, thermal-protection circuitry activates, shutting down all power outputs until the device cools to within a safe operating region, which is ensured by a thermal shutdown hysteresis. Thermal limiting prevents destruction of the IC from overheating beyond the package power-dissipation ratings. During power up, the devices control the rise times of the xVCC and xVPP outputs and limit the inrush current into a large load capacitance, faulty card, or connector.
12-V SUPPLY NOT REQUIRED
Some PC Card switches use the externally supplied 12 V to power gate drive and other chip functions, which requires that power be present at all times. The TPS2220A, TPS2224A and TPS2226A offer considerable power savings by using an internal charge pump to generate the required higher gate drive voltages from the 3.3-V input. Therefore, the external 12-V supply can be disabled except when needed by the PC Card in the slot, thereby extending battery lifetime. A special feature in the 12-V circuitry actually helps to reduce the supply current demanded from the 3.3-V input. When 12 V is supplied and requested at the VPP output, a voltage selection circuit draws the charge-pump drive current for the 12-V FETs from the 12-V input. This selection is automatic and effectively reduces demand fluctuations on the normal 3.3-V VCC rail. For proper operation of this feature, a minimum 3.3-V input capacitance of 4.7 F is recommended, and a minimum 12-V input ramp-up rate of 12 V/50 ms (240 V/s) is required. Additional power savings are realized during a software shutdown in which quiescent current drops to a maximum of 1 A.
VOLTAGE-TRANSITIONING REQUIREMENT
PC Cards, like portables, are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space, and increase logic speeds. The TPS2220A, TPS2223A, TPS2224A, and TPS2226A meet all combinations of power delivery as currently defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering the card with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the capacitors on 3.3-V-compatible cards be discharged to below 0.8 V before applying 3.3-V power. This action ensures that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power reset. PC Card specification requires that VCC be discharged within 100 ms. PC Card resistance cannot be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible high-impedance isolation by power-management schemes. The devices include discharge transistors on all xVCC and xVPP outputs to meet the specification requirement.
SHUTDOWN MODE
In the shutdown mode, which can be controlled by SHDN or bit D8 of the input serial DATA word, each of the xVCC and xVPP outputs is forced to a high-impedance state. In this mode, the chip quiescent current is reduced to 1 A or less to conserve battery power.
POWER-SUPPLY CONSIDERATIONS
These switches have multiple pins for each 3.3-V (except for TPS2220A) and 5-V power input and for the switched xVCC outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel, the series resistance is higher than that specified, resulting in increased voltage drops and power loss. It is recommended that all input and output power pins be paralleled for optimum operation. To increase the noise immunity of the TPS2220A, TPS2223A, TPS2224A, and TPS2226A, the power-supply inputs should be bypassed with at least a 4.7-F electrolytic or tantalum capacitor paralleled by a 0.047-F to
22
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
APPLICATION INFORMATION (continued)
0.1-F ceramic capacitor. It is strongly recommended that the switched outputs be bypassed with a 0.1-F (or larger) ceramic capacitor; doing so improves the immunity of the IC to electrostatic discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the devices and the load. High switching currents can produce large negative voltage transients, which forward biases substrate diodes, resulting in unpredictable performance. Similarly, no pin should be taken below -0.3 V.
RESET INPUT
To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should be reset at the same time as the host by applying low-impedance paths from xVCC and xVPP terminals to ground. A low-impedance output state allows discharging of residual voltage remaining on PC Card filter capacitance, permitting the system (host and PC Cards) to be powered up concurrently. The active low RESET input closes internal ground switches S1, S4, S7, and S11 with all other switches left open. The TPS2220A, TPS2223A, TPS2224A, and TPS2226A remain in the low-impedance output state until the signal is deasserted and further data is clocked in and latched. The input serial data cannot be latched during reset mode. RESET is provided for direct compatibility with systems that use an active-low reset voltage supervisor. The RESET pin has an internal 150-k pullup resistor.
CALCULATING JUNCTION TEMPERATURE
The switch resistance, rDS(on), is dependent on the junction temperature, TJ, of the die. The junction temperature is dependent on both rDS(on) and the current through the switch. To calculate TJ, first find rDS(on) from Figure 26 through Figure 28, using an initial temperature estimate about 30C above ambient. Then, calculate the power dissipation for each switch, using the formula: P +r I2 D DS(on) Next, sum the power dissipation of all switches and calculate the junction temperature:
T+ P R )T J D qJA A where: RJA is the inverse of the derating factor given in the dissipation rating table.
Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not within a few degrees of each other, recalculate using the calculated temperature as the initial estimate.
LOGIC INPUTS AND OUTPUTS
The serial interface consists of the DATA, CLOCK, and LATCH leads. The data is clocked in on the positive edge of the clock (see Figure 2). The 11-bit (D0-D10) serial data word is loaded during the positive edge of the latch signal. The positive edge of the latch signal should occur before the next positive edge of the clock occurs. The serial interface of the device is compatible with serial-interface PCMCIA controllers. An overcurrent output (OC) is provided to indicate an overcurrent or overtemperature condition in any of the xVCC and xVPP outputs as previously discussed.
23
TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
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APPLICATION INFORMATION (continued) TPS2220A, TPS2223A, TPS2224A, and TPS226A CONTROL LOGIC
xVPP AVPP CONTROL SIGNALS D8 (SHDN) 1 1 1 1 1 0 D0 0 0 0 1 1 X D1 0 1 1 0 1 X D9 X 0 1 X X X OUTPUT V_AVPP 0V 3.3 V 5V 12 V (1) Hi-Z Hi-Z BVPP CONTROL SIGNALS D8 (SHDN) 1 1 1 1 1 0 D4 0 0 0 1 1 X D5 0 1 1 0 1 X D10 X 0 1 X X X OUTPUT V_BVPP 0V 3.3 V 5V 12 V (1) Hi-Z Hi-Z
(1) The output V_xVPP is Hi-Z forTPS2223A. xVCC AVCC CONTROL SIGNALS D8 (SHDN) 1 1 1 1 0 D3 0 0 1 1 X D2 0 1 0 1 X OUTPUT V_AVCC 0V 3.3 V 5V 0V Hi-Z BVCC CONTROL SIGNALS D8 (SHDN) 1 1 1 1 0 D6 0 0 1 1 X D7 0 1 0 1 X OUTPUT V_BVCC 0V 3.3 V 5V 0V Hi-Z
24
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TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
ESD PROTECTIONS (see Figure 35)
All inputs and outputs of these devices incorporate ESD-protection circuitry designed to withstand a 2-kV human-body-model discharge as defined in MIL-STD-883C, Method 3015. The xVCC and xVPP outputs can be exposed to potentially higher discharges from the external environment through the PC Card connector. Bypassing the outputs with 0.1-F capacitors protects the devices from discharges up to 10 kV.
TPS2226A AVCC 0.1 F AVCC VCC VCC PC Card Connector A AVPP 0.1 F Vpp1 Vpp2
12 V
4.7 F
0.1 F
12 V 12 V 5V 5V 5V
BVCC 0.1 F BVCC
VCC VCC PC Card Connector B
5V 4.7 F 0.1 F
BVPP
0.1 F
Vpp1 Vpp2
3.3 V
4.7 F
0.1 F
3.3 V 3.3 V 3.3 V DATA CLOCK LATCH RESET OC From PCI or System RST GPI/O Controller DATA CLOCK LATCH
Maximum recommended output capacitance for xVCC is 220 F including card capacitance, and for xVPP is 10 F, without OC glitch when switches are powered on.
Figure 35. Detailed Interconnections and Capacitor Recommendations
25
TPS2220A, TPS2223A TPS2224A, TPS2226A
SLVS428B - MAY 2002 - REVISED SEPTEMBER 2004
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12-V FLASH MEMORY SUPPLY
The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 mA from inputs as low as 2.7 V. The device is pin-for-pin compatible with the MAX734 regulator and offers the following advantages: lower supply current, wider operating input-voltage range, and higher output currents. As shown in Figure 36, the only external components required are: an inductor, a Schottky rectifier, an output filter capacitor, an input filter capacitor, and a small capacitor for loop compensation. The entire converter occupies less than 0.7 in2 of PCB space when implemented with surface-mount components. An enable input is provided to shut the converter down and reduce the supply current to 3 A when 12 V is not needed. The TPS6734 is a 170-kHz current-mode PWM (pulse-width modulation) controller with an n-channel MOSFET power switch. Gate drive for the switch is derived from the 12-V output after start-up to minimize the die area needed to realize the 0.7- MOSFET and improve efficiency at input voltages below 5 V. Soft start is accomplished with the addition of one small capacitor. A 1.22-V reference, pin 2 of TPS6734, is brought out for external use. For additional information, see the TPS6734 data sheet (SLVS127).
3.3 V or 5 V Enable (see Note A) R1 10 k TPS6734 EN REF SS COMP VCC FB OUT GND TPS2226A or TPS2224A 1 2 C1 33 F 20 V + 3 4 C2 0.01 F 8 7 6 5 D1 33 F, 20 V + C1 L1 18 H AVCC AVCC AVCC AVPP
12 V 0.1 F
12 V 12 V BVCC BVCC
C4 0.001 F
5V 1 F 0.1 F
5V 5V 5V
BVCC BVPP
3.3 V
4.7 F
0.1 F
3.3 V 3.3 V 3.3 V DATA CLOCK LATCH SHDN RESET OC
Not on TPS2224A
NOTE A: The enable terminal can be tied to a general-purpose I/O terminal on the PCMCIA controller or tied high.
Figure 36. TPS2224A and TPS2226A with TPS6734 12-V, 120-mA Supply
26
THERMAL PAD MECHANICAL DATA
www.ti.com
PWP (R-PDSO-G24)
THERMAL INFORMATION
This PowerPADTM package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. When the thermal pad is soldered directly to the printed circuit board (PCB), the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC). For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities, refer to Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 and Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004. Both documents are available at www.ti.com. The exposed thermal pad dimensions for this package are shown in the following illustration.
24
13
Exposed Thermal Pad
2,40 1,65
1
12
5,16 4,10
Top View NOTE: All linear dimensions are in millimeters
PPTD030
Exposed Thermal Pad Dimensions
PowerPAD is a trademark of Texas Instruments
MECHANICAL DATA
MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001
DB (R-PDSO-G**)
28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 1 A 14 0- 8 0,25 0,95 0,55
Seating Plane 2,00 MAX 0,05 MIN 0,10
PINS ** DIM A MAX
14
16
20
24
28
30
38
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 /E 12/01
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless

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