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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13504-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16F MB90230 Series
MB90233/234/P234/W234
s DESCRIPTION
The MB90230 series is a member of general-purpose, 16-bit microcontrollers designed for those applications which require high-speed realtimeprocessing, proving to be suitable for various industrial machines, camera and video devices, OA equipment, and for process control. The CPU used in this series is the F2MC*-16F. The instruction set for the F2MC-16F CPU core is designed to be optimized for controller applications while inheriting the AT architecture of the F2MC-16/16H series, allowing a wide range of control tasks to be processed efficiently at high speed. The peripheral resources integrated in the MB90230 series include: the UART (clock asynchronous/synchronous transfer) x 1 channel, the extended serial I/O interface x 1 channel, the A/D converter (8/10-bit precision) x 8 channels, the D/A converter (8-bit precision) x 2 channels, the level comparator x 1 channel, the external interrupt input x 4 lines, the 8-bit PPG timer (PWM/single-shot function) x 1 channel, the 8-bit PWM controller x 6 channels, the 16-bit free run timer x 1 channel, the input capture unit x 4 channels, the output compare unit x 6 channels, and the serial E2PROM interface. *: F2MC stands for FUJITSU Flexible Microcontroller.
s FEATURES
F2MC-16F CPU block
* Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz) * Instruction set optimized for controllers Various data types supported (bit, byte, word, and long-word) Extended addressing modes: 23 types High coding efficiency Higher-precision operation enhanced by a 32-bit accumulator Signed multiplication and division instructions
(Continued)
s PACKAGE
100-pin Plastic LQFP 100-pin Ceramic LQFP
(FPT-100P-M05)
(FPT-100C-C01)
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MB90230 Series
(Continued) * Enhanced instructions applicable to high-level language (C) and multitasking System stack pointer Enhanced pointer-indirect instructions Barrel shift instructions * Increased execution speed: 8-byte instruction queue * 8-level, 32-factor powerful interrupt service functions * Automatic transfer function independent of the CPU (EI2OS) * General-purpose ports: Up to 84 lines Ports with input pull-up resistor available: 24 lines Ports with output open-drain available: 9 lines
Peripheral blocks
* ROM:48 Kbytes (MB90233) 96 Kbytes (MB90234) EPROM: 96 Kbytes (MB90W234) One-time PROM: 96 Kbytes (MB90P234) * RAM: 2 Kbytes (MB90233) 3 Kbytes (MB90234/W234/P234) * PWM control circuit: (simple 8 bits): 6 channels * Serial interface UART: 1 channel Extended serial I/O interface Switchable I/O port: 1 channel Communication prescaler (Source clock generator for the UART, serial I/O interface, CKOT, and level comparator): 1 channel * Serial E2PROM interface: 1 channel * A/D converter with 8/10-bit resolution: input 8 channels * Level comparator: 1 channel 4-bit D/A converter integrated * D/A converter with 8-bit resolution: 2 channels 8-bit PPG timer: 1 channel * Input/output timer 16-bit free run timer: 1 channel 16-bit output compare unit: 6 channels 16-bit input capture unit: 4 channels * 18-bit timebase timer * Watchdog timer function * Standby modes Sleep mode Stop mode
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MB90230 Series
s PRODUCT LINEUP
Part number Parameter
MB90233
NB90234
MB90P234 One-time PROM model 96 Kbytes 3 Kbytes
MB90W234 EPROM model 96 Kbytes 3 Kbytes
MB90V230 Evaluation model -- 4 Kbytes
Classification ROM size RAM size CPU functions
Mask ROM products 48 Kbytes 2 Kbytes 96 Kbytes 3 Kbytes
Number of instructions: 420 Instruction bit length: 8 or 16 bits Instruction length: 1 to 7 bytes Data bit length: 1, 4, 8, 16, or 32 bits Minimum execution time: 62.5 ns at 16 MHz (internal) Up to 84 lines I/O ports (CMOS): 51 I/O ports (CMOS) with pull-up resistor available: 24 I/O ports (open-drain): 9 Number of channels: 1 (switchable I/O) Clock synchronous communication (2404 to 38460 bps, full-duplex double buffering) Clock asynchronous communication (500K to 5M bps, full-duplex double buffering) Number of channels: 1 Internal or external clock mode Clock synchronous transfer (62.5 kHz to 1 MHz, "LSB first" or "MSB first" transfer) Resolution: 10 or 8 bits, Number of input lines: 4 Single conversion mode (conversion for a specified input channel) Scan conversion mode (continuous conversion for specified consecutive channels) Continuous conversion mode (repeated conversion for a specified channel) Stop conversion mode (periodical conversion) Resolution: 8 bits, Number of output pins: 2 Comparison to internal D/A converter (4-bit resolution) Number of channels: 6 8-bit PWM control circuit (operation of 1x, 2x, 16x, 32x) Number of channels: 1 channel with 8-bit resolution PWM function: Continuous output of pulse synchronous to trigger Single-shot function: Output of single pulse by trigger Number of channels: 1 Instruction code (NS type) Variable address length: 8 to 11 bits (with address increment function) Variable data length: 8 or 16 bits Number of channels: 6 16-bit reload timer operation (operation clock cycle of 0.25 s to 1.05 s) Number of channels: 1 16-bit input capture unit: 4 channels 16-bit output compare unit: 6 channels Number of input pins: 4 Stop mode and sleep mode FPT-100P-M05 FPT-100C-C01 PGA256-A02
Ports
UART
Serial interface
A/D converter
D/A converter Level comparator PWM PPG timer
Serial E2PROM interface
Timer Free run timer
External interrupt input Standby mode Package
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MB90230 Series
s PIN ASSIGNMENT
(TOP VIEW)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P21/A01 P20/A00 P17/D15 P16/D14 P15/D13 P14/D12 P13/D11 P12/D10 P11/D09 P10/D08 P07/D07 P06/D06 P05/D05 P04/D04 P03/D03 P02/D02 P01/D01 P00/D00 VCC X1 X0 VSS P57 P56/RD P55/WRL
P22/A02 P23/A03 P24/A04 P25/A05 P26/A06 P27/A07 P30/A08 P31/A09 VSS P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 PWM0/P40/A16 PWM1/P41/A17 PWM2/P42/A18 PWM3/P43/A19 PWM4/P44/A20 VCC PWM5/P45/A21 TRG/P46/A22 PPG/P47/A23 ATG/P70
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
RST P54/WRH P53/HRQ P52/HAK P51/RDY P50/CLK PA5/SCK2 PA4/SOT2 PA3/SIN2 PA2/SCK1 PA1/SOT1 PA0/SIN1 P96/SCK0 P95/SOT0 P94/SIN0 P93/IN3/CKOT P92/IN2 P91/IN1 P90/IN0 P87/OUT5 P86/OUT4 P85/OUT3 P84/OUT2 P83/OUT1/INT3 P82/OUT0/INT2
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P71/EDI P72/EDO P73/ESK P74/ECS P75/DA0 P76/DA1 AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7/CMP P80/INT0 P81/INT1 MD0 MD1 MD2 HST
(FPT-100P-M05) (FPT-100C-C01)
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MB90230 Series
s PIN DESCRIPTION
Pin no. 80 81 82 83 to 90 X0 X1 VCC P00 to P07 -- G Power supply pin General-purpose I/O port An input pull-up resistor can be added to the port by setting the pull-up resistor setting register. These pins serve as D00 to D07 pins in bus modes other than the single-chip mode. I/O pins for the lower eight bits of the external data bus. These pins are enabled in an external-bus enabled mode. G General-purpose I/O port An input pull-up resistor can be added to the port by setting the pull-up resistor setting register. These pins are enabled in the single-chip mode with the external-bus enabled and the 8-bit data bus specified. I/O pins for the upper eight bits of the external data bus These pins are enabled in an external-bus enabled mode with the 16bit data bus specified. G General-purpose I/O port An input pull-up resistor can be added to the port by setting the pull-up resistor setting register. These pins are enabled in the single-chip mode. I/O pins for the lower eight bits of the external data bus These pins are enabled in an external-bus enabled mode. E General-purpose I/O port This port is enabled in the single-chip mode or when the middle address control register setting is "port." I/O pins for the middle eight bits of the external data bus These pins are enabled in an external-bus enabled mode when the middle address control register setting is "address." -- E Power supply pin General-purpose I/O port This port is enabled in the single-chip mode or when the middle address control register setting is "port." I/O pins for the middle eight bits of the external data bus These pins are enabled in an external-bus enabled mode when the middle address control register setting is "address." Pin name Circuit type A Oscillator pins Function
D00 to D07 91 to 98 P10 to P17
D08 to D15
99, 100 1 to 6
P20 to P27
A00 to A07 7, 8 P30, P31
A08, A09
9 10 to 15
VSS P32 to P37
A10 to A15
(Continued)
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MB90230 Series
Pin no. 16
Pin name P40
Circuit type E
Function General-purpose I/O port This port is enabled in the single-chip mode or when the upper address control register setting is "port." Output pin for external address A16 This pin is enabled in the external-bus enabled mode with the upper address control register set to "address." This pin serves as the output pin for 8-bit PWM0 The pin is enabled for output by the control status register.
A16
PWM0 17 P41 E
General-purpose I/O port This port is enabled in the single-chip mode or when the upper address control register setting is "port." Output pin for external address A17 This pin is enabled in the external-bus enabled mode with the upper address control register set to "address." This pin serves as the output pin for 8-bit PWM1. The pin is enabled for output by the control status register.
A17
PWM1 18 P42 E
General-purpose I/O port This port is enabled in the single-chip mode or when the upper address control register setting is "port." Output pin for external address A18 This pin is enabled in the external-bus enabled mode with the upper address control register set to "address." This pin serves as the output pin for 8-bit PWM2. This pin is enabled for output by the control status register.
A18
PWM2 19 P43 E
General-purpose I/O port This port is enabled in the single-chip mode or when the upper address control register setting is "port." Output pin for external address A19 This pin is enabled in the external-bus enabled mode with the upper address control register set to "address." This pin serves as the output pin for 8-bit PWM3. This pin is enabled for output by the control status register.
A19
PWM3 20 P44 E
General-purpose I/O port This port is enabled in the single-chip mode or when the upper address control register setting is "port." Output pin for external address A20 This pin is enabled in the external-bus enabled mode with the upper address control register set to "address." This pin serves as the output pin for 8-bit PWM4. The pin is enabled for output by the control status register.
A20
PWM4 21 VCC --
Power supply pin
(Continued)
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MB90230 Series
Pin no. 22
Pin name P45
Circuit type E
Function General-purpose I/O port This port is enabled in the single-chip mode or when the upper address control register setting is "port." Output pin for external address A21 This pin is enabled in the external-bus enabled mode with the upper address control register set to "address." This pin serves as the output pin for 8-bit PWM5. The pin is enabled for output by the control status register.
A21
PWM5 23 P46 L*1
General-purpose I/O port This port is enabled in the single-chip mode or when the upper address control register setting is "port." Output pin for external address A22 This pin is enabled in the external-bus enabled mode with the upper address control register set to "address." This pin serves as the external trigger pin for the 8-bit PPG timer The pin is enabled for triggering by the control status register.
A22
TRG 24 P47 E
General-purpose I/O port This port is enabled in the single-chip mode or when the upper address control register setting is "port." Output pin for external address A23 This pin is enabled in the external-bus enabled mode with the upper address control register set to "address." This pin serves as the output pin for the 8-bit PPG timer. The pin is enabled for output by the control status register.
A23
PPG 25 P70 ATG 26 P71 EDI 27 P72 EDO 28 P73 ESK 29 P74 ECS E E E F L*1
General-purpose I/O port External trigger input pin for the A/D converter This pin functions when enabled by the control status register. General-purpose I/O port Data input pin for the serial EEPROM interface This pin functions when enabled by the control status register. General-purpose I/O port Data output pin for the serial EEPROM interface This pin functions when enabled by the control status register. General-purpose I/O port Clock output pin for the serial EEPROM interface This pin functions when enabled by the control status register. General-purpose I/O port Chip select signal output pin for the serial EEPROM interface This pin functions when enabled by the control status register.
(Continued)
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MB90230 Series
Pin no. 30, 31
Pin name P75, P76 DA0 DA1
Circuit type K General-purpose I/O port
Function
This pin serves as the D/A converter output pin. The pin functions when enabled by the control status register. -- -- -- -- J A/D converter power supply pin "H" reference power supply pin for the A/D converter "L" reference power supply pin for the A/D converter A/D converter power pin (GND) General-purpose I/O port This port is enabled when the analog input enable register setting is "port." A/D converter analog input pins These pins are enabled when the analog input enable register setting is "analog input." -- J Power pin (GND) General-purpose I/O port This port is enabled when the analog input enable register setting is "port." A/D converter analog input pins These pins are enabled when the analog input enable register setting is "analog input." J General-purpose I/O port This port is enabled when the analog input enable register setting is "port." A/D converter analog input pin This pin is enabled when the analog input enable register setting is "analog input." Comparator input pin L*2 General-purpose I/O port This port is always enabled. External interrupt request input 0 Since this pin serves for interrupt request as required when external interrupt is enabled, other outputs must be off unless used intentionally. L*2 General-purpose I/O port This port is always enabled. External interrupt request input 1 Since this pin serves for interrupt request as required when external interrupt is enabled, other outputs must be off unless used intentionally. C C Mode pin This pin must be fixed to VCC or VSS. Mode pin This pin must be fixed to VCC or VSS.
32 33 34 35 36 to 39
AVCC AVRH AVRL AVSS P60 to P63
AN0 to AN3
40 41 to 43
VSS P64 to P66
AN4 to AN6
44
P67
AN7
CMP 45 P80 INT0
46
P81 INT1
47 48
MD0 MD1
(Continued)
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MB90230 Series
Pin no. 49 50 51, 52
Pin name MD2 HST P82, P83 OUT0, OUT1 INT2, INT3
Circuit type C D L*
2
Function Mode pin This pin must be fixed to VSS. Hardware standby input pin General-purpose I/O port Output compare output pins These pins function when enabled by the control status register. External interrupt request inputs 2 and 3. Since these pins serve for interrupt request as required when external interrupt is enabled, other outputs must be off unless used intentionally.
53 to 56
P84 to P87 OUT2 to OUT5
E
General-purpose I/O port This pin is always enabled. Output compare output pins These pins function when enabled by the control status register.
57 to 59
P90 to P92 IN0 to IN2
L*1
General-purpose I/O port This port is always enabled. Input capture edge input pins These pins function when enabled by the control status register.
60
P93 IN3 CKOT
L*1
General-purpose I/O port This port is always enabled. Input capture edge input pin This pin functions when enabled by the control status register. Prescaler output pin This pin functions when enabled by the control status register.
61
P94
I
General-purpose I/O port This port is always enabled. The port serves as an open-drain output depending on the open-drain setting register. Serial data input pin for the UART This pin functions when enabled by the control status register.
SIN0 62 P95 H
General-purpose I/O port This port is always enabled. The port serves as an open-drain output depending on the open-drain setting register. Serial data output pin for the UART This pin functions when enabled by the control status register.
SOT0 63 P96 I
General-purpose I/O port This port is always enabled. The port serves as an open-drain output depending on the open-drain setting register. UART clock output pin This pin functions when enabled by the control status register.
SCK0
(Continued)
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MB90230 Series
Pin no. 64
Pin name PA0
Circuit type I
Function General-purpose I/O port This port is always enabled. The port serves as an open-drain output depending on the open-drain setting register. Serial data input pin for the extended serial I/O interface This pin functions when enabled by the control status register and by the serial port switching register.
SIN1
65
PA1
H
General-purpose I/O port This port is always enabled. The port serves as an open-drain output depending on the open-drain setting register. Serial data output pin for the extended serial I/O interface This pin functions when enabled by the control status register and by the serial port switching register.
SOT1
66
PA2
I
General-purpose I/O port This port is always enabled. The port serves as an open-drain output depending on the open-drain setting register. Clock output pin for the extended serial I/O interface This pin functions when enabled by the control status register and by the serial port switching register.
SCK1
67
PA3
I
General-purpose I/O port This port is always enabled. The port serves as an open-drain output depending on the open-drain setting register. Serial data input pin for the extended serial I/O interface This pin functions when enabled by the control status register and by the serial port switching register.
SIN2
68
PA4
H
General-purpose I/O port This port is always enabled. The port serves as an open-drain output depending on the open-drain setting register. Serial data output pin for the extended serial I/O interface This pin functions when enabled by the control status register and by the serial port switching register.
SOT2
69
PA5
I
General-purpose I/O port This port is always enabled. The port serves as an open-drain output depending on the open-drain setting register. Clock output pin for the extended serial I/O interface This pin functions when enabled by the control status register and by the serial port switching register. The pin is a general-purpose I/O port.
SCK2
(Continued)
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MB90230 Series
(Continued)
Pin no. 70 Pin name P50 CLK Circuit type H Function This pin is enabled in the single-chip mode and when the CLK output is disabled. CLK output pin This pin is enabled in an external-bus enabled mode with the CLK output enabled. F General-purpose I/O port This port is enabled in the single-chip mode. Ready signal input pin This pin is enabled in an external-bus enabled mode. E General-purpose I/O port This port is enabled in the single-chip mode or when the hold function is disabled. Hold acknowledge signal output pin This pin is enabled in the single-chip mode or when the hold function is enabled. E General-purpose I/O port This port is enabled in the single-chip mode or when the hold function is disabled. Hold acknowledge signal output pin This pin is enabled in the single-chip mode or when the hold function is enabled. E General-purpose I/O port This port is enabled in the single-chip mode, in external-bus 8-bit mode, or when the WR pin output is disabled. Write strobe output pin for the upper eight bits of the data bus This pin is enabled in an external-bus enabled mode and in external bus 16-bit mode with the WR pin output enabled. B E Reset signal input pin This port is enabled in the single-chip mode, in external-bus 8-bit mode, or when the WR pin output is disabled Write strobe output pin for the lower eight bits of the data bus This pin is enabled in an external-bus enabled mode and in external bus 16-bit mode with the WR pin output enabled. The pin is a general-purpose I/O port. E This pin is enabled in the single-chip mode. Read strobe output pin for the data bus This pin is enabled in an external-bus enabled mode. E -- General-purpose I/O port Power pin (GND)
71
P51 RDY
72
P52
HAK
73
P53
HRQ
74
P54
WRH
75 76
RST P55 WRL
77
P56 RD
78 79
P57 VSS
*1: Enabled in any standby mode *2: Enabled only in the hardware standby mode
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MB90230 Series
s I/O CIRCUIT TYPE
Type A Circuit Remarks * Oscillation feedback resistor: Approx. 1 M
X1
X0
Standby control
B
* Hysteresis input with pull-up resistor
C
* CMOS input port
D
* Hysteresis input port
E
* CMOS level output
CMOS Standby control
(Continued)
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MB90230 Series
Type F
Circuit
Remarks * CMOS level output * Hysteresis input
Standby control
G
Pull-up control
* Input pull-up resistor control provided * CMOS level input/output
CMOS Standby control
H
* CMOS level input/output * Open-drain control provided
Open-drain control signal
CMOS Standby control
(Continued)
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MB90230 Series
(Continued)
Type I
Open-drain control signal
Circuit
Remarks * CMOS level output * Hysteresis input * Open-drain control provided
CMOS Standby control
J
* CMOS level input/output * Analog input
Analog input CMOS Standby control
K
* CMOS level input/output * Analog output * Also serving for D/A output
DA output CMOS Standby control
L
Open-drain control signal
* CMOS level output * Hysteresis input * Open-drain control provided
Standby control
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MB90230 Series
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage wihich shows on "1. Absolute Maximum Ratings" in section "s Electrical Characteristics" is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor.
3. External Reset Input
To reset the internal circuit by the Low-level input to the RST pin, the Low-level input to the RST pin must be maintained for at least five machine cycles. Pay attention to it if the chip uses external clock input.
4. VCC and VSS Pins
Apply equal potential to the VCC and VSS pins.
5. Notes on Using an External Clock
When using an external clock, drive the X0 pin as illustrated below: Use of External Clock
X0 MB90234
X1
6. Power-on Sequence for A/D Converter Power Supplies and Analog Inputs
Be sure to turn on the digital power supply (VCC) before applying voltage to the A/D converter power supplies (AVCC, AVRH, and AVRL) and analog inputs (AN0 to AN15). When turning power supplies off, turn off the A/D converter power supplies (AVCC, AVRH, and AVRL) and analog inputs (AN0 to AN15) first, then the digital power supply (AVCC). When turning AVRH on or off, be careful not to let it exceed AVCC.
7. Pin set when turning on power supplies
When turning on power supplies, set the hardware standby input pin (HST) to "H". 15
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MB90230 Series
8. Program Mode
When shipped from Fujitsu, and after each erasure, all bits (96K x 8 bits) in the MB90W234 and MB90P234 are in the "1" state. Data is introduced by selectively programming "0's" into the desired bit locations. Bits cannot be set to 1 electrically.
9. Erasure Procedure
Data written in the MB90W234 is erased (from 0 to 1) by exposing the chip to ultraviolet rays with a wavelength of 2,537A through the translucent cover. Recommended irradiation dosage for exposure is 10 Wsec/cm2. This amount is reached in 15 to 20 minutes with a commercial ultraviolet lamp positioned 2 to 3 cm above the package (when the package surface illuminance is 1200 W/cm2). If the ultraviolet lamp has a filter, remove the filter before exposure. Attaching a mirrored plate to the lamp increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. If the translucent part of the package is stained with oil or adhesive, transmission of ultraviolet rays is degraded, resulting in a longer erasure time. In that case, clean the translucent part using alcohol (or other solvent not affecting the package). The above recommended dosage is a value which takes the guard band into consideration and is a multiple of the time in which all bits can be evaluated to have been erased. Observe the recommended dosage for erasure; the purpose of the guard band is to ensure erasure in all temperature and supply voltage ranges. In addition, check the lifespan of the lamp and control the illuminance appropriately. Data in the MB90W234 is erased by exposure to light with a wavelength of 4000A or less. Data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure results in a much lower erasure rate than exposure to 2537A ultraviolet rays. Note that exposure to such lights for an extended period will therefore affect system reliability. If the chip is used where it is exposed to any light with a wavelength of 4000A or less, cover the translucent part, for example, with a protective seal to prevent the chip from being exposed to the light. Exposure to light with a wavelength of 4,000 to 5,000A or more will not erase data in the device. If the light applied to the chip has a very high illuminance, however, the device may cause malfunction in the circuit for reasons of general semiconductor characteristics. Although the circuit will recover normal operation when exposure is stopped, the device requires proper countermeasures for use in a place exposed continuously to such light even though the wavelength is 4,000A or more.
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MB90230 Series
10. Recommended Screening Conditions
High-temperature aging is recommended for screening before packaging.
Program, verify
Aging +150C, 48 Hrs.
Data verification
Assembly
11. Write Yield
OTPROM products cannot be write-tested for all bits due to their nature. Therefore the write yield cannot always be guaranteed to be 100%.
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MB90230 Series
s BLOCK DIAGRAM
X0, X1 RST HST
4
Clock controller
CPU F2MC |16F Interrupt controller
RAM INT0 ROM External interrupt 4
@ @to
INT3
F2MC-16 bus
SIN0 SOT0 SCK0
UART 8-bit PWM 6 ch
PWM0
@ @ to
PWM5
CKOT
Communication prescaler
8-bit PPG timer
TRG PPG
SIN1, 2 SOT1, 2 SCK1, 2
Extended serial I/O interface
I/O timer 16-bit input capture x 4 16-bit free run timer 16-bit output compare x 6 IN0, 1 IN2, 3 OUT0, 1 OUT2, 3 OUT4, 5 2 Serial E2PROM interface ECS, ESK EDO EDI
AVcc AVRH, AVRL AVss ATG AN0 to AN7
10-bit A/D converter
DA0 DA1
D/A converter
Level comparator
CMP
I/O ports (84 lines) 8 P00 to P07 8 P10 to P17 8 P20 to P27 8 P30 to P37 8 P40 to P47 8 P50 to P57 8 P60 to P67 7 P70 to P76 8 P80 to P87 7 P90 to P96 6 PA0 to PA5
P00 to P27 (24 lines): Provided with input pull-up resistor setting registers P94 to P96, PA0 to PA5 (9 lines): Provided with open-drain setting registers
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MB90230 Series
s MEMORY MAP
FFFFFFH
Single-chip mode ROM area
Internal ROM and external bus ROM area
External ROM and external bus
Address1#
00FFFFH ROM area (FF bank image) ROM area (FF bank image)
Address#2
Address#3 RAM 000100H 0000C0H 000000H Peripherals Peripherals Peripherals Registers RAM Registers RAM Registers
Internal
External
Inhibited area
Note: 000000H to 000005H and 000010H to 000015H are allocated for external use when the external bus is enabled. Product type MB90233 MB90234 MB90P234 MB90W234 MB90V230 Address#1 FF4000H FE8000H FE8000H (FE0000H) Address#2 004000H 004000H 004000H (004000H) Address#3 000900H 000D00H 000D00H (001100H)
The MB90230 series can access the 00 bank to read ROM data written to the upper 48-KB locations in the FF bank. An advantage of reading written to data addresses FFFFFFH-FF4000H from addresses 00FFFFH-004000H is that you can use the small model of a C compiler. Note, however, that the products with more than 48KB ROM space (MB90V230, MB90P/W234, MB90234) cannot read data in addresses other than FFFFFFH to FF4000H from the 00 bank.
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MB90230 Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Port 0 resistor register Port 1 resistor register Port 2 resistor register Port 9 pin register Port A pin register Mode control register Status register Serial input register /Serial output register Rate and data register Serial mode control status register Register name PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA RDR0 RDR1 RDR2 ODR9 ODRA UMC USR UIDR /UODR URD SMCS Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Extended serial I/O interface Resouce name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 0 Port 1 Port 2 Port 9 Port A UART Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX - XXXXXXX XXXXXXXX - XXXXXXX - - XXXXXX 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -0000000 00000000 -0000000 --000000 00000000 00000000 00000000 -000---- --000000 00000100 00010000 XXXXXXXX 0000--00 ---00000 00000010
(Continued)
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MB90230 Series
Address 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H
Register Serial data register Reserved area Cycle setting register Duty factor setting register Control status register Reserved area Communication prescaler Clock control register Level comparator Interrupt/DTP enable register Interrupt/DTP factor register Request level setting register Reserved area Analog input enable register Reserved area Control status data register Data register Reserved area Reserved area D/A converter data register 0 D/A converter data register 1 D/A control register Reserved area PWM data register 0 PWM data register 1 Control status data register 0, 1 Reserved area PWM data register 2 PWM data register 3 Control status register 2, 3
Register name SDR -- PCSR PDUT PCNTL PCNTH -- CDCR CLKR LVLC ENIR EIRR ELVR -- ADER -- ADCS0 ADCS1 ADCR0 ADCR1 -- -- DAT0 DAT1 DACR -- PWD0 PWD1 PWC01 -- PWD2 PWD3 PWC23
Access R/W -- W W R/W -- R/W R/W R/W R/W R/W R/W -- R/W -- R/W R -- -- R/W R/W R/W -- R/W R/W R/W -- R/W R/W R/W
Resouce name Extended serial I/O interface -- 8-bit PPG timer
Initial value XXXXXXXX -- XXXXXXXX XXXXXXXX 00000000 0000000-
-- UART, CKOT, I/O, serial IF CKOT output Level comparator DTP/external interrupt
-- 0---1111 -----000 XXXX0 0 0 0 ----0000 ----0000 00000000 -- 11111111 -- 00000000 00000000 XXXXXXXX 0 0 0 0 0 0 XX
-- 10-bit A/D converter
-- -- 8-bit D/A converter
-- -- XXXXXXXX 00000000 ------00 -- 00000000 00000000 00000000 -- 00000000 00000000 00000000
-- 8-bit PWM0, 1
-- 8-bit PWM2, 3
(Continued)
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MB90230 Series
Address 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H to 6FH
Register Reserved area PWM data register 4 PWM data register 5 Control status register 4, 5 Reserved area Data register Control status register Reserved area Compare register 0 Compare register 1 Control status register 0, 1 Reserved area Reserved area Compare register 2 Compare register 3 Control status register 2, 3 Reserved area Reserved area Compare register 4 Compare register 5
Register name -- PWD4 PWD5 PWC45 -- TCDT TCCS -- OCP0 OCP1 CS00 CS01 -- -- OCP2 OCP3 CS10 CS11 -- -- OCP4 OCP5 CS20 CS21 -- --
Access -- R/W R/W R/W -- R R/W -- R/W R/W R/W -- -- R/W R/W R/W -- -- R/W
Resouce name -- 8-bit PWM4, 5
Initial value -- 00000000 00000000 00000000 -- 00000000 00000000 00000000 -- XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0000--00 ---00000
-- 16-bit free run timer
-- Output compare 0, 1
-- -- Output compare 2, 3
-- -- XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0000--00 ---00000
-- -- Output compare 4, 5
-- -- XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0000--00 ---00000
R/W R/W -- -- -- --
Control status register 4, 5 Reserved area Reserved area
-- --
(Continued)
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MB90230 Series
Address 70H 71H 72H 73H 74H 75H to 77H 78H 79H 7AH 7BH 7CH 7DH to 7FH 80H 81H 82H 83H 84H 85H 86H to 8FH 90H to 9EH 9FH A0H
Register Capture register 0 Capture register 1 Control status register 0, 1 Reserved area Capture register 2 Capture register 3 Control status register 2, 3 Reserved area OP code register Format status register Data register Address register Reserved area System reserved area Delayed interrupt source generate/ release register Standby control register
Register name ICP0 ICP1 ICS0 -- ICP2 ICP3 ICS1 -- EOPC ECTS EDAT EADR -- -- DIRR STBYC
Access R/W R/W R/W -- R/W R/W R/W -- R/W R/W R/W R/W -- *1 R/W R/W
Resouce name Input capture 0, 1
Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000
-- Input capture 2, 3
-- XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000
-- Serial E2PROM interface
-- ----0000 00000000 XXXXXXXX XXXXXXXX 00000000 00---000
-- -- Delayed interrupt generation module Low-power consumption mode -- -- External pin External pin External pin -- -- Watchdog timer/ reset
-- -- -------0 0 0 0 1 XXXX
A1H A2H A3H A4H A5H A6H A7H A8H
Reserved area Reserved area Middle address control register Upper address control register External pin control register Reserved area Reserved area Watchdog timer control register
-- -- MACR HACR EPCR -- -- TWC
-- -- W W W -- -- R/W
-- -- *2 *2 *2 -- -- XXXXXXXX
(Continued)
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MB90230 Series
Address A9H AAH to AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H to FFH
Register Timebase timer control register Reserved area Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 External area
Register name TBTC -- ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 --
Access R/W -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W --
Resouce name Timebase timer -- Interrupt controller
Initial value ---00000 -- 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111
--
*3
Initial values 0: The initial value for the bit is "0." 1: The initial value for the bit is "1." X: The initial value for the bit is undefined. -: The bit is not used; the initial value is undefined. *1: Access inhibited *2: The initial value depends on each bus mode. *3: Only this area can be used as the external access area in the area that follows address 0000FFH. Access to any address in reserved areas specified in the I/O map table is handled as access to an internal area. An access signal to the external bus is not generated.
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MB90230 Series
s INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS FOR INTERRUPT SOURCES
Interrupt source Reset INT9 instruction Exceptional External interrupt (INT0) 0 ch External interrupt (INT1) 1 ch External interrupt (INT2) 2 ch External interrupt (INT3) 3 ch Extended serial I/O interface Serial E2PROM interface Input capture channel 0 Input capture channel 1 Input capture channel 2 Input capture channel 3 Output compare channel 0 Output compare channel 1 Output compare channel 2 Output compare channel 3 Output compare channel 4 Output compare channel 5 16-bit free run timer overflow Timebase timer overflow 8-bit PPG timer Level comparator UART reception UART transmission End of A/D conversion Delayed interrupt Stack fault x x I2OS support x x x #08 #09 #10 #11 #12 #13 #14 #15 #17 #19 #21 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #37 #39 #42 #256 Interrupt vector No. 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 11H 13H 15H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 25H 27H 2AH FFH Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFB8H FFFFB0H FFFFA8H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF68H FFFF60H FFFF54H FFFC00H ICR12 ICR13 ICR14 ICR15 -- 0000BCH 0000BDH 0000BEH 0000BFH -- ICR11 0000BBH ICR10 0000BAH ICR09 0000B9H ICR08 0000B8H ICR07 0000B7H ICR02 ICR03 ICR04 ICR05 ICR06 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H ICR01 0000B1H Interrupt control register ICR -- -- -- ICR00 Address -- -- -- 0000B0H
: The request flag is cleared by the EI2OS interrupt clear signal. : The request flag is cleared by the EI2OS interrupt clear signal. The stop request is available. : The request flag is not cleared by the EI2OS interrupt clear signal.
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MB90230 Series
s PERIPHERAL RESOURCES
1. I/O Ports
Each pin in each port can be specified for input or output by setting the direction register when the corresponding peripheral resource is not set to use that pin. When the data register is read, the value depending on the pin level is read whenever the pin serves for input. When the data register is read with the pin serving for output, the latch value of the data register is read. This also applies to read operation by the read modify write instruction. * General-purpose I/O port
Data register read Internal data bus Data register Data register write Direction register Direction register write Pin
Direction register read
* Port with pull-up resistor setting register
Pull-up resistor (Approx. 50 k)
Data register Internal data bus
Port input/output
Direction register read
Resistor register
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MB90230 Series
* Port with open-drain setting register
Data register Internal data bus
Port input/output
Direction register
Pin register
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MB90230 Series
(1) Register Configuration
bit Address: 000000H Address: 000001H Address: 000002H Address: 000003H Address: 000004H Address: 000005H Address: 000006H Address: 000007H Address: 000008H Address: 000009H Address: 00000AH bit Address: 000010H Address: 000011H Address: 000012H Address: 000013H Address: 000014H Address: 000015H Address: 000016H Address: 000017H Address: 000018H Address: 000019H Address: 00001AH
15/7 P07 P17 P27 P37 P47 P57 P67 -- P87 -- -- 15/7 P07 P17 P27 P37 P47 P57 P67 -- P87 -- -- 15
14/6 P06 P16 P26 P36 P46 P56 P66 P76 P86 P96 -- 14/6 P06 P16 P26 P36 P46 P56 P66 P76 P86 P96 -- 14
13/5 P05 P15 P25 P35 P45 P55 P65 P75 P85 P95 PA5 13/5 P05 P15 P25 P35 P45 P55 P65 P75 P85 P95 PA5 13
12/4 P04 P14 P24 P34 P44 P54 P64 P74 P84 P94 PA4 12/4 P04 P14 P24 P34 P44 P54 P64 P74 P84 P94 PA4 12
11/3 P03 P13 P23 P33 P43 P53 P63 P73 P83 P93 PA3 11/3 P03 P13 P23 P33 P43 P53 P63 P73 P83 P93 PA3 11
10/2 P02 P12 P22 P32 P42 P52 P62 P72 P82 P92 PA2 10/2 P02 P12 P22 P32 P42 P52 P62 P72 P82 P92 PA2 10
9/1 P01 P11 P21 P31 P41 P51 P61 P71 P81 P91 PA1 9/1 P01 P11 P21 P31 P41 P51 P61 P71 P81 P91 PA1 9
8/0 P00 P10 P20 P30 P40 P50 P60 P70 P80 P90 PA0 8/0 P00 P10 P20 P30 P40 P50 P60 P70 P80 P90 PA0 8 Analog input enable register (ADER) Port 0 direction register (DDR0) Port 1 direction register (DDR1) Port 2 direction register (DDR2) Port 3 direction register (DDR3) Port 4 direction register (DDR4) Port 5 direction register (DDR5) Port 6 direction register (DDR6) Port 7 direction register (DDR7) Port 8 direction register (DDR8) Port 9 direction register (DDR9) Port A direction register (DDRA) Port 0 data register (PDR0) Port 1 data register (PDR1) Port 2 data register (PDR2) Port 3 data register (PDR3) Port 4 data register (PDR4) Port 5 data register (PDR5) Port 6 data register (PDR6) Port 7 data register (PDR7) Port 8 data register (PDR8) Port 9 data register (PDR9) Port A data register (PDRA)
bit Address: 000034H
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 15/7 P07 P17 P27 15/7 -- -- 14/6 P06 P16 P26 14/6 P96 -- 13/5 P05 P15 P25 13/5 P95 PA5 12/4 P04 P14 P24 12/4 P94 PA4 11/3 P03 P13 P23 11/3 -- PA3 10/2 P02 P12 P22 10/2 -- PA2 9/1 P01 P11 P21 9/1 -- PA1 8/0 P00 P10 P20 8/0 -- PA0
bit Address: 00001BH Address: 00001CH Address: 00001DH
Port 0 resistor register (RDR0) Port 1 resistor register (RDR1) Port 2 resistor register (RDR2)
bit Address: 00001EH Address: 00001FH
Port 9 pin register (ODR9) Port A pin register (ODRA)
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MB90230 Series
Ports 0 to 5 in the MB90230 series share the external bus and pins. Each pin function is selected depending on the bus mode and register settings. Function Pin name P07 to P00 P17 to P10 P27 to P20 P37 to P30 P47 to P45 P44 P43 to P40 P50 P51 P52 P53 P54 P55 P56 P57 Port WR RD Port Port CLK*2 RDY*2 HAK*2 HRQ*2 WRH*2 WRL*2 CE OE PGM "0" Not used A23 to A16*1 A23 to A16 Port Single-chip mode External bus extended mode 8 bits D07 to D00 D15 to D08 A07 to A00 A15 to A08*1 16 bits EPROM write D07 to D00 D15 to D08 A07 to A00 A15 to A08
*1: The pin can be used as an I/O port by setting the upper and middle address control registers. *2: The pin can be used as an I/O port by setting the external pin control register.
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MB90230 Series
2. 8-bit PWM (with 6 channels in this series)
The PWM module consists of a pair of 8-bit PWM output circuits. The MB90230 series incorporates a set of three PWM modules. They can output a waveform continuously from the port at an arbitrary duty factor according to the register settings. * * * * 8-bit down counter 8-bit data registers Compare circuit Control registers
(1) Register Configuration
bit 000041, 40H 000045, 44H 000049, 48H 000042H 000046H 00004AH
15
87
0
PWDx
7
PWDx
0
PWM data registers 0 to 5
PWCxx
Control registers 0 to 5
(2) Block Diagram
8-bit down counter
Comparator, PWM output section Bus
PWM output
8-bit data registers
Control registers
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MB90230 Series
3. UART
The UART is a serial I/O port for synchronous or asynchronous communication with external resources. It has the following features: * * * * * * * * * Full-duplex double buffering Data transfer synchronous or asynchronous with clock pulses Multiprocessor mode support (Mode 2) Internal dedicated baud-rate generator Arbitrary baud-rate setting from external clock input or internal timer Variable data length (7 to 9 bits (without parity bit); 6 to 8 bits (with parity bit)) Error detection function (Framing, overrun, parity) Interrupt function (Two sources for transmission and reception) Transfer in NRZ format
(1) Register Configuration
15 USR URD 8 bits
8
7 UMC UIDR (R)/UODR (W) 8 bits
0 (R/W) (R/W)
bit Address: 000020H bit Address: 000021H bit Address: 000022H bit Address: 000023H bit Address: 00002DH
7 PEN 15
6 SBL 14
5 MC1 13 PE 5 D5 13 RC1 13 --
4 MC0 12 TDRE 4 D4 12 RC0 12 --
3 SMDE 11 RIE 3 D3 11 -- 11 DIV3
2 RFC 10 TIE 2 D2 10 -- 10 DIV2
1 SCKE 9 RBF 1 D1 9 P 9 DIV1
0 SOE 8 TBF 0 D0 8 D8 8 DIV0
Mode control register (UMC) Status register (USR) Serial input data register Serial output data register (UIDR/UODR) Rate and data register (URD) Communication prescaler (CDCR)
RDRF ORFE 7 D7 15 -- 15 MD 6 D6 14 RC2 14 --
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MB90230 Series
(2) Block Diagram
CONTROL BUS Reception interrupt (To CPU) Dedicated baud-rate clock Transmitting clock Clock selector circuit Receiving clock SCK0 Transmission interrupt (To CPU)
Internal timer
External clock Reception control circuit Transmission control circuit
SIN0
Start bit detector
Transmission start circuit
Received bit counter
Transmission bit counter
Received parity counter
Transmission parity counter
SOT0
Reception status detection circuit
Reception shifter
Transmission shifter
End of reception UIDR Reception error occurrence signal for EI2OS (To CPU) Data bus
Start of transmission UODR
UMC register
PEN SBL MC1 MC0 SMDE RFC SCKE SOE
USR register
RDRF ORFE PE TDRE RIE TIE RBF TBF
URD register
BCH RC2 RC1 RC0
P D8
CONTROL BUS
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MB90230 Series
4. Extended Serial I/O Interface
This block is a serial I/O interface implemented on a single 8-bit channel that can transfer data in synchronization with clock pulses. It allows the "LSB first" or "MSB first" option to be selected for data transfer. The serial I/O port to be used can also be selected. There are two serial I/O operation modes available: * Internal shift clock mode: Transfers data in synchronization with internal clock pulses. * External shift clock mode: Transfers data in synchronization with clock pulses entered from an external pin (SCKx). In this mode, data can be transferred by instructions from the CPU by operating the general-purpose port that shares the external pin (SCKx). (1) Register Configuration
bit Address: 000025H bit Address: 000024H bit Address: 000026H
15
14
13 SMD0 5 -- 5 D5
12 SIE 4
11 SIR 3
10 BUSY 2 BDS 2 D2
9 STOP 1 SOE 1 D1
8 STRT 0 SCOE 0 D0 Serial mode control status register (SMCS) Serial data register (SDR)
SMD2 SMD1 7 -- 7 D7 6 -- 6 D6
OUTC MODE 4 D4 3 D3
(2) Block Diagram
Internal data bus (MSB first) D0 to D7 SIN1, 2 SDR (Serial data register) SOT1, 2 Read Write D7 to D0 (LSB first) Selecting transfer direction
SCK1, 2 Control circuit Shift clock counter
Internal clock
2
1
0
SIE SIR BUSY STOP STRT MODE BDS SOE SCOE
SMD2 SMD1 SMD0
Interrupt request Internal data bus
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MB90230 Series
5. A/D Converter
The A/D converter converts the analog input voltage to a digital value. It has the following features: Conversion time: 5 s min. per channel (at 16 MHz machine clock) RC-type successive approximation with sample-and-hold circuit 8-bit or 10-bit resolution Eight analog input channels programmable for selection A/D conversion mode selectable from the following three: One-shot conversion mode: Converts a specified channel once. Consecutive conversion mode: Converts a specified channel repeatedly. Stop conversion mode: Converts one channel and suspends its own operation until the next activation (allowing synchronized conversion start). * Conversion mode: Single conversion mode: Converts one channel (when the start and stop channels are the same). Scan conversion mode: Converts multiple consecutive channels (when the start and stop channels are different). * On completion of A/D conversion, the converter can generate an interrupt request for termination of A/D conversion to the CPU. This interrupt generation can activate the EI2OS to transfer the A/D conversion result to memory, making the converter suitable for continuous operation. * Conversion can be activated by software, external trigger (falling edge), and/or timer (rising edge) as selected. * * * * * (1) Register Configuration
bit 000037, 36H 000039, 38H 000034H
15 ADCS1 ADCR1 ADER
8
7 ADCS0 ADCR0 Analog input enable register
0 Control status register Data register
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MB90230 Series
(2) Block Diagram
AVCC
AVRH, AVRL
AVSS
D/A converter MPX AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Input circuit
Successive approximation register
Comparator Data bus Data register Decoder ADCR1, 0 A/D control register 0 A/D control register 1 ADCS1, 0 Operation clock Prescaler
Sample-and-hold circuit
Activation by timer Timer Interlocked with PPG timer
ATG
Activation trigger
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MB90230 Series
6. 16-bit I/O Timer
The 16-bit I/O timer consists of 16-bit free run timer, 6-line output compare, and 4-line input capture modules. The 16-bit I/O timer can output six independent waveforms based on the 16-bit free run timer, allowing the input pulse width and external clock cycle to be measured. (1) Outline of Functions 16-bit free run timer (x 1) The 16-bit free run timer consists of a 16-bit up-count timer, a control register, and a prescaler. The value output from this timer/counter is used as the base time by the input capture and output compare modules. * The counter operation clock cycle can be selected from the following four: Four internal clock cycles (/4, /16, /32, /64) * The interrupt counter value can be generated by compare/match operation with the overflow register and compare register 0 (compare/match operation requires the mode setting). * The counter value can be initialized to "0000H" by compare/match operation with the reset register, software clear register, and compare register 0. Output compare module (x 6) The output compare module consists of six 16-bit compare registers, compare output latches, and control registers. When the compare value matches the 16-bit free run timer value, this module can generates an interrupt while inverting the output level. * Six compare registers can operate independently, and have each output pin and interrupt flag. * Two compare resisters can be used to control the same output pin. * The initial value for each output pin can be set. * The interrupt can be generated by compare/match operation. Input capture module (x 4) The input capture module consists of four external input pins and associated capture and control registers. This module can detect an arbitrary edge of the signal input from each external input pin to generate an interrupt while holding the 16-bit free run timer value in the capture register. * The external input signal edge can be selected from the rising edge, failing edge or both edges. * Four input capture lines can operate independently. * The interrupts can be generated by a valid edge of external input signals. The extended intelligent I/O service (EI2OS) can be activated.
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MB90230 Series
(2) Register Configuration * 16-bit free run timer
bit 00004CH 00004EH 15 TCDT TCCS 0 Timer data register Control status register
* 16-bit output compare module
bit 000050, 52, 58, 5AH 000060, 62H 000054, 55H 00005C, 5DH 000064, 65H 15 OCP0 to 5 0 Compare register 0 to 5
CS x 1
CS x 0
Control status register 0 to 5
* 16-bit input capture module
bit 000070, 72, 78, 7AH 000074, 7CH 15 IPCP0 to 3 ICS0 to 3 0 Compare register 0 to 3 Control status register 0 to 3
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MB90230 Series
(3) Block Diagram
Control logic To each block Clear Output compare 0 Compare register 0 TQ OUT 0
16-bit free run timer 16-bit timer
Bus
Compare register 1 Output compare 1 Compare register 2
TQ
OUT 1
TQ
OUT 2
Compare register 3 Output compare 2 Compare register 4
TQ
OUT 3
TQ
OUT 4
Compare register 5
TQ
OUT 5
Input capture 0 Capture register 0 Edge selection IN 0
Capture register 1 Input capture 1 Capture register 2
Edge selection
IN 1
Edge selection
IN 2
Capture register 3
Edge selection
IN 3
Interrupt 10
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MB90230 Series
7. PPG Timer (Programmable Pulse Generator)
This module can output the pulse synchronized with an external or software trigger. The cycle and duty factor of the output pulse can be changed arbitrarily by changing the values in two 8-bit registers. PWM function: Outputs a pulse in programmable mode while changing the values in the two registers in synchronization with the input trigger. This module can also be used as a D/A converter using an external circuit. Single-shot function: Detects the trigger input edge to output a single pulse. (1) Module Configuration This module consists of an 8-bit down counter, prescaler, 8-bit cycle setting register, 8-bit duty factor setting register, 16-bit control register, external trigger input pin, and PPG output pin. (2) Register Configuration
bit Address: 000028H 000029H 00002BH, 2AH PDUT PCNTH PCNTL
15
8
7 PCSR
0 Cycle setting register Duty factor setting register Control status register
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MB90230 Series
(3) Block Diagram
PCSR
PDUT
Prescaler
1/ 4/ 16 / 64 / ck 8-bit down counter Start Borrow Load
cmp
PPG mask
S @Q
PPG output
R
Inverted bit
Interrupt selection
Enable
IRQ
TRG input
Edge detection
Software trigger
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MB90230 Series
8. Serial E2PROM Interface
This module is the interface circuit dedicated to external bit-serial E2PROM. (1) Features * * * * * * Instruction code support (compatible with the MB8557). Selectable address length: 8 to 11 bits Selectable data length: 8 or 16 bits Automatic address increment function Transmit/receive data transfer enabled by EI2OS Up to 2048-by-16 bit access enabled (at an address length of 11 bits and a data length of 16 bits)
(2) Register Configuration
15 8 7 0 Status format register Data register Address register
bit
bit Address: 000081H bit Address: 000080H bit Address: 000083H bit Address: 000082H bit Address: 000085H bit Address: 000084H
15 IFEN 7 -- 15 D15 7 D7 15 CLK 7 A7
14 INT 6 -- 14 D14 6 D6 14 FRQ 6 A6
13 INTE 5 -- 13 D13 5 D5 13 -- 5 A5
12 BUSY 4 -- 12 D12 4 D4 12 -- 4 A4
11 ADL1 3 OP3 11 D11 3 D3 11 -- 3 A3
10 ADL0 2 OP2 10 D10 2 D2 10 A10 2 A2
9 DTL 1 OP1 9 D9 1 D1 9 A9 1 A1
8 CON 0 OP0 8 D8 0 D0 8 A8 0 A0
Format status register (ECTS) Op code register (EOPC) Data register (EDAT) Data register (EDAT) Address register (EADR) Address register (EADR)
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MB90230 Series
(3) Block Diagram
Op code register
Address register
Bus
EDI Data register Data register EDO Format register ECS Status register
Operation clock Machine cycle Prescaler ESK
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MB90230 Series
9. DTP/External Interrupt
The data transfer peripheral (DTP) is located between external peripherals and the F2MC-16F CPU. It receives a DMA request or interrupt request generated by the external peripherals and reports it to the F2MC-16F CPU to activate the extended intelligent I/O service or interrupt handler. The user can select two request levels of "H" and "L" for extended intelligent I/O service (EI2OS) or, four request levels of "H," "L," rising edge, and falling edge for external interrupt requests. (1) Register Configuration
bit Address: 000031H, 30H 000032H
15 EIRR
8
7 ENIR ELVR
0 Interrupt/DTP enable register Request level setting register
(2) Block Diagram
4
Interrupt DTP source register
F2MC-16 bus
4
Gate
Source F/F
Edge detection circuit
3
Request input
4
Interrupt DTP source register
8
Request level setting register
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10. D/A Converter
This block is an R-2R type D/A converter with 8-bit resolution. The D/A converter incorporates two channels, each of which can be controlled for output independently by the D/A control register. (1) Register Configuration
bit DAT1 Address: 00003DH DAT0 Address: 00003CH DACR Address: 00003EH
15 DA17 7 DA07 7 --
14 DA16 6 DA06 6 --
13 DA15 5 DA05 5 --
12 DA14 4 DA04 4 --
11 DA13 3 DA03 3 --
10 DA12 2 DA02 2 --
9 DA11 1 DA01 1 DAE1
8 DA10 0 DA00 0 DAE0 D/A control register D/A converter data register 2 D/A converter data register 1
(2) Block Diagram
F2MC-16 bus
DA DA DA DA DA DA DA DA 17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA 07 06 05 04 03 02 01 00
AVCC DA17 2R DA16 2R DA15 R DA07
AVCC
2R DA06 2R DA05
R
R
R
DA11 2R DA10 R
DA01 2R DA00 R
2R 2R DAE1 Standby control
2R 2R DAE0 Standby control
DA output ch. 1
DA output ch. 0
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11. Level Comparator
This module compares the input level (by checking whether it is high or low). The module consists of a comparator, 4-bit resistor ladder, and control register. * The external input can be compared to the internal 4-bit resistor ladder. (1) Register Configuration
bit Address: 00002FH
8 LVLC
0 Level comparator
(2) Block Diagram
4-bit D/A AVRH RD3 RD2 RD1 RD0 Bus 4 CPLV INT INTE CPEN Interrupt Comparator
AVRL Analog input CMP S/H
Resistor ladder
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12.Watchdog Timer and Timebase Timer
The watchdog timer consists of a 2-bit watchdog counter using carry signals from an 18-bit timebase counter as the clock source, a control register, and a watchdog reset control section. The timebase timer consists of an 18-bit timer and an interval interrupt control circuit. (1) Register Configuration
bit Address: 0000A9H, A8H
15 TBTC
8
7 WTC
0 Timebase timer control register
(2) Block Diagram
Oscillation clock TBTC TBC1 F2MC-16 bus TBC0 TBR TBIE AND TBOF Timebase interrupt WTC WT1 Selector WT0 WTE PONR STBR WRST ERST SRST RST pin From RST bit in STBYC register 2-bit counter OF CLR Watchdog reset generator CLR WDGRST To internal reset generator Q S R Clock input 2 12 2 14 2 16 Timebase timer 2 18 TBTRES 2 14 2 16 2 17 2 18
Selector
From power-on occurrence From hardware standby control circuit
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13. Delay Interruupt Generation Module
The delayed interrupt generation module is used to generate an interrupt for task switching. Using this module allows an interrupt request to the F2MC-16F CPU to be generated or canceled by software. (1) Register Configuration
15 -- (--) (X) 14 -- (--) (X) 13 -- (--) (X) 12 -- (--) (X) 11 -- (--) (X) 10 -- (--) (X) 9 -- (--) (X) 8 R0 (R/W) (0) DIRR
bit Delayed interrupt source generate/release register Address: 00009FH Read/write Initial value
(2) Block Diagram
F2MC-16 bus
Delayed interrupt source generate/release decoder
Interrupt source latch
14. Clock Output Control Register
The clock output control register outputs the output from the communication prescaler to the pin. (1) Register Configuration
bit Clock control register Address: 00002EH Read/write Initial value
15 -- (--) (--)
14 -- (--) (--)
13 -- (--) (--)
12 -- (--) (--)
11 -- (--) (--)
10 CKEN (R/W) (0)
9 FRQ1 (R/W) (0)
8 FRQ0 (R/W) (0) CLKR
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15.Low-power Consumption Control Circuit The low-power consumption control circuit consists of a low-power consumption control register, clock generator, standby status control circuit, and gear divider circuit. These internal circuits implements the sleep, stop, and hardware standby modes as well as the clock gear function. The gear function allows the machine clock cycle to be selected as a division of the frequency of crystal oscillation or external clock input by 1, 2, 4, or 16. (1) Register Configuration
bit Address: 0000A0H
15
8
7 STBYC
0 Standby control register
(2) Block Diagram
Oscillation clock Gear divider circuit 1/1 1/2 STBYC CLK1 Selector F2MC-16 bus CLK0 Resource clock generator Standby control circuit STP RST Clear HST start HST pin Interrupt request or RST Clock input Time-base timer 2 14 2 16 2 17 2 18 Resource clock 1/4 1/16 CPU clock generator
CPU clock
SLP
OSC1 Selector OSC0
20 2 16 2 17 2 18
SPL
Pin high-impedance control circuit
Pin HI-Z
RST pin Internal reset generator RST Internal RST To watchdog timer WDGRST
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MB90230 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = 0.0 V) Parameter Symbol VCC Power supply voltage Input voltage Output voltage "L" level output current "L" level average output current "L" level total output current "H" level output current "H" level total output current Power consumption Operating temperature Storage temperature AVCC, AVSS AVRH, AVRL VI*2 VO*2 IOL IOLAV IOL IOH IOH PD TA TSTG Value Min. VSS - 0.3 VCC - 0.3*1 VSS - 0.3 VSS - 0.3 -- -- -- -- -40 -55 Max. VSS + 7.0 VSS + 7.0 VCC + 0.3 VCC + 0.3 20 4 50 -10 -4 -50 400 +70 +150 Unit V V V V mA mA mA mA mA mA mW C C Remarks
"H" level average output current IOHAV
*1: AVRH, AVRL, or AVCC must not exceed VCC. AVSS and AVRH must not exceed AVRH and AVCC, respectively. VCC AVCC AVRH > AVRL AVSS VSS *2: VI or VO must not exceed "VCC + 0.3 V." WARNING: Permanent device damage may occur if the above "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for externded periods may affect device reliability.
2. Recommended Operating Conditions
(VSS = 0.0 V) Parameter Power supply voltage Operating temperature Symbol VCC TA Value Min. 4.75 3.0 -40 Max. 5.25 5.5 +70 Unit V V C Remarks During normal operation In stop mode
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3. DC Characteristics
(VCC = 5.0 V5%, VSS = 0.0 V, TA = -40C to +70C) Value Unit Remarks Min. Typ. Max. 0.7 VCC VCC = 5.0 V5% 0.8 VCC VCC - 0.3 VSS - 0.3 VCC = 5.0 V5% VCC = 4.75 V IOH = -2.0 mA VCC = 4.75 V IOL = 1.8 mA VSS + 4.75 V Parameter
Symbol VIH
Pin name *1 *2 *3 *1 *2 *3 *1, *2 *1, *2 *1, *2, *3
Condition
"H" level input voltage
VIHS VIHM VIL
"L" level input voltage "H" level output voltage "L" level output voltage Input leakage current Power supply current
VILS VILM VOH VOL IIH ICC ICCS ICCH
Input capacity Open-drain output leakage current (N-channel Tr OFF) Pull-up current
CIN
ILEAK
*4
--
--
0.1
10
A
IPULL
*5
--
-250
--
-50
A
*1: CMOS I/O pin (Other than hysteresis pins) *2: Hysteresis input pins: P46/TRG, P70/ATG, P71/ESI, P80/INT0, P81/INT1, P82/OUT0/INT2, P83/OUT1/INT3, P90/IN0, P91/IN1, P92/IN2, P93/IN3/CKOT, P94/SIN0, P96/SCK0, PA0/SIN1, PA2/SCK1, PA3/SIN2, PA5/SCK2 *3: Mode pins MD2 to MD0 *4: Open-drain pins P94 to P96 and PA0 to PA5: Set by registers *5: Pins with pull-up resistor RST and P00 to P27: Set by registers
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4. AC Characteristics
(1) Clock Timing Standards (VCC = +5.0 V5%, VSS = 0.0 V, TA = -40C to +70C) Value Condition Unit Remarks Min. Max. VCC = 5.0 V 5% VCC = 5.0 V 5% VCC = 5.0 V 5% -- 1 62.5 25.0 5 16 -- -- 10 MHz ns ns ns Duty = 60%
Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time
Symbol fC tC PWH PWL tcr tcf
Pin name X0 X1 X0 X1 X0 X0
tc
0.8 VCC 0.2 VCC
PWH tcf
PWL tcr
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(2) Reset, Hardware Standby, and Trigger Input Standards (VCC = +5.0 V5%, VSS = 0.0 V, TA = -40C to +70C) Value Condition Unit Remarks Min. Max. -- -- -- -- -- 5 5 5 5 5 -- -- -- -- -- Machine cycle* Machine cycle* Machine cycle* Machine cycle* Machine cycle*
Parameter Reset input time A/D start trigger input time PPG start trigger input time Input capture input trigger
Pin Symbol name tRSTL tATGX tPPGL tINP RST HST ATG TRG IN0 to IN3
Hardware standby input time tHSTL
*Machine cycle: tCYC = 1/machine clock = 1/(fC / N) fC: Oscillation frequency N: Gear divide ratio (1, 2, 4, 16) Note: Clock input is required during reset. The machine cycle at hardware standby input is set to 1/32 divided oscillation.
RST HST ATG TRG IN0 to IN3
tRSTL, tHSTL, tINP tATGX, tPPGT
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(3) Power-on Reset (VCC = +5.0 V 5%, VSS = 0.0 V, TA = -40C to +70C) Value Pin name Condition Unit Remarks Min. Max. Vcc -- -- 1 50 -- ms ms
Parameter Power supply riseing time Power-off time
Symbol tR tOFF
tR Vcc 4.5 V 0.2 V tOFF
Keep in mind that abrupt changes in supply voltage may cause a power-on reset.
Vcc
5V
3V RAM data refined Vss
It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower.
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(4) UART Timing (VCC = +5.0 V5%, VSS = 0.0 V, TA = -40C to +70C) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name -- -- -- -- -- -- -- -- -- External clock operation output pin: CL = 80 pF Internal clock operation output pin: CL = 80 pF Condition Value Min. 8 tCYC -80 100 60 4 tCYC 4 tCYC -- 60 60 Max. -- 80 -- -- -- -- 150 -- -- Unit ns ns ns ns ns ns ns ns ns Remarks
Notes: * These AC characteristics assume the CLK synchronous mode. * CL is the value for load capacity applied to the pin under testing. * tCYC is the machine cycle (in nanoseconds). * Internal shift clock mode
tSCYC SCK 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH 2.4 V 0.8 V tSHIX 2.4 V 0.8 V 2.4 V 0.8 V
SIN
* External shift clock mode
tSLSH SCK 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH 2.4 V SIN 0.8 V tSHIX 2.4 V 0.8 V 0.8 V 2.4 V tSHSL 2.4 V
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(5) Extended Serial I/O Timing (VCC = +5.0 V5%, VSS = 0.0 V, TA = -40C to +70C) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name -- -- -- -- -- -- -- -- -- External clock operation output pin: CL = 80 pF Internal clock operation output pin: CL = 80 pF Condition Value Min. 8 tCYC 50 1 tCYC 1 tCYC 250 250 2 tCYC 1 tCYC 2 tCYC Max. -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns External clock: 2 MHz max. Remarks
Notes: * CL is the value for load capacity applied to the pin under testing. * tCYC is the machine cycle (in nanoseconds). * Internal shift clock mode
tSCYC SCK 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH 2.4 V 0.8 V tSHIX 2.4 V 0.8 V 2.4 V 0.8 V
SIN
* External shift clock mode
tSLSH SCK 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH 2.4 V SIN 0.8 V tSHIX 2.4 V 0.8 V 0.8 V 2.4 V tSHSL 2.4 V
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5. A/D Converter Electrical Characteristics
(AVCC = VCC = +5.0 V5%, AVSS = VSS = 0.0 V, +3.0 V AVRH - AVRL, TA = -40C to +70C Value Symbol Pin name Unit Parameter Min. Typ. Max. Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Conversion time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Variation between channels -- IA IAS IR IRS -- VOT VFST -- IAIN AN0 to AN7 fC = 16 MHz AN0 to AN7 AVRH AVRL AVCC AVRH AN0 to AN7 -- -- -- -- -- -- -1.5 AVRH -4.5 5.00 -- AVRL AVRL 0 -- -- -- -- -- 10 -- -- -- +0.5 AVRH -1.5 -- -- -- -- -- 5 -- 200 -- -- 10 3.0 2.0 1.5 +2.5 AVRH +0.5 -- 10 AVRH AVCC AVRH -- 5* -- 5* 4 bit LSB LSB LSB LSB LSB s A V V V mA A A A LSB
* : Current applied in CPU stop mode with the A/D converter inactive (VCC = AVCC = AVRH = 5.5 V). Notes: * The error becomes larger as |AVRH-AVRL| becomes smaller. * Use the output impedance of the external circuit for analog input under the following conditions: External circuit output impedance < Approx. 7 k * If the output impedance the external circuit is too high, the analog voltage sampling time may be insufficient. (Sampling time = 3.0 s at a machine clock frequency of 16 MHz) * Analog Input Circuit Mode
Analog input RON1 RON2 + RON2 = Approx. 3 k C0 = Approx. 60 pF C1 = Approx. 4 pF Note: The values shown here are reference values. RON2 C1
C0 Comparator
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6. A/D Glossary
* Resolution Analog changes that are identifiable with the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024 * Total error Difference between actual and logical values. This error is caused by a zero transition error, full-scale transition error, linearity error, differential linearity error, or by noise. * Linearity error The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1111" "11 1111 1110") from actual conversion characteristics * Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
Digital output 11 1111 1111 11 1111 1110 * * * * * * * * * * * 00 0000 0010 00 0000 0001 00 0000 0000 VOT
(1LSB x N + VOT)
Linearity error Analog input VNT V(N
{1)T
VFST
1LSB
=
VFST - VOT 1022 VNT - (1LSB x N + VOT ) 1LSB V( N+1)T -VNT 1LSB
Linearity error
=
(LSB)
Differential linearity error =
-1
(LSB)
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7. D/A Converter Electrical Characteristics
(AVCC = VCC = +5.0 V5%, AVSS = VSS = 0.0 V, TA = -40C to +70C) Parameter Resolution Differential linearity error Conversion time Analog output impedance Symbol -- -- -- -- Pin name -- -- -- -- Value Min. -- -- -- -- Typ. 8 -- 10* 28 Max. 8 0.9 20* -- Unit bit LSB s K
*: A load capacity of 20 pF is assumed.
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8. Serial E2PROM Interface Timing
(1) E2PROM interface at an operation clock frequency of 1 MHz (VCC = +5.0 V5%, VSS = 0.0 V, TA = -40C to +70C) Value Unit Remarks Typ. Max. -- 0.5 0.5 -- -- -- -- -- -- -- 1.0 -- -- -- -- -- -- -- -- -- -- -- s s s s s s s s s s s
Parameter Operation cycle Clock "H" time Clock "L" time ECS setup time ECS hold time EDO data decision time EDO output hold time EDI setup time EDI hold time READY ECS ECS "L" time
Symbol tSK tSKH tSKL tCSS tCSH tPD tOH tDIS tDIH tRCSH tCSL
Min. 1.0 0.4 0.4 0.3 0.0 0.3 0.5 0.0 0.4 0.4 0.8
(2) E2PROM interface at an operation clock frequency of 2 MHz (VCC = +5.0 V5%, VSS = 0.0 V, TA = -40C to +70C) Parameter Operation cycle Clock "H" time Clock "L" time ECS setup time ECS hold time EDO data decision time EDO output hold time EDI setup time EDI hold time READY ECS ECS "L" time Symbol tSK tSKH tSKL tCSS tCSH tPD tOH tDIS tDIH tRCSH tCSL Value Min. 0.5 0.2 0.2 0.15 0.0 0.15 0.25 0.0 0.2 0.2 0.4 Typ. -- 0.25 0.25 -- -- -- -- -- -- -- 0.5 Max. -- -- -- -- -- -- -- -- -- -- -- Unit s s s s s s s s s s s Remarks
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tSK tSKH ESK tPD EDO tOH Determined data Determined data tCSH tSKL
tCSS ECS tDIS EDI Input data tDIH Input data
tCSL ECS
tST DO (E2PROM output) Hi-z BUSY READY
MB90230 series ECS ESK EDO EDI
E2PROM ECS ESK EDI EDO
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s INSTRUCTIONS (412 INSTRUCTIONS)
Table 1 Item Mnemonic Description of Instruction Table Description Upper-case letters and symbols: Described directry in assembly code Lower-case letters: Replaced when described in assembly code Numbers after lower-case letters: Indicates the bit width within the code Indicates the number of bytes Indicates the number of cycles See Table 4 for details about meanings of letters in items. Indicates the compensation value for calculating the number of actual cycles during execution of instruction. The number of actual cycles during execution of instruction is summed with the value in the "cycles" column. Indicates operation of instruction. Indicates special operations involving the bits 15 through 08 of the accumulator. Z: Transfers "0" X: Extends before transferring --: No transfer Indicates special operations involving the high-order 16 bits in the accumulator. *: Transfers from AL to AH --: No transfer Z: Transfers 00H to AH. X: Transfers 00H or FFH to AH by extending AL Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). *: Changes due to execution of instruction. --: No change. S: Set by execution of instruction. R: Reset by execution of instruction.
# ~ B
Operation LH
AH
I S T N Z V C RMW
Indicates whether the instruction is a read-modify-write instruction (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.). *: Instruction is a read-modify-write instruction --: Instruction is not a read-modify-write instruction Note: Cannot be used for addresses that have different meanings depending on whether they are read or written.
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Table 2 Symbol A Explanation of Symbols in Table of Instructions Description 32-bit accumulator The number of bits used varies according to the instruction. Byte: Low order 8 bits of AL Word: 16 bits of AL Long: 32 bits of AL, AH High-order 16 bits of A Low-order 16 bits of A Stack pointer (USP or SSP) Program counter Stack pointer upper limit register Stack pointer lower limit register Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Compact direct addressing Direct addressing Physical direct addressing Bits 0 to 15 of addr24 Bits 16 to 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset value Vector number (0 to 15) Vector number (0 to 255) Bit address Branch specification relative to PC Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list
AH AL SP PC SPCU SPCL PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 addr24 0 to 15 addr24 16 to 23 io #imm4 #imm8 #imm16 #imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b rel ear eam rlst 62
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Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Notation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Fields Address format Register direct "ea" corresponds to byte, word, and long-word types, starting from the left Number of bytes in address extemsion* --
@RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + dip16 addr16
Register indirect
0
Register indirect with post-increment
0
Register indirect with 8-bit displacement
1
Register indirect with 16-bit displacemen
2
Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address
0 0 2 2
* : The number of bytes for address extension is indicated by the "+" symbol in the "#" (number of bytes) column in the Table of Instructions.
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Table 4 Code 00 to 07 Number of Execution Cycles for Each Form of Addressing Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + dip16 @addr16 (a)* Number of execution cycles for each from of addressing Listed in Table of Instructions
08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F
1 4 1 1 2 2 2 1
* : "(a)" is used in the "cycles" (number of cycles) column and column B (correction value) in the Table of Instructions. Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles Operand Internal register Internal RAM even address Internal RAM odd address Even address not in internal RAM Odd address not in internal RAM External data bus (8 bits) + + + + + + (b)* byte 0 0 0 1 1 1 + + + + + + (c)* word 0 0 1 1 3 3 + + + + + + (d)* long 0 0 2 2 6 6
* : "(b)", "(c)", and "(d)" are used in the "cycles" (number of cycles) column and column B (correction value) in the Table of Instructions.
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Table 6 Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVP MOVP MOVN A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, @SP+disp8 A, addr24 A, @A A, #imm4 # ~ Transfer Instructions (Byte) [50 Instructions] B (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) (b) (b) (b) 0 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 (b) 0 (b) (b) 0 (b) (b) Operation byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RLi))+disp8) byte (A) ((SP)+disp8) byte (A) (addr24) byte (A) ((A)) byte (A) imm4 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RWi))+disp8) byte (A) ((RLi))+disp8) byte (A) ((SP)+disp8) byte (A) (addr24) byte (A) ((A)) byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi)) +disp8) (A) byte ((SP)+disp8) (A) byte (addr24) (A) byte (Ri) (ear) byte (Ri) (eam) byte ((A)) (Ri) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 byte ((A)) (AH) byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam)
LH AH I S T N Z V C RMW
2 2 2 3 1 1 1 2 2+ 2+ (a) 2 2 2 2 2 2 6 3 3 3 3 5 2 2 1 1
Z Z Z Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X X X X - - - - - - - - - - - - - - - - - - - - Z Z - -
* * * * * * * - * * * - * * * * * * * * - * * * * - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * R * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 2 MOVX A, dir 2 3 MOVX A, addr16 1 2 MOVX A, Ri 1 2 MOVX A, ear 2+ 2+ (a) MOVX A, eam 2 2 MOVX A, io 2 2 MOVX A, #imm8 2 2 MOVX A, @A 3 MOVX A,@RWi+disp8 2 6 MOVX A, @RLi+disp8 3 3 3 MOVX A, @SP+disp8 3 5 MOVPX A, addr24 2 2 MOVPX A, @A MOV MOV MOV MOV MOV MOV MOV MOV MOVP MOV MOV MOVP MOV MOV MOV MOV MOV MOV MOV MOV XCH XCH XCH XCH dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A @SP+disp8, A addr24, A Ri, ear Ri, eam @A, Ri ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH A, ear A, eam Ri, ear Ri, eam 2 2 2 3 1 1 2 2 2+ 2+ (a) 2 2 6 3 3 3 3 5 2 2 2+ 3+ (a) 3 2 3 2 2+ 3+ (a) 2 2 3 3 3 3 2 3 3+ 2+ (a) 2 2
0 3 2 2+ 3+ (a) 2x (b) 0 4 2 2+ 5+ (a) 2x (b)
For an explanation of "(a)" and "(b)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 7 Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 A, @SP+disp8 # ~ Transfer Instructions (Word) [40 Instructions] B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) (c) (c) (c) 0 0 0 0 (c) (c) (c) (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) Operation word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16 word (A) ((RWi) +disp8) word (A) ((RLi) +disp8) word (A) ((SP) +disp8 word (A) (addr24) word (A) ((A)) word (dir) (A) word (addr16) (A) word (SP) imm16 word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) word ((RWi) +disp8) (A) word ((RLi) +disp8) (A) word ((SP) +disp8) (A) word (addr24) (A) word ((A)) (RWi) word (RWi) (ear) word (RWi) (eam) word (ear) (RWi) word (eam) (RWi) word (RWi) imm16 word (io) imm16 word (ear) imm16 word (eam) imm16 word ((A)) (AH) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam)
LH AH I S T N Z V C RMW
MOVPWA, addr24 MOVPWA, @A
2 2 3 2 1 2 1 1 2 1 2+ 2+ (a) 2 2 2 2 3 2 2 3 3 6 3 3 5 3 2 2 2 3 4 1 1 2 2+ 2 2 3 3 5 2 2 2+ 2 2+ 3 4 4 4+ 2 2 2 2 2 1 2 2+ (a) 2 3 6 3 3 3 2 3+ (a) 3 3+ (a) 2 3 2 2+ (a) 2
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * - * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW
dir, A addr16, A SP # imm16 , SP A , RWi, A ear, A eam, A io, A @RWi+disp8, A @RLi+disp8, A @SP+disp8, A RWi, ear RWi, eam ear, RWi eam, RWi RWi, #imm16 io, #imm16 ear, #imm16 eam, #imm16
MOVPWaddr24, A MOVPW@A, RWi
MOVW @AL, AH XCHW XCHW XCHW XCHW A, ear A, eam RWi, ear RWi, eam
2 3 0 2+ 3+ (a) 2x (c) 2 4 0 2+ 5+ (a) 2x (c)
Note: For an explanation of "(a)" and "(c)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 8 Mnemonic # Transfer Instructions (Long Word) [11 Instructions] ~ B 0 (d) 0 (d) (d) (d) (d) (d) (d) 0 (d) Operation long (A) (ear) long (A) (eam) long (A) imm32 long (A) ((SP) +disp8) long (A) (addr24) long (A) ((A)) long ((A)) (RLi) long ((SP) + disp8) (A) long (addr24) (A) long (ear) (A) long (eam) (A)
LH AH I S T N Z V C RMW
MOVL A, ear 2 1 MOVL A, eam 2+ 3+ (a) MOVL A, # imm32 5 3 MOVL A, @SP + disp8 3 4 MOVPL A, addr24 5 4 MOVPL A, @A 2 3 MOVPL@A, RLi 2 5
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * * * * * * *
* * * * * * * * * * *
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
MOVL @SP + disp8, A 3 4 MOVPL addr24, A 5 4 MOVL ear, A 2 2 MOVL eam, A 2+ 3+ (a)
For an explanation of "(a)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 9 Mnemonic ADD A, #imm8 ADD A, dir ADD A, ear ADD A, eam ADD ear, A ADD eam, A ADDC A ADDC A, ear ADDC A, eam ADDDC A SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] # ~ B Operation byte (A) (A) + imm8 byte (A) (A) + (dir) byte (A) (A) + (ear) byte (A) (A) + (eam) byte (ear) (ear) + (A) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C) byte (A) (AH) + (AL) + (C) (Decimal) byte (A) (A) - imm8 byte (A) (A) - (dir) byte (A) (A) - (ear) byte (A) (A) - (eam) byte (ear) (ear) - (A) byte (eam) (eam) - (A) byte (A) (AH) - (AL) - (C) byte (A) (A) - (ear) - (C) byte (A) (A) - (eam) - (C) byte (A) (AH) - (AL) - (C) (Decimal) word (A) (AH) + (AL) word (A) (A) + (ear) word (A) (A) + (eam) word (A) (A) + imm16 word (ear) (ear) + (A) word (eam) (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) - imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) + imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) - imm32
LH AH I S T N Z V C RMW
2 2 0 2 3 (b) 2 2 0 2+ 3+ (a) (b) 2 2 0 2+ 3+ (a) 2x (b) 1 2 0 2 2 0 2+ 3+ (a) (b) 1 3 0 2 2 0 2 3 (b) 2 2 0 2+ 3+ (a) (b) 2 2 0 2+ 3+ (a) 2x (b) 1 2 0 2 2 0 2+ 3+ (a) (b) 1 3 0
Z Z Z Z - Z Z Z Z Z Z Z Z Z - - Z Z Z Z - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
- - - - * * - - - - - - - - * * - - - - - - - - * * - - - - - - * * - - - - - - - -
ADDW A 1 2 0 ADDW A, ear 2 2 0 ADDW A, eam 2+ 3+ (a) (c) ADDW A, #imm16 3 2 0 ADDW ear, A 2 2 0 ADDW eam, A 2+ 3+ (a) 2x (c) ADDCW A, ear 2 2 0 ADDCW A, eam 2+ 3+ (a) (c) SUBW A 1 2 0 SUBW A, ear 2 2 0 SUBW A, eam 2+ 3+ (a) (c) SUBW A, #imm16 3 2 0 SUBW ear, A 2 2 0 SUBW eam, A 2+ 3+ (a) 2x (c) SUBCW A, ear 2 2 0 SUBCW A, eam 2+ 3+ (a) (c) ADDL ADDL ADDL SUBL SUBL SUBL A, ear 2 5 A, eam 2+ 6+ (a) A, #imm32 5 4 A, ear 2 5 A, eam 2+ 6+ (a) A, #imm32 5 4 0 (d) 0 0 (d) 0
For an explanation of "(a)", "(b)", "(c)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # ~ B Operation
LH AH I S T N Z V C RMW
2 2 0 byte (ear) (ear) +1 2+ 3+ (a) 2x (b) byte (eam) (eam) +1 2 2 0 byte (ear) (ear) -1 2+ 3+ (a) 2x (b) byte (eam) (eam) -1 2 2 0 word (ear) (ear) +1 2+ 3+ (a) 2x (c) word (eam) (eam) +1 2 2 0 word (ear) (ear) -1 2+ 3+ (a) 2x (c) word (eam) (eam) -1 2 4 0 long (ear) (ear) +1 2+ 5+ (a) 2x (d) long (eam) (eam) +1 2 4 0 long (ear) (ear) -1 2+ 5+ (a) 2x (d) long (eam) (eam) -1
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
* * * * * * * * * * * *
* * * * * * * * * * * *
* * * * * * * * * * * *
- - - - - - - - - - - -
* * * * * * * * * * * *
DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam
For an explanation of "(a)", "(b)", "(c)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW A A, ear A, eam A, #imm8 A A, ear A, eam A, #imm16 #
Compare Instructions (Byte/Word/Long Word) [11 Instructions] ~ B 0 0 (b) 0 0 0 (c) 0 0 (d) 0 Operation byte (AH) - (AL) byte (A) - (ear) byte (A) - (eam) byte (A) - imm8 word (AH) - (AL) word (A) - (ear) word (A) - (eam) word (A) - imm16 long (A) - (ear) long (A) - (eam) long (A) - imm32
LH AH I S T N Z V C RMW
1 2 2 2 2+ 2+ (a) 2 2 1 2 2 2 2+ 2+ (a) 3 2 2 3 2+ 4+ (a) 5 3
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
- - - - - - - - - - -
CMPL A, ear CMPL A, eam CMPL A, #imm32
For an explanation of "(a)", "(b)", "(c)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 12 Mnemonic
DIVU DIVU DIVU A A, ear
Unsigned Multiplication and Division Instructions (Word/Long Word) [11 Instructions] # 1 2 ~ *
1
B
Operation
LH AH
I
S
T
N
Z
V
C RMW
*2 *3 *4 *5
A, eam 2+
DIVUW A, ear DIVUW
2
A, eam 2+
0 word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam)
Quotient word (A) Remainder word (eam)
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * - - - - - -
* * * * * - - - - - -
- - - - - - - - - - -
MULU MULU MULU MULUW MULUW MULUW
A A, ear A, eam A A, ear A, eam
1 2 2+ 1 2 2+
*8 *9 *10 *11 *12 *13
0 0 (b) 0 0 (c)
byte (AH) x byte (AL) word (A) byte (A) x byte (ear) word (A) byte (A) x byte (eam) word (A) word (AH) x word (AL) long (A) word (A) x word (ear) long (A) word (A) x word (eam) long (A)
For an explanation of "(b)" and "(c), refer to Table 5, "Correction Values for Number of Cycle Used to Calculate Number of Actual Cycles." *1: 3 when dividing into zero, 6 when an overflow occurs, and 14 normally. *2: 3 when dividing into zero, 5 when an overflow occurs, and 13 normally. *3: 5 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 17 + (a) normally. *4: 3 when dividing into zero, 5 when an overflow occurs, and 21 normally. *5: 4 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 25 + (a) normally. *6: (b) when dividing into zero or when an overflow occurs, and 2 x (b) normally. *7: (c) when dividing into zero or when an overflow occurs, and 2 x (c) normally. *8: 3 when byte (AH) is zero, and 7 when byte (AH) is not 0. *9: 3 when byte (ear) is zero, and 7 when byte (ear) is not 0. *10: 4 + (a) when byte (eam) is zero, and 8 + (a) when byte (eam) is not 0. *11: 3 when word (AH) is zero, and 11 when word (AH) is not 0. *12: 3 when word (ear) is zero, and 11 when word (ear) is not 0. *13: 4 + (a) when word (eam) is zero, and 12 + (a) when word (eam) is not 0.
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Table 13 Mnemonic DIV DIV
DIV
Signed Multiplication and Division Instructions (Word/Long Word) [11 Insturctions] # 2 2 ~ *
1
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
A A, ear
*2 *3 *4 *5 *8 *9 *10 *11 *12 *13
A, eam 2+
DIVW A, ear
DIVW
2
A, eam 2+
0 word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) 0 0 (b) 0 0 (b) byte (AH) x byte (AL) word (A) byte (A) x byte (ear) word (A) byte (A) x byte (eam) word (A) word (AH) x word (AL) long (A) word (A) x word (ear) long (A) word (A) x word (eam) long (A)
Z Z Z - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * - - - - - -
* * * * * - - - - - -
- - - - - - - - - - -
MUL MUL
2 2 MUL A, eam 2+ MULW A 2 MULW A, ear 2 MULW A, eam 2+
A A, ear
For an explanation of "(b)" and "(c)", refer to Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." *1: *2: *3: *4: *5: 3 when dividing into zero, 8 or 18 when an overflow occurs, and 18 normally. 3 when dividing into zero, 10 or 21 when an overflow occurs, and 22 normally. 4 + (a) when dividing into zero, 11 + (a) or 22 + (a) when an overflow occurs, and 23 + (a) normally. When the dividend is positive: 4 when dividing into zero, 10 or 29 when an overflow occurs, and 30 normally. When the dividend is negative: 4 when dividing into zero, 11 or 30 when an overflow occurs, and 31 normally. When the dividend is positive: 4 + (a) when dividing into zero, 11 + (a) or 30 + (a) when an overflow occurs, and 31 + (a) normally. When the dividend is negative: 4 + (a) when dividing into zero, 12 + (a) or 31 + (a) when an overflow occurs, and 32 + (a) normally. (b) when dividing into zero or when an overflow occurs, and 2 x (b) normally. (c) when dividing into zero or when an overflow occurs, and 2 x (c) normally. 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative.
*6: *7: *8: *9: *10: *11: *12: *13:
Note: Which of the two values given for the number of execution cycles applies when an overflow error occurs in a DIV or DIVW instruction depends on whether the overflow was detected before or after the operation.
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Table 14 Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW NOTW NOTW NOTW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam A A, #imm16 A, ear A, eam ear, A eam, A A A, #imm16 A, ear A, eam ear, A eam, A A A, #imm16 A, ear A, eam ear, A eam, A A ear eam # ~ Logical 1 Instructions (Byte, Word) [39 Instructions] B Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A) byte (A) not (A) byte (ear) not (ear) byte (eam) not (eam) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A) word (A) not (A) word (ear) not (ear) word (eam) not (eam)
LH AH I S T N Z V C RMW
2 2 0 2 2 0 2+ 3+ (a) (b) 2 3 0 2+ 3+ (a) 2x (b) 2 2 0 2 2 0 2+ 3+ (a) (b) 2 3 0 2+ 3+ (a) 2x (b) 2 2 0 2 2 0 2+ 3+ (a) (b) 2 3 0 2+ 3+ (a) 2x (b) 1 2 0 2 2 0 2+ 3+ (a) 2x (b) 1 2 0 3 2 0 2 2 0 2+ 3+ (a) (c) 2 3 0 2+ 3+ (a) 2x (c) 1 2 0 3 2 0 2 2 0 2+ 3+ (a) (c) 2 3 0 2+ 3+ (a) 2x (c) 1 2 0 3 2 0 2 2 0 2+ 3+ (a) (c) 2 3 0 2+ 3+ (a) 2x (c) 1 2 0 2 2 0 2+ 3+ (a) 2x (c)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - * * - - - * * - - - * * - * * - - - - * * - - - - * * - - - - * * - * *
For an explanation of "(a)", "(b)", "(c)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 15 Mnemonic ANDL A, ear ANDL A, eam ORL ORL A, ear A, eam # ~ Logical 2 Instructions (Long Word) [6 Instructions] B 0 (d) 0 (d) 0 (d) Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam)
LH AH I S T N Z V C RMW
2 5 2+ 6+ (a) 2 5 2+ 6+ (a) 2 5 2+ 6+ (a)
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
* * * * * *
* * * * * *
R R R R R R
- - - - - -
- - - - - -
XORL A, ear XORL A, eam
For an explanation of "(a)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
Table 16 Mnemonic NEG NEG NEG A ear eam # 1 ~ 2
Sign Inversion Instructions (Byte/Word) [6 Instructions] B 0 Operation byte (A) 0 - (A)
LH AH I S T N Z V C RMW
X - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
* * * * * *
* * * * * *
* * * * * *
* * * * * *
- * * - * *
2 2 0 byte (ear) 0 - (ear) 2+ 3+ (a) 2x (b) byte (eam) 0 - (eam) 1 2 0 word (A) 0 - (A)
NEGW A NEGW ear NEGW eam
2 2 0 word (ear) 0 - (ear) 2+ 3+ (a) 2x (c) word (eam) 0 - (eam)
For an explanation of "(a)", "(b)" and "(c)" and refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
Table 17 Mnemonic ABS A ABSW A ABSL A # 2 2 2
Absolute Value Instructions (Byte/Word/Long Word) [3 Insturctions] ~ 2 2 4 B 0 0 0 Operation byte (A) absolute value (A) word (A) absolute value (A) long (A) absolute value (A)
LH AH I S T N Z V C RMW
Z - -
- - -
- - -
- - -
- - -
* * *
* * *
* * *
- - -
- - -
Table 18 Mnemonic NRML A, R0 # 2 ~ * B 0
Normalize Instructions (Long Word) [1 Instruction] Operation long (A) Shifts to the position at which "1" was set first byte (R0) current shift count
LH AH I S T N Z V C RMW
-
-
-
-
*
-
-
-
-
-
* : 5 when the contents of the accumulator are all zeroes, 5 + (R0) in all other cases.
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Table 19 Mnemonic RORC A ROLC A RORC RORC ROLC ROLC ASR LSR LSL
ASR LSR LSL
Shift Instructions (Byte/Word/Long Word) [27 Instructions] B 0 0 Operation byte (A) Right rotation with carry byte (A) Left rotation with carry byte (ear) Right rotation with carry byte (eam) Right rotation with carry byte (ear) Left rotation with carry byte (eam) Left rotation with carry
byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0)
byte (A) Arithmetic right barrel shift (A, imm8) byte (A) Logical right barrel shift (A, imm8) byte (A) Logical left barrel shift (A, imm8) LH AH I S T N Z V C RMW
# 2 2
~ 2 2
- - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - * * - * * -
* * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * *
- - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * *
- - * * * * - - - - - - - - - - - - - - - - - - - - -
ear eam ear eam A, R0 A, R0 A, R0
2 2 0 2+ 3+ (a) 2x (b) 2 2 0 2+ 3+ (a) 2x (b) 2 2 2 *1 *1 *1 *3 *3 *3 2 2 2 *1 *1 *1 *3 *3 *3 *2 *2 *2 *4 *4 *4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A, #imm8 3 A, #imm8 3 A, #imm8 3
ASRW A
1
LSRW A/SHRW A 1 LSLW A/SHLW A 1
word (A) Arithmetic right shift (A, 1 bit) word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit)
** *R -* * * - * * - * * - * * - * * * * * * * * * * * *
ASRW A, R0 LSRW A, R0 LSLW A, R0
2 2 2
word (A) Arithmetic right barrel shift (A, R0) -
word (A) Logical right barrel shift (A, R0) - word (A) Logical left barrel shift (A, R0) -
word (A) Arithmetic right barrel shift (A, imm8) word (A) Logical right barrel shift (A, imm8)
ASRW A, #imm8 3 LSRW A, #imm8 3 LSLW A, #imm8 3
word (A) Logical left barrel shift (A, imm8)
- - -
ASRL A, R0 LSRL A, R0 LSLL A, R0
ASRL LSRL LSLL
2 2 2
long (A) Arithmetic right shift (A, R0) - long (A) Logical right barrel shift (A, R0) - long (A) Logical left barrel shift (A, R0) - long (A) Arithmetic right shift (A, imm8) - long (A) Logical right barrel shift (A, imm8) - long (A) Logical left barrel shift (A, imm8) -
A, #imm8 3 A, #imm8 3 A, #imm8 3
For an explanation of "(a)" and "(b)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." *1: *2: *3: *4: 3 when R0 is 0, 3 + (R0) in all other cases. 3 when R0 is 0, 4 + (R0) in all other cases. 3 when imm8 is 0, 3 + (imm8) in all other cases. 3 when imm8 is 0, 4 + (imm8) in all other cases.
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Table 20 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP rel rel rel rel # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 ~ * *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 2 3 4+ (a) 3 4+ (a) 3
1
Branch 1 Instructions [31 Instructions] Operation Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0 ( (V) xor (N) ) or (Z) = 1 ( (V) xor (N) ) or (Z) = 0 Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam) word (PC) (ear), (PCB) (ear +2) word (PC) (eam), (PCB) (eam +2) word (PC) ad24 0 to 15 (PCB) ad24 16 to 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call linstruction word (PC) (ear) 0 to 15, (PCB) (ear) 16 to 23 word (PC) (eam) 0 to 15, (PCB) (eam) 16 to 23 word (PC) addr 0 to 15, (PCB) addr 16 to 23
LH AH I S T N Z V C RMW
B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@A addr16 @ear @eam @ear *3 @eam *3 addr24
@ear *4 2 @eam *4 2+ addr16 *5 3 1 #vct4 *5 2 @ear *6 2+ 4
4 (c) 5+ (a) 2x (c) 5 (c) 5 2x (c) 7 2x (c) 8+ (a) 7 *2 2x (c)
CALLP @eam *6 CALLP addr24 *7
For an explanation of "(a)", "(c)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." *1: *2: *3: *4: *5: *6: *7: 3 when branching, 2 when not branching. 3 x (c) + (b) Read (word) branch address. W: Save (word) to stack; R: Read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: Read (long word) branch address. Save (long word) to stack.
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Table 21 Mnemonic # ~ * *1 *1 *3 *1 *3 *2 *4 *2 *4 14 12 13 14 9 11 6
1
Branch 2 Instructions [20 Instructions] Operation
Branch when byte (A) imm8 Branch when byte (A) imm16 Branch when byte (ear) imm8 Branch when byte (eam) imm8 Branch when word (ear) imm16 Branch when word (eam) imm16
LH AH I S T N Z V C RMW
B 0 0 0 (b) 0 (c) 0
CBNE A, #imm8, rel 3 CWBNE A, #imm16, rel 4
CBNE CBNE CWBNE CWBNE ear, #imm8, rel eam, #imm8, rel ear, #imm16, rel eam, #imm16, rel
- - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - -
- - - - - - - - - - R R R R * * -
- - - - - - - - - - S S S S * * -
- - - - - - - - - - - - - - * * -
* * * * * * * * * * - - - - * * -
* * * * * * * * * * - - - - * * -
* * * * * * * * * * - - - - * * -
* * * * * * - - - - - - - - * * -
- - - - - - - * - * - - - - - - -
4 4+ 5 5+ 3 3+ 3 3+ 2 3 4 1 1 2 2
DBNZ DBNZ
ear, rel eam, rel
DWBNZ ear, rel DWBNZ eam, rel INT #vct8 INT addr16 INTP addr24 INT9 RETI RETIQ *6 LINK #imm8
Branch when byte (ear) = (ear) - 1, and (ear) 0 2x (b) Branch when byte (ear) = (eam) - 1, and (eam) 0 0 Branch when word (ear) = (ear) - 1, and (ear) 0 2x (c) Branch when word (eam) = (eam) - 1, and (eam) 0 8x (c) 6x (c) 6x (c) 8x (c) 6x (c) *5 (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt Return from interrupt At constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. Return from subroutine Return from subroutine
5 UNLINK RET *7 RETP *8 1 4 5 1 1 (c) (d) (c)
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
For an explanation of "(b)", "(c)" and "(d)", refer to Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." *1: *2: *3: *4: *5: *6: 4 when branching, 3 when not branching 5 when branching, 4 when not branching 5 + (a) when branching, 4 + (a) when not branching 6 + (a) when branching, 5 + (a) when not branching 3 x (b) + 2 x (c) when an interrupt request is generated, 6 x (c) when returning from the interrupt. High-speed interrupt return instruction. When an interrupt request is detected during this instruction, the instruction branches to the interrupt vector without performing stack operations when the interrupt is generated. *7: Return from stack (word) *8: Return from stack (long word)
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Table 22 Mnemonic PUSHW PUSHW PUSHW PUSHW POPW POPW POPW POPW JCTX AND OR A AH PS rlst A AH PS rlst @A # 1 1 1 2 1 1 1 2 1 Other Control Instructions (Byte/Word/Long Word) [36 Instructions] ~ 3 3 3 *3 3 3 3 *2 9 3 3 2 2 B (c) (c) (c) *4 (c) (c) (c) *4 Operation
word (SP) (SP) -2, ((SP)) (A) word (SP) (SP) -2, ((SP)) (AH) word (SP) (SP) -2, ((SP)) (PS) (SP) (SP) -2n, ((SP)) (rlst) word (A) ((SP)), (SP) (SP) +2 word (AH) ((SP)), (SP) (SP) +2 word (PS) ((SP)), (SP) (SP) +2 (rlst) ((SP)) , (SP) (SP)
LH AH I S T N Z V C RMW
- - - - - - - - -
- - - - * - - - - - - - - - - * * - - * - - - - - - - - - - - - - - - -
- - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - * - * * * - - - - - - - - * * * - - - - - - - - - - - - - -
- - - - - - * - * * * - - - - - - - - * * * - - - - - - - - - - - * * *
- - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6x (c) Context switch instruction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCR, #imm8 2 CCR, #imm8 2 2 2
byte (CCR) (CCR) and imm8 - - byte (CCR) (CCR) or imm8 byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam word (SP) ext (imm8) word (SP) imm16 byte (A) (brgl) byte (brg2) (A) byte (brg2) imm8 No operation
Prefix code for AD space access Prefix code for DT space access Prefix code for PC space access Prefix code for SP space access
MOV RP #imm8 , MOV ILM, #imm8 MOVEA RWi, ear MOVEA RWi, eam MOVEA A, ear MOVEA A, eam ADDSP #imm8 ADDSP #imm16 MOV MOV
MOV
- - - - - - - - Z - - - - - - - - - - - - - Z Z Z
2 3 2+ 2+ (a) 2 2 2+ 1+ (a) 2 3 2 2 3 1 1 1 1 1 1 1 3 3 *1 1 2 1 1 1 1 1 1 1 2 2 2 2 *5 *6 *7
A, brgl brg2, A
brg2, #imm8
NOP ADB DTB PCB SPB NCC CMR
Prefix code for no flag change
Prefix code for the common register bank
MOVW SPCU, #imm16 4 MOVW SPCL, #imm16 4
SETSPC CLRSPC BTSCN A BTSCNSA BTSCNDA
2 2 2 2 2
word (SPCU) (imm16) word (SPCL) (imm16) Stack check operation enable Stack check operation disable
byte (A) position of "1" bit in word (A) byte (A) position of "1" bit in word (A) x 2 byte (A) position of "1" bit in word (A) x 4
For an explanation of "(a)" and "(c)", refer to Tables 4 and 5. *1: PCB, ADB, SSB, USB, and SPB: 1 cycle DTB: 2 cycles DPR: 3 cycles *2: 3 + 4 x (pop count) *3: 3 + 4 x (push count) *4: *5: *6: *7: Pop count x (c), or push count x (c) 3 when AL is 0, 5 when AL is not 0. 4 when AL is 0, 6 when AL is not 0. 5 when AL is 0, 7 when AL is not 0.
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Table 23 Mnemonic MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A SETB SETB SETB CLRB CLRB CLRB BBC BBC BBC BBS BBS BBS SBBS dir:bp addr16:bp io:bp dir:bp addr16:bp io:bp dir:bp, rel addr16:bp, rel io:bp, rel dir:bp, rel addr16:bp, rel io:bp, rel addr16:bp, rel # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 ~ 3 3 3 4 4 4 4 4 4 4 4 4 *1 *1 *1 *1 *1 *1 *2 *3 *3 Bit Manipulation Instructions [21 Instructions] B (b) (b) (b) Operation byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b
LH AH I S T N Z V C RMW
Z Z Z - - - - - - - - - - - - - - - - - -
* * * - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
* * * * * * - - - - - - - - - - - - - - -
* * * * * * - - - - - - * * * * * * * - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - * * * * * * * * * - - - - - - * - -
2x (b) bit (dir:bp) b (A) 2x (b) bit (addr16:bp) b (A) 2x (b) bit (io:bp) b (A) 2x (b) bit (dir:bp) b 1 2x (b) bit (addr16:bp) b 1 2x (b) bit (io:bp) b 1 2x (b) bit (dir:bp) b 0 2x (b) bit (addr16:bp) b 0 2x (b) bit (io:bp) b 0 (b) (b) (b) (b) (b) (b) 2x (b) *4 *4 Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1
Branch when (addr16:bp) b = 1, bit = 1
WBTS io:bp WBTC io:bp
Wait until (io:bp) b = 1 Wait until (io:bp) b = 0
For an explanation of "(b)", refer to Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." *1: *2: *3: *4: 5 when branching, 4 when not branching 7 when condition is satisfied, 6 when not satisfied Undefined count Until condition is satisfied
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Table 24 Mnemonic SWAP SWAPW EXT EXTW ZEXT ZEXTW # 1 1 1 1 1 1 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] ~ 3 2 1 2 1 2 B 0 0 0 0 0 0 Operation byte (A) 0 to 7 (A) 8 to 15 word (AH) (AL) Byte code extension Word code extension Byte zero extension Word zero extension
LH AH I S T N Z V C RMW
- - X - Z -
- * - X - Z
- - - - - -
- - - - - -
- - - - - -
- - * * R R
- - * * * *
- - - - - -
- - - - - -
- - - - - -
Table 25 Mnemonic MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FILS/FILSI
MOVSW/MOVSWI
String Instructions [10 Instructions] Operation
LH AH I S T N Z V C RMW
# 2 2 2 2
~ *2 *2 *1 *1
B
*3 Byte transfer @AH+ @AL+, counter = RW0 - *3 Byte transfer @AH- @AL-, counter = RW0 - *4 Byte retrieval @AH+ - AL, counter = RW0 *4 Byte retrieval @AH- - AL, counter = RW0 - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - * * * - - * * *
- - * * * - - * * *
- - * * - - - * * -
- - * * - - - * * -
- - - - - - - - - -
2 5m +3 *5 Byte filling @AH+ AL, counter = RW0 2 2 2 2 *2 *2 *1 *1 *6 Word transfer @AH+ @AL+, counter = RW0 *6 Word transfer @AH- @AL-, counter = RW0 *7 Word retrieval @AH+ - AL, counter = RW0 *7 Word retrieval @AH- - AL, counter = RW0
MOVSWD
SCWEQ/SCWEQI
SCWEQD FILSW/FILSWI
2 5m +3 *8 Word filling @AH+ AL, counter = RW0
m: RW0 value (counter value) *1: *2: *3: *4: *5: *6: *7: *8: 3 when RW0 is 0, 2 + 6 x (RW0) for count out, and 6n + 4 when match occurs 4 when RW0 is 0, 2 + 6 x (RW0) in any other case (b) x (RW0) (b) x n (b) x (RW0) (c) x (RW0) (c) x n (c) x (RW0)
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Table 26 Mnemonic
@A, @RLi, #imm8 @A, eam, #imm8 addr16, @RLi, #imm8 addr16, eam, #imm8 @A, @RLi, #imm8 @A, eam, #imm8 addr16, @RLi, #imm8 addr16, eam, #imm8 @RLi, @A, #imm8 eam, @A, #imm8 @RLi, addr16, #imm8 eam, addr16, #imm8 @RLi, @A, #imm8 eam, @A, #imm8 @RLi, addr16, #imm8 eam, addr16, #imm8 bnk : addr16, *5 bnk : addr16, #imm8 MOVMW bnk : addr16, *5 bnk : addr16, #imm8 MOVM MOVM MOVM MOVM MOVMW MOVMW MOVMW MOVMW MOVM MOVM MOVM MOVM MOVMW MOVMW MOVMW MOVMW MOVM
Multiple Data Transfer Instructions [18 Instructions] B * *3 *3 *3 *4 *4 *4 *4 *3 *3 *3 *3 *4 *4 *4 *4 *3 *4
3
# 3 3+ 5 5+ 3 3+ 5 5+ 3 3+ 5 5+ 3 3+ 5 5+ 7 7
~ * *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *1
1
Operation
Multiple data trasfer byte ((A)) ((RLi)) Multiple data trasfer byte ((A)) (eam) Multiple data trasfer byte (addr16) ((RLi)) Multiple data trasfer byte (addr16) (eam) Multiple data trasfer word ((A)) ((RLi)) Multiple data trasfer word ((A)) (eam) Multiple data trasfer word (addr16) ((RLi)) Multiple data trasfer word (addr16) (eam) Multiple data trasfer byte ((RLi)) ((A)) Multiple data trasfer byte (eam) ((A))
Multiple data transfer byte ((RLi)) (addr16) Multiple data transfer byte (eam) (addr16)
LH AH
I
S
T
N
Z
V
C RMW
Multiple data trasfer word ((RLi)) ((A))
Multiple data trasfer word (eam) ((A)) Multiple data transfer word ((RLi)) (addr16) Multiple data transfer word (eam) (addr16)
Multiple data transfer byte (bnk:addr16) (bnk:addr16) Multiple data transfer word (bnk:addr16) (bnk:addr16)
- - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
*1: 5 + imm8 x 5, 256 times when imm8 is zero. *2: 5 + imm8 x 5 + (a), 256 times when imm8 is zero. *3: Number of transfers x (b) x 2 *4: Number of transfers x (c) x 2 *5:The bank register specified by "bnk" is the same as for the MOVS instruction.
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MB90230 Series
s ORDERING INFORMATION
Model MB90233PFV-XXX MB90234PFV-XXX MB90234PFV MB90W234ZFV Package 100-pin Plastic LQFP (FPT-100P-M05) 100-pin Plastic LQFP (FPT-100P-M05) 100-pin Ceramic SQFP (FPT-100C-C01) Only ES Only ES Remarks
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MB90230 Series
s PACKAGE DIMENSIONS
100-pin Plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ
75
14.000.10(.551.004)SQ
51
1.50 -0.10 (Mounting height) +.008 .059 -.004
+0.20
76
50
12.00 (.472) REF INDEX
15.00 (.591) NOM
Details of "A" part 0.15(.006)
100
26
0.15(.006) 0.15(.006)MAX
LEAD No.
1
25
"B"
+0.05 -0.02 +.002 -.001
"A" 0.50(.0197)TYP 0.18 .007
+0.08 -0.03 +.003 -.001
0.40(.016)MAX 0.127 .005
0.08(.003)
M
Details of "B" part 0.100.10 (STAND OFF) (.004.004)
0.10(.004)
0.500.20(.020.008) 0~10
C
1995 FUJITSU LIMITED F100007S-2C-3
Dimensions in mm (inches)
100-pin Ceramic LQFP (FPT-100C-C01)
16.000.20 SQ (.630.008) 13.60 -0.15 SQ +.010 .535 -.006 12.00(.472)REF 0.50(.0197)TYP 0.200.05 (.008.002)
+0.25
1.70(.067)MAX
(Mounting height)
0.90(.035)REF
Details of "A" part
15.000.25 SQ (.5910.10)
0.1250.05 (.005.002)
0(0)MIN STAND OFF
INDEX AREA 0.500.20 (.020.008)
"A"
C
1995 FUJITSU LIMITED F100015SC-1-3
Dimensions in mm (inches)
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MB90230 Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9901 (c) FUJITSU LIMITED Printed in Japan
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