View EDI88128C100CB_281092.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

EDI88128C
128KX8 MONOLITHIC SRAM, SMD 5962-89598
n Access Times of 70, 85, 100ns n Available with Single Chip Selects (EDI88128) or Dual Chip Selects (EDI88130) n 2V Data Retention (LP Versions) n CS and OE Functions for Bus Control n TTL Compatible Inputs and Outputs n Fully Static, No Clocks n Organized as 128Kx8 n Industrial, Military and Commercial Temperature Ranges n Thru-hole and Surface Mount Packages JEDEC Pinout * 32 pin Ceramic DIP, 0.6 mils wide (Package 9) * 32 lead Ceramic SOJ (Package 140) n Single +5V (10%) Supply Operation
FEATURES
The EDI88128C is a high speed, high performance, Monolithic CMOS Static RAM organized as 128Kx8. The device is also available as EDI88130C with an additional chip select line (CS2) which will automatically power down the device when proper logic levels are applied. The second chip select line (CS2) can be used to provide system memory security during power down in non-battery backed up systems and simplifiy decoding schemes in memory banking where large multiple pages of memory are required. The EDI88128C and the EDI88130C have eight bi-directional input-output lines to provide simultaneous access to all bits in a word. An automatic power down feature permits the on-chip circuitry to enter a very low standby mode and be brought back into operation at a speed equal to the address access time. Low power versions, EDI88128LP and EDI88130LP, offer a 2V data retention function for battery back-up opperation. Military product is available compliant to Appendix A of MIL-PRF-38535.
FIG. 1
PIN CONFIGURATION
32 DIP 32 SOJ
PIN DESCRIPTION
I/O0-7 A0-16 WE CS1, CS2 Data Inputs/Outputs Address Inputs Write Enable Chip Selects Output Enable Power (+5V 10%) Ground Not Connected
TOP VIEW
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AO I/OO I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 VCC 31 A15 30 NC/CS2* 29 WE 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CS1 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3
OE VCC VSS NC
BLOCK DIAGRAM
* Pin 30 is NC for 88128 or CS2 for 88130.
1
March 2002 Rev. 16
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
EDI88128C
ABSOLUTE MAXIMUM RATINGS
Parameter Unit O E CS1 CS2 WE
TRUTH TABLE
Mode Output Power
Voltage on any pin relative to Vss
Operating T emperature TA (Ambient)
-0.5 to 7.0
V
Commercial Industrial Military Storage Temperature, Plastic Power Dissipation Output Current Junction Temperature, TJ
0 to +70 -40 to +85 -55 to +125 -65 to +150 1 20 175
C C C C W mA C
X X X H L X
H X X L L L
X L L H H H
X X X H H L
Standby Standby Output Deselect Output Deselect Read Write
High Z High Z High Z High Z Data Out Data In
Icc2, Icc3 Icc2, Icc3 Icc1 Icc1 Icc1 Icc1
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min T yp Max Unit
NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Supply Voltage Supply Voltage Input High Voltage Input Low Voltage
VCC VSS VIH VIL
4.5 0 2.2 -0.3
5.0 0 -- --
5.5 0 Vcc +0.5 +0.8
V V V V
CAPACITANCE (TA = +25C)
Parameter Symbol Condition Max Unit
Address Lines Input/Output Lines
CI CO
VIN = Vcc or Vss, f = 1.0MHz VOUT = Vcc or Vss, f = 1.0MHz
12 14
pF pF
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS (VCC = 5V, TA = -55C +125C)
TO Parameter Symbol Conditions Min Typ Max Units
Input Leakage Current Output Leakage Current Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current Output Low Voltage Output High Voltage
ILI ILO ICC1 ICC2 ICC3 VOL VOH
VIN = 0V to VCC VI/O = 0V to VCC, CS1 VIH and/or CS2 VIL WE, CS1 = VIL, II/O = 0mA, Min Cycle CS2 = VIH CS1 VIH and/or CS2 VIL, VIN VIH or VIL CS1 VCC -0.2V and/or CS2 Vcc +0.2V VIN Vcc -0.2V or VIN 0.2V IOL = 2.1mA IOH = -1.0mA C LP (70-85ns) (100ns)
-5 -10 -- -- -- -- -- -- 2.4
-- --
+5 +10 120 110 10
A A mA mA mA mA mA V V
1 -- -- --
5 1 0.4 --
NOTE: DC test conditions : VIL = 0.3V, VIH = Vcc -0.3V
White Electronic Designs Corporation * Phoenix AZ * (602) 437-1520
2
EDI88128C
AC CHARACTERISTICS READ CYCLE (VCC = 5.0V, VSS = 0V, TA = -55C +125C)
TO Symbol Parameter JEDEC Alt. Min 70ns Max Min 85ns Max Min 100ns Max Units
Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low Z (1) Chip Disable to Output in High Z (1) OutputHoldfromAddressChange OutputEnabletoOutputValid Output Enable to Output in Low Z (1) Output Disable to Output in High Z (1)
tAVAV tAVQV tELQV tSHQV tELQX tSHQX tEHQZ tSLQZ tAVQX tGLQV tGLQX tGHQZ
tRC tAA tACS tACS tCLZ tCLZ tCHZ tCHZ tOH tOE tOLZ tOHZ
70 70 70 70 3 3 0 0 3 25 0 0 30 30 30
85 85 85 85 3 3 0 0 3 30 0 0 30 30 30
100 100 100 100 3 3 0 0 3 50 0 0 30 30 30
ns ns ns ns ns ns ns ns ns ns ns ns
1. This parameter is guaranteed by design but not tested.
AC TEST CONDITIONS
Figure 1
Vcc
Figure 2
Vcc
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load
480
VSS to 3.0V 5ns 1.5V Figure 1
480
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
Q
255 30pF
Q
255 5pF
3
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
EDI88128C
AC CHARACTERISTICS WRITE CYCLE (VCC = 5.0V, VSS = 0V, TA = -55C +125C)
TO Symbol Parameter JEDEC Alt. Min 70ns Max Min 85ns Max Min 100ns Max Units
Write Cycle Time Chip Select to End of Write
tAVAV tELWH tELEH tSHWH tSHSL tAVWL tAVEL tAVSH tAVWH tWLWH tWLEH tWLSL tWHAX tEHAX tSLAX tWHDX tEHDX tSLDX tWLQZ tDVWH tDVEH tDVSL tWHQX
tWC tCW tCW tCW tCW tAS tAS tAS tAW tWP tWP tWP tWR tWR tWR tDH tDH tDH tWHZ tDW tDW tDW tWLZ
70 60 60 60 60 0 0 0 60 35 35 35 5 5 5 0 0 0 0 35 35 35 5 30
85 75 75 75 75 0 0 0 75 70 70 70 5 5 5 0 0 0 0 40 40 40 5 35
100 85 85 85 85 0 0 0 85 80 80 80 5 5 5 0 0 0 0 40 40 40 5 40
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Address Setup Time
Address Valid to End of Write Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1) Data to Write Time
Output Active from End of Write (1)
1. This parameter is guaranteed by design but not tested.
White Electronic Designs Corporation * Phoenix AZ * (602) 437-1520
4
EDI88128C
FIG. 2 TIMING WAVEFORM - READ CYCLE
ADDRESS
tAVAV tAVQV
CS1
tELQV tELQX
tAVAV
ADDRESS
ADDRESS 1 ADDRESS 2
tEHQZ
CS2
tSHQV tSHQX
OE
tSLQZ
tAVQV
DATA I/O
tAVQX
DATA 1 DATA 2
tGLQV tGLQX
DATA I/O READ CYCLE 2 (WE HIGH)
tGHQZ
READ CYCLE 1 (WE HIGH; OE, CS LOW)
FIG. 3 WRITE CYCLE 1
tAVAV
ADDRESS
tAVWL
WE
tAVWH tWLWH
tWHAX
CS1
tELWH
CS2
tSHWH
DATA IN
tDVWH
DATA VALID
tWHQX tWHDX
tWLQZ
DATA OUT
HIGH Z
WRITE CYCLE 1 - LATE WRITE, WE CONTROLLED
FIG. 4 WRITE CYCLE 2
tAVAV
ADDRESS
WRITE CYCLE 3
WS32K32-XHX
ADDRESS
tAVAV tSLAX
tAVEL
WE
tWLEH
tEHAX
WE
tAVSH
tWLSL
tELEH
CS1
CS1
tSHSL
CS2
CS2
tDVEH
DATA IN
DATA VALID
tEHDX
DATA IN
tDVSL
DATA VALID
tSLDX
WRITE CYCLE 2 - EARLY WRITE, CS1 CONTROLLED
WRITE CYCLE 3 - EARLY WRITE, CS2 CONTROLLED
5
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
EDI88128C
DATA RETENTION CHARACTERISTICS (EDI88128LP & EDI88130LP ONLY) (TA = -55C +125C)
TO Characteristic Sym Conditions Min Typ Max Units
Low Power Version only
Data Retention Voltage Data Retention Quiescent Current Chip Disable to Data Retention Time (1) Operation Recovery Time (1)
VDD ICCDR TCDR TR
VDD = 2.0V CS1 VDD -0.2V VIN VDD -0.2V or VIN 0.2V
2 - 0 TAVAV*
- - - -
- 400 - -
V A ns ns
NOTE: 1. Parameter guaranteed by design, but not tested. * Read Cycle Time
FIG. 5 DATA RETENTION - CS1 CONTROLLED
Data Retention Mode
Vcc
4.5V VDD
WS32K32-XHX
4.5V
tCDR
CS1
CS1 VDD -0.2V
tR
DATA RETENTION, CS1 CONTROLLED
FIG. 6 DATA RETENTION - CS2 CONTROLLED
Data Retention Mode
Vcc
4.5V VDD
WS32K32-XHX
4.5V
tCDR
CS2
CS2 0.2V
tR
DATA RETENTION, CS2 CONTROLLED
White Electronic Designs Corporation * Phoenix AZ * (602) 437-1520
6
EDI88128C
PACKAGE 9: 32 PIN SIDEBRAZED CERAMIC DIP (600MILS WIDE)
1.616 1.584
Pin 1 Indicator 0.200 0.125 0.061 0.017 0.020 0.016 15 x 0.100 = 1.500
0.060 0.040
0.620 0.600
0.100 TYP
0.155 0.115
0.600 NOM
ALL Dimensions ARE in inches
PACKAGE 140: 32 LEAD CERAMIC SOJ
0.010 0.006 0.019 0.015
0.840 0.820
0.444 0.430
0.379 0.155 0.106
ALL Dimensions ARE in inches
0.050 TYP
7
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
EDI88128C
ORDERING INFORMATION
EDI 8 8 128 C X X X
WHITE ELECTRONIC DESIGNS
SRAM
ORGANIZATION, 128Kx8
8 130 = Dual Chip Select
TECHNOLOGY:
C = CMOS Standard Power LP = Low Power
ACCESS TIME (ns)
PACKAGE TYPE:
C = 32 lead Sidebrazed DIP, 600 mil (Package 9) N = 32 lead Ceramic SOJ (Package 140)
DEVICE GRADE:
B = MIL-STD-883 Compliant M = Military Screened I = Industrial C = Commercial
-55C to +125C -40C to +85C 0C to +70C
White Electronic Designs Corporation * Phoenix AZ * (602) 437-1520
8

▲Up To Search▲

Price & Availability of EDI88128C100CB

	To Download EDI88128C100CB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .