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(R)
LCP1521
PROGRAMMABLE TRANSIENT VOLTAGE SUPPRESSOR FOR SLIC PROTECTION
A.S.D.TM
FEATURES
s
s
s
s
s
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Dual programmable transient suppressor Wide negative firing voltage range: VMGL = -150 V max. Low dynamic switching voltages: VFP and VDGL Low gate triggering current: IGT = 5 mA max Peak pulse current: IPP = 30 A (10/1000 s) Holding current: IH = 150 mA min
DESCRIPTION This device has been especially designed to protect new high voltage, as well as classical SLICs, against transient overvoltages. Positive overvoltages are clamped by 2 diodes. Negative surges are suppressed by 2 thyristors, their breakdown voltage being referenced to -VBAT through the gate. This component presents a very low gate triggering current (IGT) in order to reduce the current consumption on printed circuit board during the firing phase. A particular attention has been given to the internal wire bonding. The Kelvin method configuration ensures reliable protection, reducing the overvoltage introduced by the parasitic inductances of the wiring, especially for very fast transients.
SO-8
FUNCTIONAL DIAGRAM
TIP
1
TIP
GATE
GND
NC
GND
BENEFITS Trisils are not subject to ageing and provide a fail safe mode in short circuit for a better protection. Trisils are used to help equipment to meet various standards such as UL1950, IEC950 / CSA C22.2, UL1459 and FCC part68. Trisils have UL94 V0 resin approved (Trisils are UL497B approved (file: E136224)).
RING
RING
January 2002 - Ed: 3B
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LCP1521
IN COMPLIANCES WITH THE FOLLOWING STANDARDS STANDARD GR-1089 Core First level GR-1089 Core Second level GR-1089 Core Intra-building ITU-T-K20/K21 ITU-T-K20 (IEC61000-4-2) VDE0433 VDE0878 IEC61000-4-5 FCC Part 68, lightning surge type A FCC Part 68, lightning surge type B Peak Surge Voltage (V) 2500 1000 5000 1500 6000 1500 8000 15000 4000 2000 4000 2000 4000 4000 1500 800 1000 Voltage Waveform 2/10s 10/1000s 2/10s 2/10s 10/700s 1/60 ns 10/700s 1.2/50s 10/700s 1.2/50s 10/160s 10/560s 9/720s Required peak current (A) 500 100 500 100 150 37.5 Minimum serial Current resistor to meet Waveform standard () 2/10s 10/1000s 2/10s 2/10s 5/310s 10 24 20 0 110 0 0 0 60 10 0 0 60 0 22.5 15 0
ESD contact discharge ESD air discharge 100 50 100 50 100 100 200 100 25 5/310s 1/20s 5/310s 8/20s 10/160s 10/560s 5/320s
THERMAL RESISTANCE Symbol Rth (j-a) Junction to ambient Parameter Value 170 Unit C/W
ELECTRICAL CHARACTERISTICS (Tamb = 25C) Symbol IGT IH IRM IRG VRM VGT VF VFP VDGL VGATE VRG C Parameter Gate triggering current Holding current Reverse leakage current LINE / GND Reverse leakage current GATE / LINE Reverse voltage LINE / GND Gate triggering voltage Forward drop voltage LINE / GND Peak forward voltage LINE / GND Dynamic switching voltage GATE / LINE GATE / GND voltage Reverse voltage GATE / LINE Capacitance LINE / GND
IPP VR VRM VF IRM IR IH
I
V
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ABSOLUTE RATINGS (Tamb = 25C, unless otherwise specified). Symbol IPP Parameter Peak pulse current (see note1) 10/1000s 8/20s 10/560s 5/310s 10/160s 1/20s 2/10s t = 10ms t = 1s t = 10ms -40C < Tamb < +85C -40C < Tamb < +85C Value 30 100 35 40 50 100 170 20 5 2 -150 -150 - 55 to + 150 150 260 Unit A
ITSM
Non repetitive surge peak on-state current (50Hz sinusoidal) Maximum gate current (50Hz sinusoidal) Maximum voltage LINE/GND Maximum voltage GATE/LINE Storage temperature range Maximum junction temperature
A
IGSM VMLG VMGL Tstg Tj TL
A V C C
Maximum lead temperature for soldering during 10s
Repetitive peak pulse current tr: rise time (s) tp: pulse duration (s) ex: Pulse waveform 10/1000s tr = 10s tp = 1000s
% IPP
100 50 0 tr tp
t
1- PARAMETERS RELATED TO THE DIODE LINE / GND (Tamb = 25C) Symbol VF VFP (note 1) IF = 5A 10/700s 1.2/50s 2/10s 1.5kV 1.5kV 2.5kV Test conditions t = 500s RS = 10 RS = 10 RS = 62 Max 2 5 7 12 Unit V V
Note 1: see test circuit for VFP; RS is the protection resistor located on the line card.
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2 - PARAMETERS RELATED TO THE PROTECTION THYRISTOR (Tamb = 25C unless otherwise specified) Symbol IGT IH VGT IRG VDGL VGND / LINE = -48V VGATE = -48V (note 2) at IGT VRG = -150V VRG = -150V VGATE = -48V 10/700s 1.2/50s 2/10s (note 3) 1.5kV 1.5kV 2.5kV RS = 10 RS = 10 RS = 62 IPP = 30A IPP = 30A IPP = 38A 7 10 25 V Tc=25C Tc=85C Test conditions Min 0.1 150 2.5 5 50 Max 5 Unit mA mA V A
Note 2: see functional holding current (IH) test circuit Note 3: see test circuit for VDGL The oscillations with a time duration lower than 50ns are not taken into account
3 - PARAMETERS RELATED TO DIODE AND PROTECTION THYRISTOR (Tamb = 25C, unless otherwise specified) Symbol IRM C VGATE / LINE = -1V VGATE / LINE = -1V Test conditions VRM = -150V VRM = -150V Tc=25C Tc=85C 30 70 Typ. Max. 5 50 Unit A pF
VR = 50V bias, VRMS = 1V, F = 1MHz VR = 2V bias, VRMS = 1V, F = 1MHz
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LCP1521
FUNCTIONAL HOLDING CURRENT (IH) TEST CIRCUIT : GO-NO GO TEST
R
Surge generator
VBAT = - 100V
D.U.T
This is a GO-NO GO test which allows to confirm the holding current (IH) level in a functional test circuit. TEST PROCEDURE : - Adjust the current level at the IH value by short circuiting the D.U.T. - Fire the D.U.T. with a surge current : IPP = 10A, 10/1000s. - The D.U.T. will come back to the off-state within a duration of 50ms max.
TEST CIRCUIT FOR VFP AND VDGL PARAMETERS
(V is defined in unload condition)
P
R4 TIP R2 RING R3
L
VP
C1
R1
C2
G ND
Pulse (s) tr 10 1.2 2 tp 700 50 10
Vp (V) 1500 1500 2500
C1 (F) 20 1 10
C2 (nF) 200 33 0
L (H) 0 0 1.1
R1 () 50 76 1.3
R2 () 15 13 0
R3 () 25 25 3
R4 () 25 25 3
IPP (A) 30 30 38
Rs () 10 10 62
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TECHNICAL INFORMATION Fig. A1: LCP1521 concept behavior.
Rs1
L1
TIP IG ID1 T1 Gate Th1 D1 GND
V Tip
GND
-Vbat
C
Rs2
RING
VRing
L2
Figure A1 shows the classical protection circuit using the LCP1521 crowbar concept. This topology has been developed to protect the new high voltage SLIC's. It allows to program the negative firing threshold while the positive clamping value is fixed at GND. When a negative surge occurs on one wire (L1 for example) a current IG flows through the base of the transistor T1 and then injects a current in the gate of the thyristor Th1. Th1 fires and all the surge current flows through the ground. After the surge when the current flowing through Th1 becomes less negative than the holding current IH, then Th1 switches off. When a positive surge occurs on one wire (L1 for example) the diode D1 conducts and the surge current flows through the ground. Fig. A2: Example of PCB layout based on LCP1521 protection.
220 nF
To line side
GND
To SLIC side
In order to minimize the remaining voltage across the SLIC inputs during the surge, the TIP and RING pins of the LCP1521 are doubled (Pins 1 and 8 for TIP / Pins 4 and 5 for RING). This fact allows the board designer to connect the tracks like in figure A2. With such a PCB design, the extra voltages caused by track stray inductance remain located on the line side of the LCP and do not affects the SLIC side. The capacitor C is used to speed up the crowbar structure firing during the fast surge edges. This allows to minimize the dynamical breakover voltage at the SLIC Tip and Ring inputs during fast strikes. Note that this capacitor is generally present around the SLIC - Vbat pin. So to be efficient it has to be as close as possible from the LCP1521 Gate pin and from the reference ground track (or plan) (see Fig. A2). The optimized value for C is 220nF.
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The series resitors Rs1 and Rs2 designed in figure A1 represent the fuse resistors or the PTC which are mandatory to withstand the power contact or the power induction tests imposed by the various country standards. Taking into account this fact the actual lightning surge current flowing through the LCP is equal to: I surge = V surge / (Rg + Rs) With V surge = peak surge voltage imposed by the standard. Rg = series resistor of the surge generator Rs = series resistor of the line card (e.g. PTC)
e.g. For a line card with 30 of series resistors which has to be qualified under GR1089 Core 1000V 10/1000s surge, the actual current through the LCP1521 is equal to: I surge = 1000 / (10 + 30) = 25A The LCP1521 is particularly optimized for the new telecom applications such as the fiber in the loop, the WLL, the remote central office. In this case, the operating voltages are smaller than in the classical system. This makes the high voltage SLICs particularly suitable. The schematics of figure A3 gives the most frequent topology used for these applications.
Fig. A3: Protection of high voltage SLIC.
-Vbat Rs (*) TIP Gate TIP GND GND RING Rs (*) RING
Line
GND
220nF
SLIC
LCP1521 Line card
Rs (*) = PTC or Resitor fuse
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Fig. 1: Surge peak current versus overload duration. Fig. 2: Relative variation of holding current versus junction temperature
ITSM (A) 20 18 16 14 12 10 8 6 4 2 0 0.01
IH ( Tj ) / IH ( Tj=25C )
1.3 1.2 1.1 1 0.9 0.8
t(s) 0.1 1 10 100 1000
0.7 -40 -30 -20 -10 0 10
Tj ( C ) 20 30 40 50 60 70 80 90
ORDER CODE
LCP
LINE CARD PROTECTION
15
IH = 150 mA
2
1
PACKAGE 1 : SO-8
RL
VERSION
RL : Tape & Reel : Tube
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LCP1521
PACKAGE MECHANICAL DATA SO-8 (Plastic) DIMENSIONS REF.
L c1 C a3 a2 A b1
Millimetres Min. Typ. Max. 1.75 0.1 0.65 0.35 0.19 0.25 4.8 5.8 1.27 3.81 3.8 0.4 4.0 0.6 8 (max) 0.15 1.27 0.016 0.50 0.25 0.004 1.65 0.85 0.025 0.48 0.014 0.25 0.007 0.50 0.010 45 (typ) 5.0 6.2 0.189 0.228 Min.
Inches Typ. Max. 0.069 0.010 0.065 0.033 0.019 0.010 0.020 0.197 0.244 0.050 0.150 0.157 0.050 0.024
A a1 a2 a3 b b1 C c1 D
b e3
e
S
E
a1
D M
8
5 F
E e e3 F L M S
1
4
Order code LCP1521 LCP1521RL
Marking 151DHV 151DHV
Package SO-8 SO-8
Weight 0.08 g 0.08 g
Base qty 100 2000
Delivery mode Tube Tape & Reel
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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