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HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
Timing Diagrams 1 2 3 4 4.1 4.2 4.3 5 6 6.1 6.2 7 7.1 7.2 8 8.1 8.2 9 9.1 9.2 10 11 12 12.1 12.2 12.3 12.4 13 14 15 Bank Activate Command Cycle Burst Read Operation Read Interrupted by a Read Read to Write Interval Read to Write Interval Minimum Read to Write Interval Non-Minimum Read to Write Interval Burst Write Operation Write and Read Interrupt Write Interrupted by a Write Write Interrupted by a Read Burst Write and Read with Auto Precharge Burst Write with Auto Precharge Burst Read with Auto Precharge Burst Termination Termination of a full Page Burst Read Operation Termination of a full Page Burst Write Operation AC Parameters AC Parameters for a Write Timing AC Parameters for a Read Timing Mode Register Set Power on Sequence and Auto Refresh (CBR) Clock Suspension (Using CKE) Clock Suspension During Burst Read CAS Latency = 2 Clock Suspension During Burst Read CAS Latency = 3 Clock Suspension During Burst Write CAS Latency = 2 Clock Suspension During Burst Write CAS Latency = 3 Power Down Mode and Clock Suspend Self Refresh (Entry and Exit) Auto Refresh (CBR)
Semiconductor Group
1
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
Timing Diagrams (cont'd) 16 16.1 16.2 17 17.1 17.2 18 18.1 18.2 19 19.1 19.2 20 20.1 20.2 21 21.1 21.2 22 22.1 Random Column Read (Page within same Bank) CAS Latency = 2 CAS Latency = 3 Random Column Write (Page within same Bank) CAS Latency = 2 CAS Latency = 3 Random Row Read (Interleaving Banks) with Precharge CAS Latency = 2 CAS Latency = 3 Random Row Write (Interleaving Banks) with Precharge CAS Latency = 2 CAS Latency = 3 Full Page Read Cycle CAS Latency = 2 CAS Latency = 3 Full Page Write Cycle CAS Latency = 2 CAS Latency = 3 Precharge Termination of a Burst CAS Latency = 2
Semiconductor Group
2
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
1. Bank Activate Command Cycle
(CAS latency = 3)
T0 CLK T1 T T T T T
Address
Bank B Row Addr.
Bank B Col. Addr.
Bank A Row Addr.
Bank B Row Addr.
t RCD
Command
Bank B Activate
t RRD
NOP
Write B with Auto Precharge
NOP
Bank A Activate
NOP
Bank B Activate
t RC
"H" or "L"
SPT03784
2. Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Read A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
SPT03712
Semiconductor Group
3
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
3. Read Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Read A
Read B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
SPT03713
Semiconductor Group
4
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
4. Read to Write Interval 4.1. Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0 CLK Minimum delay between the Read and Write Commands = 4 + 1 = 5 cycles DQMx Write latency t DQW of DQMx T1 T2 T3 T4 T5 T6 T7 T8
t DQZ
Command NOP Read A NOP NOP NOP NOP Write B NOP NOP
DQ's
DOUT A0
DIN B0
DIN B1
DIN B2
Must be Hi-Z before the Write Command "H" or "L"
SPT03787
Semiconductor Group
5
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
4.2. Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
DQM
t DQW t DQZ
1 Clk Interval
Bank A Activate
Command
NOP
NOP
NOP
Read A
Write A
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's
Must be Hi-Z before the Write Command DIN A0 DIN A1 DIN A2 DIN A3
"H" or "L"
SPT03939
Semiconductor Group
6
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
4.3. Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
DQM
t DQW t DQZ
Command
NOP
Read A
NOP
NOP
Read A
NOP
Write B
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's "H" or "L"
Must be Hi-Z before the Write Command DOUT A0 DOUT A1 DIN B0 DIN B1 DIN B2
DOUT A0
DIN B0
DIN B1
DIN B2
SPT03940
Semiconductor Group
7
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
5. Burst Write Operation
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
NOP
Write A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQ's
DIN A0
DIN A1
DIN A2
DIN A3
don't care
The first data element and the Write are registered on the same clock edge.
Extra data is ignored after termination of a Burst.
SPT03790
Semiconductor Group
8
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
6. Write and Read Interrupt 6.1. Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
NOP
Write A
Write B
NOP
NOP
NOP
NOP
NOP
NOP
1 Clk Interval DQ's DIN A0 DIN B0 DIN B1 DIN B2 DIN B3
SPT03791
6.2. Write Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
NOP
Write A
Read B
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's
DIN A0
don't care
DOUT B0 DOUT B1 DOUT B2 DOUT B3
DIN A0
don't care
don't care
DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from the DQ's at least one clock cycle before the Read data appears on the outputs to avoid data contention.
SPT03719
Input data for the Write is ignored.
Semiconductor Group
9
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
7. Burst Write and Read with Auto Precharge 7.1. Burst Write with Auto Precharge
(Burst Length = 2, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Bank A Active
NOP
NOP
Write A Auto Precharge
NOP
NOP
NOP
NOP
NOP
t WR
DQ's DIN A0 DIN A1
t RP
Begin Auto Precharge Bank can be reactivated after t RP
SPT03909
7.2. Burst Read with Auto Precharge
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Read A with AP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t RP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3
t RP
DOUT A0 DOUT A1 DOUT A2 DOUT A3 Begin Auto Precharge Bank can be reactivated after t RP
SPT03721
Semiconductor Group
10
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
8. Burst Termination 8.1. Termination of a Full Page Burst Read Operation
(CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Read A
NOP
NOP
NOP
Burst Terminate
NOP
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3 The burst ends after a delay equal to the CAS latency.
SPT03722
8.2. Termination of a Full Page Burst Write Operation
(CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
NOP
Write A
NOP
NOP
Burst Terminate
NOP
NOP
NOP
NOP
CAS latency = 2, 3 DQ's
DIN A0
DIN A1
DIN A2
don't care
Input data for the Write is masked.
SPT03419
Semiconductor Group
11
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
9. AC Parameters 9.1. AC Parameters for a Write Timing
Burst Length = 4, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CH t CL
CKE
t CK2
t CKS
t CS t CH
Begin Auto Precharge Bank A
Begin Auto Precharge Bank B
t CKH
CS RAS CAS WE BS
t AH
AP
RAx RBx RAy RAz RBy
t AS
Addr. DQM
RAx CAx RBx CBx RAy RAy RAz RBy
t DS t RCD t RC
DQ Hi-Z
t DH
t WR t RP t RRD
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3
Activate Command Bank A Write with Auto Precharge Command Bank A
Activate Command Bank B Write with Auto Precharge Command Bank B
Activate Command Bank A
Write Command Bank A
Precharge Command Bank A
Activate Command Bank A
Activate Command Bank B
SPT03910
Semiconductor Group
12
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
9.2. AC Parameters for a Read Timing
y
Burst Length = 2, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
t CH t CL
CKE
t CK2 t CKH t CS
Begin Auto Precharge Bank A Begin Auto Precharge Bank B
t CKS t CH
CS RAS CAS WE BS
t AH
AP RAx RBx RAy
t AS
Addr. RAx CAx RBx RBx RAy
t RRD t RAS
DQM
t RC t AC2 t LZ t RCD t OH t AC2 t HZ
Ax1 Bx0 Bx1
t HZ
t RP
DQ
Hi-Z
Ax0
Activate Command Bank A
Read with Auto Precharge Command Bank A
Activate Command Bank B
Read with Auto Precharge Command Bank B
Precharge Command Bank A
Activate Command Bank A
SPT03911
Semiconductor Group
13
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
10. Mode Register Set
CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
t RSC
CS RAS CAS WE BS0, BS1 A10, A11 Address Key A0-A9
Precharge Command All Banks Mode Register Set Command
Any Command
SPT03912
Semiconductor Group
14
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
11. Power on Sequence and Auto Refresh (CBR)
T0
~ ~
T1
T2
T3
T4
T5
T6
T7
T8
~ ~
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
~ ~
CKE
High Level is required
~ ~
~ ~
Minimum of 8 Refresh Cycles are required
~ ~
2 Clock min.
CS RAS CAS WE BS AP
~ ~ ~ ~ ~ ~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~
~ ~
~~ ~~
~~ ~~
~~ ~~
~~ ~~
Address Key
~ ~ ~~ ~~ ~~ ~~
Addr. DQM
t RP
DQ
~ ~ ~ ~
~ ~
t RC
Hi-Z
Precharge Command All Banks Inputs must be stable for 200 s 1st Auto Refresh Command
8th Auto Refresh Command
Mode Register Set Command
Any Command
SPT03913
Semiconductor Group
15
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
12. Clock Suspension (Using CKE) 12.1. Clock Suspension During Burst Read CAS Latency = 2
Burst Length = 4, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr. DQM
RAx RAx CAx
t CSL t CSL
DQ Hi-Z Ax0 Ax1 Ax2
t CSL
Ax3
t HZ
Read Activate Command Command Bank A Bank A
Clock Suspend 1 Cycle
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
SPT03914
Semiconductor Group
16
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
12.2. Clock Suspension During Burst Read CAS Latency = 3
Burst Length = 4, CAS Latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK3
CKE CS RAS CAS WE BS AP Addr. DQM
RAx RAx CAx
t CSL
t CSL
t CSL t HZ
DQ
Hi-Z
Ax0
Ax1
Ax2
Ax3
Activate Command Bank A
Read Command Bank A
Clock Suspend 1 Cycle
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
SPT03915
Semiconductor Group
17
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
12.3. Clock Suspension During Burst Write CAS Latency = 2
Burst Length = 4, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3
RAx RAx CAx
Activate Command Bank A
Clock Suspend 1 Cycle Write Command Bank A
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
SPT03916
Semiconductor Group
18
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
12.4. Clock Suspension During Burst Write CAS Latency = 3
Burst Length = 4, CAS Latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK3
CKE CS RAS CAS WE BA A8/AP Addr. DQMx DQ Hi-Z DAx0 DAx1 DAx2 DAx3
RAx RAx CAx
Activate Command Bank A
Clock Suspend 1 Cycle Write Command Bank A
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
SPT03917
Semiconductor Group
19
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
13. Power Down Mode and Clock Suspend
Burst Length = 4, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr. DQM
RAx RAx
t CKS
t CKS
CAx
t HZ
DQ Hi-Z Ax0 Ax1 Ax2 Ax3
Activate Command Bank A
Active Standby
Read Command Bank A
Clock Mask Start
Clock Mask End
Precharge Command Bank A
Precharge Standby
Any Command
Clock Suspend Mode Entry
Clock Suspend Mode Exit
Power Down Mode Entry
Power Down Mode Exit
SPT03918
Semiconductor Group
20
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
14. Self Refresh (Entry and Exit)
T0 CLK
T1
T2
T3
T4
T5
~ ~ ~ ~
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CKS
CS RAS CAS WE BS AP Addr.
~ ~
CKE
t CKS
~ ~
~~ ~~
~~ ~~
~~ ~~
~~ ~~
~~ ~~
~~ ~~
~ ~
t SREX
~ ~
DQM Hi-Z
t RC
DQ
All Banks must be idle
Self Refresh Entry
~ ~
Begin Self Refresh Exit Command Self Refresh Exit Command issued Self Refresh Exit
Any Command
SPT03919
Semiconductor Group
21
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
15. Auto Refresh (CBR)
Burst Length = 4, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx
DQM DQ Hi-Z
t RP
t RC (Minimum Interval)
t RC
Ax0 Ax1 Ax2 Ax3
Precharge Command All Banks
Auto Refresh Command
Auto Refresh Command
Activate Command Bank A
Read Command Bank A
SPT03920
Semiconductor Group
22
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
16. Random Column Read (Page within same Bank) 16.1. CAS Latency = 2
Burst Length = 4, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Az1 Az2 Az3
RAw RAw CAw CAx CAy RAz RAz CAz
Activate Command Bank A
Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
SPT03921
Semiconductor Group
23
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
16.2. CAS Latency = 3
Burst Length = 4, CAS Latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK3
CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
RAw RAw CAw CAx CAy RAz RAz CAz
Activate Command Bank A
Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A SPT03922
Semiconductor Group
24
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
17. Random Column Write (Page within same Bank) 17.1. CAS Latency = 2
Burst Length = 4, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 DBz3
RAw RAw CAw CAx CAy RAz RAz CAz
Activate Command Bank A
Write Command Bank B
Write Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Read Command Command Bank B Bank B
SPT03923
Semiconductor Group
25
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
17.2. CAS Latency = 3
Burst Length = 4, CAS Latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK3
CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1
RBz RBz CBz CBx CBy RBz RBz CBz
Activate Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Command Bank B
Write Command Bank B SPT03924
Semiconductor Group
26
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
18. Random Row Read (Interleaving Banks) with Precharge 18.1. CAS Latency = 2
Burst Length = 8, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr.
RBx RBx CBx RAx RAx CAx RBy RBy CBy
High
t RCD
DQM
t RP
t AC2
DQ Hi-Z Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 By1
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Precharge Activate Command Command Bank B Bank B Read Command Bank A
Read Command Bank B
SPT03925
Semiconductor Group
27
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
18.2. CAS Latency = 3
Burst Length = 8, CAS Latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK3
CKE CS RAS CAS WE BS AP Addr.
RBx RBx CBx RAx RAx CAx RBy RBy CBy
High
t RCD
DQM DQ Hi-Z
t AC3
t RP
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Read Command Bank A
Precharge Command Bank B
Activate Command Bank B
Read Command Bank B
Precharge Command Bank A
SPT03926
Semiconductor Group
28
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
19. Random Row Write (Interleaving Banks) with Precharge 19.1. CAS Latency = 2
Burst Length = 8, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx RBx RBx CBx RAy RAy CAy
High
t RCD
DQM DQ Hi-Z
t WR
t RP
t WR
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B Precharge Command Bank A
Activate Command Bank A
Precharge Command Bank B Write Command Bank A
SPT03927
Semiconductor Group
29
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
19.2. CAS Latency = 3
Burst Length = 8, CAS Latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK3
CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx RBx RBx CBx RAy RAy CAy
High
t RCD
DQM DQ Hi-Z
t WR
t RP
t WR
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B
Precharge Command Bank A
Activate Command Bank A
Write Command Bank A
Precharge Command Bank B
SPT03928
Semiconductor Group
30
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
20. Full Page Read Cycle 20.1. CAS Latency = 2
Burst Length = Full Page, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6
~ ~ ~ ~
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx RBx RBx
~ ~ ~~ ~~ ~ ~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~
High
~ ~
~ ~
RBy CBx RBy
t RP
~~ ~~
DQM DQ Hi-Z
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
~ ~
Ax Ax +1 Ax + 2 Ax - 2
Ax -1
Ax
Ax+1 Bx
Bx+1 Bx+2 Bx + 3 Bx+ 4 Bx+ 5 Bx + 6
Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval.
Burst Stop Precharge Command Command Bank B Activate Command Bank B
SPT03929
Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
Semiconductor Group
31
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
20.2. CAS Latency = 3
Burst Length = Full Page, CAS Latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
~ ~ ~ ~
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK3
CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx RBx RBx
~ ~ ~~ ~~ ~ ~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~
High
~ ~
~ ~
RBy CBx RBy
t RRD
~~ ~~
DQM DQ Hi-Z Ax
Activate Command Bank A Read Command Bank A
Activate Command Bank B
~ ~
Ax +1 Ax+ 2 Ax - 2
Ax -1
Ax
Ax +1 Bx
Bx +1 Bx +2 Bx + 3 Bx+ 4 Bx + 5
Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval.
Burst Stop Precharge Command Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
Activate Command Bank B
SPT03930
Semiconductor Group
32
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
21. Full Page Write Cycle 21.1. CAS Latency = 2
Burst Length = Full Page, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5
~ ~ ~ ~
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi-Z
RAx RAx CAx RBx RBx
~ ~ ~~ ~~ ~ ~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~
High
~ ~
~ ~
RBy CBx RBy
Activate Command Bank A
Write Command Bank A
~ ~
DAx DAx+1 DAx+2 DAx+3 DAx- 1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+ 3 DBx+ 4 DBx+ 5 DBx+6
~~ ~~
Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval.
Write Command Bank B
Data is ignored.
Burst Stop Command
Activate Command Bank B
Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
Precharge Command Bank B
SPT03931
Semiconductor Group
33
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
21.2. CAS Latency = 3
Burst Length = Full Page, CAS Latency = 3 T0 CLK T1 T2 T3 T4 T5 T6
~ ~ ~ ~
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK3
CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z
RAx RAx CAx RBx RBx
~ ~ ~~ ~~ ~ ~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~
High
~ ~
~ ~
RBy CBx RBy
~ ~
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+ 1 DBx DBx+1 DBx+ 2 DBx+ 3 DBx+ 4 DBx+5
~~ ~~
Activate Command Bank A Write Command Bank A
Activate Command Bank B
Write Command Bank B
Data is ignored.
Burst Stop Command Precharge Command Bank B
Activate Command Bank B
The burst counter wraps from the highest order page address back to zero during this time interval.
Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
SPT03932
Semiconductor Group
34
1998-10-01
HYB 39S64400/800/160AT(L) 64 MBit Synchronous DRAM
22. Precharge Termination of a Burst 22.1. CAS Latency = 2
Burst Length = 8 or Full Page, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx RAy RAy CAy RAz RAz CAz
High
t RP
DQM
t RP
t RP
DQ
Hi Z
DAx0 DAx1 DAx2 DAx3
Ay0 Ay1 Ay2
Az0 Az1 Az2
Activate Command Bank A
Write Command Bank A Precharge Termination of a Write Burst. Write Data is masked.
Precharge Command Bank A Activate Command Bank A
Read Command Bank A
Precharge Command Bank A Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Precharge Termination of a Read Burst.
SPT03933
Semiconductor Group
35
1998-10-01

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