 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1CY M72 64 This is an abbreviated datasheet. Contact a Cypress representative for complete specifications. CYM7232 CYM7264 DRAM Accelerator Module Features * 4-megabyte to 1-gigabyte control capability * 32- or 64-bit bus interface (M7232 only) * 32- or 64-bit EDC versions Functional Description The CYM7232 and the CYM7264 consist of a full-function DRAM controller and a pipelined/FIFO data multiplexer/demultiplexer with error correction for cache-based, uniprocessor, and multiprocessor systems memory control. The CYM7232 performs 32-bit Error Detection and Correction (EDC) while CYM7264 performs 64-bit EDC. They both connect to the system bus through a 64-bit-wide data bus, and a 36-bit wide address bus. The CYM7232 also supports 32-bit system buses. The bus transfer control signals support i486, Pentium, i860, 68040, 88110, SPARC MBus, MIPS R4000, or other interfaces. The controller module interfaces to the DRAM array through a 16-byte-wide data bus plus check bits, a 12-bit row/column address bus, four RAS outputs, four CAS outputs, and four read/write control lines. During write operations, data passes from the system bus through a FIFO array that acts as an incoming queue. Writes occur at the system bus speed until the FIFO is full (sixteen 64-bit words). The FIFO supports cache-line copy-back and fill operations, reducing system bus traffic to a minimum. The module supports posted writes, by suspending the actual write to DRAM until the cache-line read is completed during cache-line write-back. This speeds cache-line fill operations. The module pipelines a 16-byte-wide DRAM access into the data path for EDC, and multiplexes the data to the system bus during reads. This supports high-speed burst line fills with error corrected data. Reads and writes may be inhibited for multiprocessor support. Inhibited reads may be turned into reflective reads, and inhibited writes may be turned into reads-for-ownership. -- 1-bit correct; 2-bit detect * Multiplexed or non-multiplexed bus * i486, PentiumTM, i860, 68040, 88110, PowerPCTM, SPARC, and MIPS compatible * Synchronous bus interface * 25-, 33-, and 40-MHz versions * Error-logging facilities * Cache line fill burst support; posted writes * Cache line write-back support; write FIFO * High performance -- 25-ns writes -- 175-, 25-, 50-, 25-ns burst read/80-ns DRAMs * Automatic refresh with scrubbing * Multiprocessor compatible -- Inhibited reads and writes -- Reflective reads -- Reads for ownership * Bus parity generation and checking * Very small size Logic Block Diagram ADDRESS STATE MACHINE AND TIMING GENERATOR FREQUENCY MULTIPLIER CONTROL AND STATUS REGISTERS ADDRESS MUX ADDRESS CONTROL RAS/CAS CLOCK SYSTEM BUS DATA PATH CONTROL CHECK BIT GENERATOR FIFO CHECK BIT GENERATOR R/W DRAM ARRAY UPPER 64 DATA AND CHECK BITS 64 DATA BITS AND PARITY EDC MUX EDC 82C693-1 LOWER 64 DATA AND CHECK BITS Pentium is a trademark of Intel Corporation, PowerPC is a trademark of IBM. Document #: 38-00441 Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 April 1995 |
Price & Availability of CYM7232
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |