View MAX9381_275735.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-2397; Rev 0; 4/02
Lowest Power 3.0GHz ECL/PECL Differential Data and Clock D Flip-Flop
General Description
The MAX9381 differential data, differential clock D flipflop is pin compatible with the ON Semiconductor MC100EP52, with the added benefit of a wider supplyvoltage range from 2.25V to 5.5V and 25% lower supply current. Data enters the master part of the flip-flop when the clock is low and is transferred to the outputs upon a positive transition of the clock. Interchanging the clock inputs allows the part to be used as a negative edge-triggered device. The MAX9381 utilizes input clamping circuits that ensure the stability of the outputs when the inputs are left open or at VEE. The MAX9381 is offered in an 8-pin SO package and the smaller 8-pin MAX package. o 0.2psRMS Added Random Jitter o 328ps Typical Propagation Delay o PECL Operation from VCC = 2.25V to 5.5V with VEE = 0V o ECL Operation from VEE = -2.25V to -5.5V with VCC = 0V o Input Safety Clamps Ensure Output Stability when Inputs are Open or at VEE o 2kV ESD Protection (Human Body Model)
Features
o 3.0GHz Guaranteed Operating Clock Frequency
MAX9381
Applications
Precision Clock and Data Distribution Central Office DSLAM DLC Base Station ATE
PART MAX9381ESA MAX9381EUA*
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 8 SO 8 MAX
*Future product--contact factory for availability.
Functional Diagram
TOP VIEW
Pin Configuration
MAX9381
D 1 8 VCC D D Q CLK CLK 3 Q 6 Q 3 1 2 8 7 VCC Q Q VEE
D
2
75k
75k
D
Q
7
MAX9381
6 5 CLK 4
CLK
4 75k 75k
5
SO/MAX
VEE
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Lowest Power 3.0GHz ECL/PECL Differential Data and Clock D Flip-Flop MAX9381
ABSOLUTE MAXIMUM RATINGS
VCC - VEE ...............................................................-0.3V to +6.0V Input Voltage (D, D, CLK, CLK) .......(VEE - 0.3V) to (VCC + 0.3V) Differential Input Voltage ...............Smaller of |VCC - VEE| or 3.0V Output Current (Q, Q) Continuous .......................................................................50mA Surge..............................................................................100mA Junction-to-Ambient Thermal Resistance in Still Air 8-Pin MAX ..............................................................+221C/W 8-Pin SO ...................................................................+170C/W Maximum Continuous Power Dissipation 8-Pin MAX (derate 4.5mW/C above +70C) ..............362mW 8-Pin SO (derate 5.9mW/C above +70C)...................471mW Junction-to-Ambient Thermal Resistance with 500LFPM Airflow 8-Pin MAX ..............................................................+155C/W 8-Pin SO .....................................................................+99C/W Junction-to-Case Thermal Resistance 8-Pin MAX ................................................................+39C/W 8-Pin SO .....................................................................+40C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model ..........................................................2kV Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.25V to 5.5V (TA = +25C to +85C), VCC - VEE = 2.375V to 5.5V (TA = -40C to +25C), outputs terminated with 50 1% to VCC - 2.0V, unless otherwise noted. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER SYMBOL CONDITIONS -40C MIN VEE + 1.2 VEE VCC - VEE < 3.0V VID Figure 1 VCC - VEE 3.0V D, D, CLK, or CLK = VIHD or VILD 0.15 -10 0.15 TYP MAX MIN VEE + 1.2 VEE 0.15 0.15 -10 +25C TYP MAX MIN VEE + 1.2 VEE 0.15 0.15 -10 +85C TYP MAX UNITS
INPUTS (D, D, CLK, CLK) Differential Input High Voltage Differential Input Low Voltage VIHD VILD Figure 1 Figure 1 VCC VCC 0.15 VCC VEE 3.0 +200 VCC VCC 0.15 VCC VEE 3.0 +200 VCC VCC 0.15 VCC VEE 3.0 +200 A V V
Differential Input Voltage
V
Single-Ended Input Current OUTPUTS (Q, Q) Output High Voltage Output Low Voltage Differential Output Voltage POWER SUPPLY Power-Supply Current (Note 4)
IIH, IIL
VOH VOL VOD
Figure 1 Figure 1 VOH - VOL, Figure 1
VCC 1.145 VCC 1.945 550
VCC 0.895 VCC 1.695
VCC 1.145 VCC 1.945 550
VCC 0.895 VCC 1.695
VCC 1.145 VCC 1.945 550
VCC 0.895 VCC 1.695
V V mV
IEE
17
35
20
35
22
35
mA
2
_______________________________________________________________________________________
Lowest Power 3.0GHz ECL/PECL Differential Data and Clock D Flip-Flop
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.25V to 5.5V (TA = +25C to +85C), VCC - VEE = 2.375V to 5.5V (TA = -40C to +25C), outputs terminated with 50 1% to VCC - 2.0V, fCLK 3.0GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to smaller of |VCC - VEE| or 3V, unless otherwise noted. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 5)
PARAMETER Propagation Delay CLK, CLK to Q, Q Maximum Clock Frequency Setup Time Hold Time Added Random Jitter (Note 6) Differential Output Rise/Fall Time SYMBOL tPHL tPLH fCLKMAX tS tH tRJ tR/tF 20% to 80%, Figure 2 70 CONDITIONS Figure 2 VOD 300mV Figure 2 Figure 2 3.0 100 50 0.2 120 0.8 170 80 -40C MIN TYP MAX 370 3.0 100 50 0.2 120 0.8 180 90 MIN +25C TYP 328 MAX 405 3.0 100 50 0.2 120 0.8 200 MIN +85C TYP MAX 490 UNITS ps GHz ps ps ps (RMS) ps
MAX9381
Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters are production tested at +25C. DC limits are guaranteed by design and characterization over the full operating temperature range. Note 4: All pins floating except VCC and VEE. Note 5: Guaranteed by design and characterization, and are not production tested. Limits are set to 6 sigma. Note 6: Device jitter added to the input clock.
_______________________________________________________________________________________
3
Lowest Power 3.0GHz ECL/PECL Differential Data and Clock D Flip-Flop MAX9381
Typical Operating Characteristics
(VCC - VEE = 3.3V, outputs loaded with 50 1% to VCC - 2V, VIH = VCC - 1V, VIL = VCC - 1.5V, fCLK = 3GHz, fD = fCLK/2 input transition time = 125ps (20% to 80%), unless otherwise noted.)
SUPPLY CURRENT (IEE) vs. TEMPERATURE
MAX9381 toc01
OUTPUT AMPLITUDE (VOH - VOL) vs. CLK FREQUENCY
MAX9381 toc02
24 INPUTS AND OUTPUTS OPEN SUPPLY CURRENT (mA) 22
800
OUTPUT AMPLITUDE (mV) -40 -15 10 35 60 85
700
600
20
500
18
400
16 TEMPERATURE (C)
300 0 0.5 1.0 1.5 2.0 2.5 3.0 CLK FREQUENCY (GHz)
OUTPUT RISE/FALL TIME vs. TEMPERATURE
MAX9381 toc03
CLK-TO-Q PROPAGATION DELAY vs. TEMPERATURE
IN-TO-OUT PROPAGATION DELAY (ps)
MAX9381 toc04
125 fCLK = 1.5GHz OUTPUT RISE/FALL TIME (ps) 123
360
350
121
RISE TIME
340 tPHL 330 tPLH
119 FALL TIME 117
115 -40 -15 10 35 60 85 TEMPERATURE (C)
320 -40 -15 10 35 60 85 TEMPERATURE (C)
4
_______________________________________________________________________________________
Lowest Power 3.0GHz ECL/PECL Differential Data and Clock D Flip-Flop
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME D D CLK CLK VEE Q Q VCC FUNCTION Noninverting D Input to the Flip-Flop. Internally pulled down with a 75k resistor to VEE. Inverting D Input to the Flip-Flop. Internally pulled down with a 75k resistor to VEE. Noninverting Clock Input to the Flip-Flop. Internally pulled down with a 75k resistor to VEE. Inverting Clock Input to the Flip-Flop. Internally pulled down with a 75k resistor to VEE. Negative Supply Inverting Q Output from the Flip-Flop. Terminate with a 50 resistor to VCC - 2V or equivalent. Noninverting Q Output from the Flip-Flop. Terminate with a 50 resistor to VCC - 2V or equivalent. Positive Supply. Bypass from VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device.
MAX9381
Detailed Description
The MAX9381 D flip-flop transfers the logic level at the D input to the Q output on a rising edge transition of the clock, provided the minimum setup and hold times are met. By interchanging the CLK and CLK inputs, the flipflop functions as a falling-edge triggered flip-flop. The input signals (D, D and CLK, CLK) are differential and have a maximum differential input voltage of 3.0V or VCC - VEE, whichever is less. To ensure that the outputs remain stable when the inputs are left open, each of the inputs is driven low by a 75k bias resistor connected to VEE. If the D and D inputs are left open or at VEE, the output is guaranteed to be a differential low on the next low-to-high transition of the clock. If the CLK and CLK inputs are left open or at VEE, the outputs remain unchanged (Table 1). Terminate the outputs (Q, Q) through 50 to VCC - 2V or an equivalent Thevenin termination (see the Output Termination section).
Table 1. Truth Table*
D, D L H Open or VEE X CLK, CLK Open or VEE Q, Q L H L No change
*Where logic states are differential, is a low-to-high transition and X signifies a don't care state.
supply. With VCC connected to a positive supply and VEE connected to GND, the outputs are PECL. The outputs are ECL when VCC is connected to GND and VEE is connected to a negative supply.
Applications Information
T Flip-Flop
The MAX9381 can be configured as a T flip-flop by connecting Q to D and Q to D. This configuration provides an output at half the frequency of the clock. The maximum operating frequency is determined by the sum of the setup time, the propagation delay of the
ECL/PECL Operation
Output levels are referenced to VCC and are considered PECL or ECL, depending on the level of the VCC
VCC VID VID = 0 VILD (MAX) VIHD (MAX)
VCC
VOH VOH - VOL
VIHD (MIN) VID VEE VID = 0 VILD (MIN)
VOL
VEE
INPUT VOLTAGE DEFINITION
OUTPUT VOLTAGE DEFINITION
Figure 1. Input and Output Voltage Definitions _______________________________________________________________________________________ 5
Lowest Power 3.0GHz ECL/PECL Differential Data and Clock D Flip-Flop MAX9381
tS D tH
D CLK
CLK t PLH Q t PHL
Q
80% DIFFERENTIAL OUTPUT WAVEFORM
80%
Q-Q
0V (DIFFERENTIAL)
0V (DIFFERENTIAL)
20% tR tF
20%
Figure 2. CLK-to-Q Propagation Delay and Transition Timing Diagram device and any added delay by circuit board traces. The minimum supply voltage is 2.375V and is determined by input and output voltage range. Use multiple vias when connecting the bypass capacitors to ground. This reduces trace inductance, which lowers power-supply bounce when drawing high transient currents.
Output Termination
Terminate the outputs through 50 to VCC - 2V or use equivalent Thevenin terminations. Terminate each Q and Q outputs with identical termination on each for the lowest output distortion. When a single-ended signal is taken from the differential output, terminate both Q and Q. Ensure that output currents do not exceed the current limits as specified in the Absolute Maximum Ratings table. Under all operating conditions, the device's total thermal limits should be observed.
Circuit Board Traces
Circuit board trace layout is very important to maintain the signal integrity of high-speed differential signals. Maintaining integrity is accomplished in part by reducing signal reflections and skew, and increasing common-mode noise immunity. Signal reflections are caused by discontinuities in the 50 characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, not using sharp corners, or using vias. Maintaining distance between the traces also increases common-mode noise immunity. Reducing signal skew is accomplished by matching the electrical length of the differential traces.
Power-Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1F and 0.01F capacitors. Place the capacitors as close to the device as possible with the 0.01F capacitor closest to the device pins.
Chip Information
TRANSISTOR COUNT: 375 PROCESS: Bipolar
6
_______________________________________________________________________________________
Lowest Power 3.0GHz ECL/PECL Differential Data and Clock D Flip-Flop
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
9LUCSP, 3x3.EPS
MAX9381
8
4X S
8
INCHES DIM A A1 A2 b c D e E H MIN 0.002 0.030 MAX 0.043 0.006 0.037
MILLIMETERS MAX MIN 0.05 0.75 1.10 0.15 0.95
y 0.500.1 0.60.1
E
H
1
0.60.1
1
D
L
S
BOTTOM VIEW
0.014 0.010 0.007 0.005 0.120 0.116 0.0256 BSC 0.120 0.116 0.198 0.188 0.026 0.016 6 0 0.0207 BSC
0.25 0.36 0.13 0.18 2.95 3.05 0.65 BSC 2.95 3.05 4.78 5.03 0.41 0.66 0 6 0.5250 BSC
TOP VIEW
A2
A1
A
e
c b L
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0036
J
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
8LUMAXD.EPS

▲Up To Search▲

Price & Availability of MAX9381

	To Download MAX9381 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .