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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
D D D
This data sheet is applicable to all TMS45160/Ps symbolized with Revision "D" and subsequent revisions as described on page 21. Organization . . . 262144 x 16 5-V Supply (10% Tolerance) Performance Ranges:
ACCESS ACCESS ACCESS READ OR TIME TIME TIME WRITE tRAC tCAC tAA CYCLE MAX MAX MAX MIN 60 ns 15 ns 30 ns 110 ns 70 ns 20 ns 35 ns 130 ns 80 ns 20 ns 40 ns 150 ns
DZ PACKAGE ( TOP VIEW )
DGE PACKAGE ( TOP VIEW )
D D D D D D D D D D
'45160/P-60 '45160/P-70 '45160/P-80
Enhanced-Page-Mode Operation With xCAS-Before-RAS (xCBR) Refresh Long Refresh Period 512-Cycle Refresh in 8 ms (Max) 64 ms Max for Low Power With Self-Refresh Version ( TMS45160P) 3-State Unlatched Output Low Power Dissipation Texas Instruments EPICTM CMOS Process All Inputs, Outputs, and Clocks Are TTL Compatible High-Reliability, 40-Lead, 400-Mil-Wide Plastic Surface-Mount (SOJ) Package and 40/44-Lead Thin Small-Outline Package ( TSOP) Operating Free-Air Temperature Range 0C to 70C Low Power With Self-Refresh Version Upper and Lower Byte Control During Read and Write Operations
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC NC W RAS NC A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7
1 2 3 4 5 6 7 8 9 10
44 43 42 41 40 39 38 37 36 35
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8
NC NC W RAS NC A0 A1 A2 A3 VCC
13 14 15 16 17 18 19 20 21 22
32 31 30 29 28 27 26 25 24 23
NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
PIN NOMENCLATURE A0 - A8 DQ0 - DQ15 LCAS NC OE RAS UCAS VCC VSS W Address Inputs Data In / Data Out Lower Column-Address Strobe No Internal Connection Output Enable Row-Address Strobe Upper Column-Address Strobe 5-V Supply Ground Write Enable
description
The TMS45160 series are high-speed, 4 194 304-bit dynamic random-access memories organized as 262 144 words of 16 bits each. The TMS45160P series are high-speed, low-power, self-refresh 4 194 304-bit dynamic random-access memories organized as 262 144 words of 16 bits each. They employ state-of-the-art EPICTM ( Enhanced Performance Implanted CMOS) technology for high performance, reliability, and low power at low cost. These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. Maximum power dissipation is as low as 770 mW operating and 11 mW standby on 80-ns devices. All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility. The TMS45160 and TMS45160P are each offered in a 40-lead plastic surface-mount SOJ package ( DZ suffix) and a 40/44-lead plastic surface-mount small-outline ( TSOP) package ( DGE suffix). These packages are characterized for operation from 0C to 70C.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1995, Texas Instruments Incorporated
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
operation
dual CAS Two CAS pins ( LCAS- UCAS) are provided to give independent control of the 16 data I/O pins ( DQ0- DQ15) with LCAS corresponding to DQ0 - DQ7 and UCAS corresponding to DQ8 - DQ15. For read or write cycles, the column address is latched on the first xCAS falling edge. Each xCAS going low enables its corresponding DQx pins with data associated with the column address latched on the first falling xCAS edge. All address setup and hold parameters are referenced to the first falling xCAS edge.The delay time from xCAS low to valid data out ( see parameter tCAC ) is measured from each individual xCAS to its corresponding DQx pins. In order to latch in a new column address, both xCAS pins must be brought high. The column precharge time ( see parameter tCP ) is measured from the last xCAS rising edge to the first falling xCAS edge of the new cycle. Keeping a column address valid while toggling xCAS requires a minimum setup time, tCLCH. During tCLCH, at least one xCAS must be brought low before the other xCAS is taken high. For early-write cycles, the data is latched on the first falling edge of xCAS. Only the DQs that have the corresponding xCAS low are written into. Each xCAS must meet tCAS minimum in order to ensure writing into the storage cell. In order to latch a new address and new data, both xCAS pins must go high and meet tCP . enhanced page mode Page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS low time and the xCAS page-mode cycle time used. With minimum xCAS page cycle time, all 512 columns specified by column addresses A0 through A8 can be accessed without intervening RAS cycles. Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The first falling edge of xCAS latches the column addresses. This feature allows the devices to operate at a higher data bandwidth than conventional page-mode parts because data retrieval begins as soon as column address is valid rather than when xCAS transitions low. This performance improvement is referred to as enhanced page mode. A valid column address can be presented immediately after tRAH ( row-address hold time ) has been satisfied, usually well in advance of the falling edge of xCAS. In this case, data is obtained after tCAC max ( access time from xCAS low) if tAA max ( access time from column address) has been satisfied. In the event that column addresses for the next page cycle are valid at the time xCAS goes high, minimum access time for the next cycle is determined by tCPA ( access time from rising edge of the last xCAS). address ( A0- A8) Eighteen address bits are required to decode 1 of 262 144 storage cell locations. Nine row-address bits are set up on A0 through A8 and latched onto the chip by RAS. Then, nine column-address bits are set up on A0 through A8 and latched onto the chip by the first xCAS. All addresses must be stable on or before the falling edge of RAS and xCAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. xCAS is used as a chip select, activating its corresponding output buffer and latching the address bits into the column-address buffers. write enable ( W) The read or write mode is selected through W. A logic high on W selects the read mode and a logic low selects the write mode. W can be driven from the standard TTL circuits without a pullup resistor. The data input lines are disabled when the read mode is selected. When W goes low prior to xCAS ( early write ) , data out remains in the high-impedance state for the entire cycle, permitting a write operation with OE grounded.
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
data in (DQ0 - DQ15) Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS and the data is strobed in by the first occurring xCAS with setup and hold times referenced to data in. In a delayed-write or read-modify-write cycle, xCAS is already low and the data is strobed in by W with setup and hold times referenced to data in. In a delayed-write or read-modify-write cycle, OE must be high to bring the output buffers to the high-impedance state prior to impressing data on the I/O lines. data out (DQ0 - DQ15) The 3-state output buffer provides direct TTL compatibility ( no pullup resistor required ) with a fanout of two Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance ( floating) state until xCAS and OE are brought low. In a read cycle, the output becomes valid after the access-time interval tCAC ( which begins with the negative transition of xCAS ) as long as tRAC and tAA are satisfied. output enable (OE) OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance state. It is necessary for both RAS and xCAS to be brought low for the output buffers to go into the low-impedance state. They remain in the low-impedance state until either OE or xCAS is brought high. RAS-only refresh A refresh operation must be performed at least once every 8 ms ( 64 ms for TMS45160P ) to retain data. This can be achieved by strobing each of the 512 rows ( A0- A8). A normal read or write cycle refreshes all bits in each row that is selected. A RAS-only operation can be used by holding all xCAS at the high ( inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. hidden refresh Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding xCAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. The external address is ignored and the refresh address is generated internally. xCAS-before-RAS (xCBR) refresh xCBR refresh is utilized by bringing at least one xCAS low earlier than RAS ( see parameter tCSR ) and holding it low after RAS falls ( see parameter tCHR ) . For successive xCBR refresh cycles, xCAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated internally. A low-power battery-backup refresh mode that requires less than 500-A refresh current is available on the TMS45160P. Data integrity is maintained using xCBR refresh with a period of 125 s holding RAS low for less than 1 s. To minimize current consumption, all input levels must be at CMOS levels ( VIL 0.2 V, VIH VCC - 0.2 V ). self refresh ( TMS45160P) The self-refresh mode is entered by dropping xCAS low prior to RAS going low. Then xCAS and RAS are both held low for a minimum of 100 s. The chip is refreshed internally by an on-board oscillator. No external address is required since the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS and xCAS are brought high to satisfy tCHS. Upon exiting the self-refresh mode, a burst refresh (refresh a full set of row addresses) must be executed before continuing with normal operation. This ensures that the DRAM is fully refreshed.
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
power up To achieve proper device operation, an initial pause of 200 s followed by a minimum of eight RAS cycles is required after power up to the full VCC level.These eight initialization cycles must include at least one refresh (RAS-only or xCBR) cycle.
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
logic symbol
RAM 256K x 16 A0 A1 A2 A3 A4 A5 A6 A7 A8 16 17 18 19 22 23 24 25 26 20D9/21D0
A
0 262 143
20D17/21D8 C20[ROW] G23/[REFRESH ROW] 24[PWR DWN] C21 G24 & 31 C21 G34 & 31 Z31 24,25EN27 23C32 23C22
RAS
14
LCAS
29
UCAS
28
W 13 27 OE 2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 3 4 5 7 8 9 10 31 32 33 34 36 37 38 39
23,21D G25 A,22D 26,27
34,25EN37
A, Z26
A,32D 36,37
A, Z36
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. The pin numbers shown are for the DZ package.
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
functional block diagram
RAS UCAS LCAS W OE
Timing and Control
A0 A1 ColumnAddress Buffers A8
9
Column Decode Sense Amplifiers 128K Array 128K Array R o w D e c o d e 128K Array 9 128K Array 128K Array 128K Array 16 16 16 I/O Buffers DataIn Reg. DataIn Reg. 16 16
16 RowAddress Buffers 9
16
DQ0 - DQ15
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VSS VIH VIL Supply voltage Supply voltage High-level input voltage Low-level input voltage (see Note 2) 2.4 -1 4.5 NOM 5 0 6.5 0.8 MAX 5.5 UNIT V V V V
TA Operating free-air temperature 0 70 C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current TEST CONDITIONS '45160 - 60 '45160P - 60 MIN VOH VOL II IO ICC1 IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VCC VCC = 5.5 V, CAS high VCC = 5.5 V, VO = 0 V to VCC, 2.4 0.4 10 10 180 MAX '45160 - 70 '45160P - 70 MIN 2.4 0.4 10 10 160 MAX '45160 - 80 '45160P - 80 MIN 2.4 0.4 10 10 140 MAX V V A A mA UNIT
Minimum cycle
VIH = 2.4 V (TTL), After 1 memory cycle, RAS and xCAS high ICC2 Standby current VIH = VCC - 0.2 V (CMOS), After 1 memory cycle, cycle RAS and xCAS high '45160 '45160P
2 1 350
2 1 350
2 1 350
mA mA A
ICC3
Average refresh current (RAS-only refresh or CBR) Average page current Battery-backup operating current (equivalent refresh time is 64 ms); CBR only Self-refresh current
VCC = 5.5 V, Minimum cycle, RAS cycling, (RAS only), xCAS high (CBR only), RAS low after xCAS low VCC = 5.5 V, RAS low, tPC = MIN, xCAS cycling
180
160
140
mA
ICC4
160
140
120
mA
ICC5
tRC = 125 s, tRAS 1 s, VCC - 0.2 V VIH 6.5 V, 0 V VIL 0.2 V, W and OE = VIH, Address and data stable xCAS < 0.2 V, RAS < 0.2 V, tRAS and tCAS > 1000 ms
500
500
500
A
ICC6
400
400
400
A
Measured with outputs open Measured with a maximum of one address change while RAS = VIL Measured with a maximum of one address change while xCAS = VIH For TMS45160P only
capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz# (see Note 3)
PARAMETER Ci(A) Ci(OE) Ci(RC) Ci(W) Input capacitance, A0 - A8 Input capacitance, OE Input capacitance, xCAS and RAS Input capacitance, W MIN MAX 5 7 7 7 7 UNIT pF pF pF pF pF
Co Output capacitance # Capacitance measurements are made on a sample basis only. NOTE 3: VCC = 5 V 0.5 V, and the bias on pins under test is 0 V.
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER tCAC tAA tRAC tOEA tCPA tCLZ tOFF tOEZ Access time from xCAS low Access time from column address Access time from RAS low Access time from OE low Access time from column precharge Delay time, xCAS low to output in low impedance Output disable time after xCAS high (see Note 4) Output disable time after OE high (see Note 4) 0 0 0 15 15 '45160 - 60 '45160P - 60 MIN MAX 15 30 60 15 35 0 0 0 20 20 '45160 - 70 '45160P - 70 MIN MAX 20 35 70 20 40 0 0 0 20 20 '45160 - 80 '45160P - 80 MIN MAX 20 40 80 20 45 ns ns ns ns ns ns ns ns UNIT
NOTE 4: tOFF and tOEZ are specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 5)
'45160 - 60 '45160P - 60 MIN tRC tWC tRWC tPC tPRWC tRASP tRAS tCAS tCP tRP tWP tASC tASR tDS tRCS tCWL tRWL tWCS Cycle time, read (see Note 6) Cycle time, write Cycle time, read-write/read-modify-write Cycle time, page-mode read or write (see Note 7) Cycle time, page-mode read-modify-write Pulse duration, RAS low, page mode (see Note 8) Pulse duration, RAS low, nonpage mode (see Note 8) Pulse duration, xCAS low (see Note 9) Pulse duration, xCAS high Pulse duration, RAS high (precharge) Pulse duration, write Setup time, column address before xCAS low Setup time, row address before RAS low Setup time, data before W low (see Note 10) Setup time, read before xCAS low Setup time, W low before xCAS high Setup time, W low before RAS high Setup time, W low before xCAS low (see Note 11) Timing measurements are referenced to VIL max and VIH min. All cycle times assume tT = 5 ns. To assure tPC min, tASC should be tCP . In a read-modify-write cycle, tRWD and tRWL must be observed. In a read-modify-write cycle, tCWD and tCWL must be observed. Referenced to the later of xCAS or W in write operations Early-write operation only 110 110 155 40 85 60 100 000 60 15 10 40 15 0 0 0 0 15 15 0 10 000 10 000 MAX '45160 - 70 '45160P - 70 MIN 130 130 185 45 90 70 100 000 70 20 10 50 15 0 0 0 0 20 20 0 10 000 10 000 MAX '45160 - 80 '45160P - 80 MIN 150 150 205 50 105 80 100 000 80 20 10 60 15 0 0 0 0 20 20 0 10 000 10 000 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
NOTES: 5. 6. 7. 8. 9. 10. 11.
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued) (see Note 5)
'45160 - 60 '45160P - 60 MIN tCAH tDHR tDH tAR tRAH tRCH tRRH tWCH tWCR tCLCH tAWD tCHR tCRP tCSH tCSR tCWD tOEH tOED tROH tRAD tRAL tCAL tRCD tRPC tRSH tRWD tCPR tRPS tRASS tCHS tREF Hold time, column address after xCAS low (see Note 10) Hold time, data after RAS low (see Note 12) Hold time, data after xCAS low (see Note 10) Hold time, column address after RAS low (see Note 12) Hold time, row address after RAS low Hold time, read after xCAS high (see Note 13) Hold time, read after RAS high (see Note 13) Hold time, write after xCAS low (see Note 13) Hold time, write after RAS low (see Note 14) Hold time, xCAS low to xCAS high Delay time, column address to W low (see Note 15) Delay time, RAS low to xCAS high (see Note 11) Delay time, xCAS high to RAS low Delay time, RAS low to xCAS high Delay time, xCAS low to RAS low (see Note 11) Delay time, xCAS low to W low (see Note 15) Hold time, OE command Delay time, OE high before data at DQ Delay time, OE low to RAS high Delay time, RAS low to column address (see Note 16) Delay time, column address to RAS high Delay time, column address to xCAS high Delay time, RAS low to xCAS low (see Note 16) Delay time, RAS high to xCAS low (see Note 11) Delay time, xCAS low to RAS high Delay time, RAS low to W low (see Note 15) Pulse duration, xCAS precharge before self refresh Pulse duration, RAS precharge after self refresh Pulse duration, self refresh entry from RAS low Hold time, xCAS low after RAS high (for self refresh) Refresh time interval '45160 '45160P 10 30 10 30 10 0 0 10 30 5 55 15 0 60 10 40 15 15 10 15 30 30 20 0 15 85 0 110 100 - 50 8 64 2 45 30 MAX '45160 - 70 '45160P - 70 MIN 15 35 15 35 10 0 0 15 35 5 65 15 0 70 10 50 20 20 10 15 35 35 20 0 20 100 0 130 100 - 50 8 64 50 2 50 35 MAX '45160 - 80 '45160P - 80 MIN 15 35 15 35 10 0 0 15 35 5 70 20 0 80 10 50 20 20 10 15 40 40 20 0 20 110 0 150 100 - 50 8 64 50 60 40 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ms ns UNIT
tT Transition time 2 50 NOTES: 5. Timing measurements are referenced to VIL max and VIH min. 10. Referenced in the later of xCAS or W in write operations. 11. Early-write operation only 12. The minimum value is measured when tRCD is set to tRCD min as a reference. 13. Either tRRH or tRCH must be satisfied for a read cycle. 14. xCBR refresh only 15. Read-modify-write operation only 16. Maximum value specified only to assure access time
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
1.31 V VCC = 5 V
RL = 218 Output Under Test Output Under Test CL = 100 pF (see Note A)
R1 = 828
R2 = 295
CL = 100 pF (see Note A)
(a) LOAD CIRCUIT NOTE A: CL includes probe and fixture capacitance.
(b) ALTERNATE LOAD CIRCUIT
Figure 1. Load Circuits for Timing Parameters
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRC RAS tT UCAS tRCD tCAS tCLCH (see Note A) LCAS tCSH tRAD tRAH tASC tASR A0 - A8 Row tAR tCAH tRCS Don't Care tCAC tAA tCLZ DQ0 - DQ15 tRAC tOEA tROH OE NOTES: A. B. C. D. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. tCAC is measured from xCAS to its corresponding DQx. xCAS order is arbitrary. See Note B Valid Data Out tOEZ tOFF tRCH Don't Care Column tCAL tRAL Don't Care tRRH tRSH tCRP tRAS tRP
tCP
W
Figure 2. Read-Cycle Timing
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tWC RAS tT UCAS tRCD tCAS tRAS tRP
tCLCH (see Note A) LCAS tASR tCSH tRAH tASC tCAL A0 - A8 Row tAR tCAH tRAD tCWL tRWL W Don't Care tWCR tWP tDH (see Note B) tDHR DQ0 - DQ15 Valid Data In tDS tOED OE tOEH Column tRAL Don't Care tRSH tCRP
tCP
Don't Care
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. Later of xCAS or W in write operations C. xCAS order is arbitrary.
Figure 3. Write-Cycle Timing
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tWC RAS tT tRCD tCSH UCAS tCAS tRSH tCLCH (see Note A) LCAS tASR tRAH tASC tCAL tRAL A0 - A8 Row Address Column Address tCAH tAR tWCS W Don't Care tCWL tWCR DQ0 - DQ15 Don't Care tRWL tWP Don't Care tDH tDHR tDS OE Don't Care tWCH Don't Care Don't Care tRAD tCP tCRP tRAS tRP
Valid Data In
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. xCAS order is arbitrary.
Figure 4. Early-Write-Cycle Timing
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRWC RAS tT UCAS tRCD tCAS tCSH tAR tCLCH (see Note A) tRSH LCAS tRAD tRAH tASC tASR A0 - A8 Row Column tCAH tAWD tRCS W Don't Care tCWD Don't Care tCWL tRWL tWP Don't Care tRAS tRP
tCRP tCP
tRWD See Note B DQ8 - DQ15 Don't Care tAA tCAC tRAC tOEA OE tOED See Note B DQ0 - DQ7 Don't Care Valid Out Valid In Don't Care tOEZ tDS Valid Out Don't Care
tDH
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. C. xCAS order is arbitrary.
Figure 5. Read-Modify-Write-Cycle Timing
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRP RAS tRCD UCAS tRSH tPC tCSH LCAS tASR tAR tRAH tASC tCAH A0 - A8 Row tRAD W Don't Care tRCS tCLZ DQ8 - DQ15 Valid Out See Note B tCPA tAA Valid Out tCAC (see Note A) tAA tRAC tOFF tOEZ Column Don't Care Column tCAL tRAL Don't Care tRCH tRRH Don't Care tCAS tCP tRASP tCRP
DQ0 - DQ7
Valid Out tOEA
OE NOTES: A. tCAC is measured from xCAS to its corresponding DQx. B. Access time is tCPA or tAA dependent. C. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing specifications are not violated. D. xCAS order is arbitrary. E. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRP RAS tRASP tRSH UCAS tCLCH (see Note A) tCSH LCAS tASR tAR tASC tRAH A0 - A8 Row tRAD Column tCWL tWP tWCR tDS (see Note B) W Don't Care tDHR DQ8 - DQ15 Valid In tDH DQ0 - DQ7 Valid In tOED OE NOTES: A. B. C. D. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met. Referenced to xCAS or W, whichever occurs last xCAS order is arbitrary. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read and read-modify-write timing specifications are not violated. See Note B Valid In Valid In tWCH Don't Care Don't Care Don't Care Column tCWL tRWL tCAS tCAH tCAL tRAL Don't Care tCP tCRP
tRCD
tPC
Figure 7. Enhanced-Page-Mode Write-Cycle Timing
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRASP RAS tRCD UCAS tCSH tPRWC tCAS tCP tCLCH (see Note A) LCAS tASR tASC tRAD A0 - A8 tRAH Row Column tCWD tAWD tRWD W tRCS tAA tRAC tCLZ DQ0 - DQ15 Valid Out tOEA tOEZ OE NOTES: A. B. C. D. E. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met. tCAC is measured from xCAS to its corresponding DQx. Output can go from the high-impedance state to an invalid data state prior to the specified access time. xCAS order is arbitrary. A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write cycle timing specifications are not violated. Valid In tOEH tOED See Note C tCAC (see Note B) tDS tWP tCAH Column tCWL tRWL tRSH tCRP tRP
tCPA
tOEH
Valid Out Valid In
Figure 8. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRC tRAS RAS tCRP tT xCAS Don't Care tASR A0 - A8 Don't Care Row tRPC tRP
See Note A
tRAH Don't Care Row
W
Don't Care
DQ0 - DQ15
Hi-Z
OE NOTE A: All xCAS must be high.
Don't Care
Figure 9. RAS-Only Refresh Timing
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle Memory Cycle tRAS RAS tRP tCAS xCAS tASR tRAH tCHR tRAS tRP Refresh Cycle
tASC tCAH Row Col tRRH Don't Care tCAC tAA Valid Data tOEA tOEZ Don't Care
A0 - A8
tRCS W
tRAC DQ0 - DQ15
tOFF
OE
Figure 10. Hidden-Refresh-Cycle Timing
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRC tRP tRAS
RAS tCSR tT
tRPC xCAS
tCHR
W
Don't Care
A0 - A8
Don't Care
OE
Don't Care
DQ0 - DQ15 NOTE A: Any xCAS can be used.
Hi-Z
Figure 11. Automatic-CBR- Refresh-Cycle Timing
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRASS RAS tCSR tRPC xCAS tCPR Don't Care tRPS tCHS
A0 - A8
W
Don't Care
OE
Don't Care
DQ0 - DQ15 NOTE A: Any xCAS can be used.
Hi-Z
Figure 12. Self-Refresh-Cycle Timing
device symbolization (TMS45160 illustrated)
TI -SS Speed ( - 60, - 70, - 80) TMS45160 DZ W B Y M LLL P Asembly Site Code Lot Traceability Code Month Code Year Code Die Revision Code Wafer Fab Code Low-Power / Self-Refresh Designator (Blank or P) Package Code
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443
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TMS45160, TMS45160P 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D - AUGUST 1992 - REVISED JUNE 1995
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443
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