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(R)
PG A20 6
PGA206 PGA207
PG
A2
07
High-Speed Programmable Gain INSTRUMENTATION AMPLIFIER
FEATURES
q DIGITALLY PROGRAMMABLE GAINS: PGA206: G=1, 2, 4, 8V/V PGA207: G=1, 2, 5, 10V/V q TRUE INSTRUMENTATION AMP INPUT q FAST SETTLING: 3.5s to 0.01% q FET INPUT: IB = 100pA max q INPUT PROTECTION: 40V q LOW OFFSET VOLTAGE: 1.5mV max q 16-PIN DIP, SOL-16 SOIC PACKAGES
DESCRIPTION
The PGA206 and PGA207 are digitally programmable gain instrumentation amplifiers that are ideally suited for data acquisition systems. The PGA206 and PGA207's fast settling time allows multiplexed input channels for excellent system efficiency. FET inputs eliminate IB errors due to analog multiplexer series resistance. Gains are selected by two CMOS/TTL-compatible address lines. Analog inputs are internally protected for overloads up to 40V, even with the power supplies off. The PGA206 and PGA207 are laser-trimmed for low offset voltage and low drift. The PGA206 and PGA207 are available in 16-pin plastic DIP and SOL-16 surface-mount packages. Both are specified for -40C to +85C operation.
APPLICATIONS
q MULTIPLE-CHANNEL DATA ACQUISITION q MEDICAL, PHYSIOLOGICAL AMPLIFIER q PC-CONTROLLED ANALOG INPUT BOARDS
VO1 1 - VIN 4 Over-Voltage Protection
V+ 13 PGA206 PGA207
Feedback 12
A1 10k 10k
A1 A0 Digital Ground + VIN
16 15 14 Digitally Selected Feedback Network A3 11 VO
5
Over-Voltage Protection 6
A2 10k 7 VOS Adj 9 VO2 8 V- 10k
10
Ref
International Airport Industrial Park * Mailing Address: PO Box 11400, Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 * Tel: (520) 746-1111 * Twx: 910-952-1111 Internet: http://www.burr-brown.com/ * FAXLine: (800) 548-6133 (US/Canada Only) * Cable: BBRCORP * Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132
(c)
1994 Burr-Brown Corporation
PDS-1241B
Printed in U.S.A. May, 1995
SPECIFICATIONS
At TA = +25C, VS = 15V, RL = 2k unless otherwise noted. PGA206P, U PGA207P, U PARAMETER CONDITIONS MIN TYP MAX MIN INPUT Offset Voltage, RTI All Gains Initial TA = +25C vs Temperature TA = TMIN to TMAX, G = 8, 10 vs Power Supply VS = 4.5V to 18V Long-Term Stability Impedance, Differential Common-Mode Common-Mode Voltage Range(1) VO = 0V (|VS|-4) Safe Input Voltage Common-Mode Rejection VCM = 11V, RS = 1k G=1 80 G=2 85 G = 4 or 5 90 G = 8 or 10 95 INPUT BIAS CURRENT vs Temperature Offset Current vs Temperature NOISE VOLTAGE, RTI f = 10Hz f = 100Hz f = 1kHz fB = 0.1Hz to 10Hz Noise Current f = 1kHz GAIN Gain Error Gain vs Temperature(2) Nonlinearity OUTPUT Voltage, Positive Negative Load Capacitance Stability Short-Circuit Current FREQUENCY RESPONSE Bandwidth, -3dB G=1 G=2 G = 4, 5 G = 8, 10 VO = 10V, G = 1 to 10 20V Step, All Gains 20V Step, All Gains 50% Overdrive V- V- 1 VDG+2 500 4.5 VIN = 0V -40 -40 80 15 +12.4/-11.2 18 13.5 +85 +125 T V+ T T T T T VIN = 0 PGA206PA, UA PGA207PA, UA TYP MAX UNITS
0.5 2 5 4.5 1013 || 1 1012 || 4 (|VS| -2.5)
1.5 20
T 40 75 80 84 84 100 100
1 T 10 T T T T
2.5 40
T 86 90 94 94 T T T T T T T T T T T
mV V/C V/V V/mo || pF || pF V V dB dB dB dB pA pA
92 96 100 100
2 See Typical Curve 1 See Typical Curve 30 20 18 1 1.5
G = 8,10; RS = 0 nV/Hz nV/Hz nV/Hz Vp-p fA/Hz 0.1 T 0.005 % ppm/C % of FSR V V pF mA MHz MHz MHz kHz V/s s s s T T T T V V pA V ns V mA C C C/W
All Gains, VO = 11V
0.01 1 0.0003 (V+) -4 (V-) +4 (V+) -2.3 (V-) +1.5 1000 17 5 4 1.3 600 25 2 3.5 1.5
0.05 10 0.002 T T
T T T T T T T T T T T T T T T
Slew Rate Settling Time, 0.1% 0.01% Output Overload Recovery DIGITAL LOGIC INPUTS Digital Ground Voltage, VDG Digital Low Voltage Digital Input Current Digital High Voltage Gain Switching Time POWER SUPPLY Voltage Range Current TEMPERATURE RANGE Specification Operating Thermal Resistance, JA
(V+) -4 VDG + 0.8V
T T
T T T
T T
T Specification same as PGA206P or PGA207P. NOTES: (1) Input common-mode range varies with output voltage--see typical curves. (2) Guaranteed by wafer test.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
(R)
PGA206/207
2
PIN CONFIGURATION
Top View DIP SOL-16
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .................................................................................. 18V Analog Input Voltage Range ............................................................. 40V Logic Input Voltage Range .................................................................. VS Output Short-Circuit (to ground) .............................................. Continuous Operating Temperature ................................................. -40C to +125C Storage Temperature ..................................................... -40C to +125C Junction Temperature .................................................................... +150C Lead Temperature (soldering -10s) .............................................. +300C
VO1 NC NC
- VIN + VIN
1 2 3 4 5 6 7 8
16 A1 15 A0 14 Dig. Ground 13 V+ 12 Sense 11 VO 10 Ref 9 NC: No Internal Connection VO2
ORDERING INFORMATION
PRODUCT PGA206PA PGA206P PGA206UA PGA206U PGA207PA PGA207P PGA207UA PGA207U 1, 1, 1, 1, 1, 1, 1, 1, GAINS 2, 2, 2, 2, 2, 2, 2, 2, 4, 4, 4, 4, 5, 5, 5, 5, 8V/V 8V/V 8V/V 8V/V PACKAGE 16-Pin Plastic DIP 16-Pin Plastic DIP SOL-16 Surface-Mount SOL-16 Surface-Mount TEMPERATURE RANGE -40C -40C -40C -40C -40C -40C -40C -40C to to to to to to to to +85C +85C +85C +85C +85C +85C +85C +85C
VOS Adjust VOS Adjust V-
10V/V 16-Pin Plastic DIP 10V/V 16-Pin Plastic DIP 10V/V SOL-16 Surface-Mount 10V/V SOL-16 Surface-Mount
PACKAGE INFORMATION
PRODUCT PGA206PA PGA206P PGA206UA PGA206U PGA207PA PGA207P PGA207UA PGA207U PACKAGE 16-Pin Plastic 16-Pin Plastic SOL-16 Surface SOL-16 Surface 16-Pin Plastic 16-Pin Plastic SOL-16 Surface SOL-16 Surface DIP DIP Mount Mount DIP DIP Mount Mount PACKAGE DRAWING NUMBER(1) 180 180 211 211 180 180 211 211
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
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3
PGA206/207
TYPICAL PERFORMANCE CURVES
At TA = +25C, and VS = 15V, unless otherwise noted.
GAIN vs FREQUENCY 30 G=5 G=8
120
COMMON-MODE REJECTION vs FREQUENCY G = 10V/V 100
20
10
Common-Mode Rejection (dB)
G = 10
Gain (dB)
G=4 G=2
80 G = 1V/V
0 G=1 -10
60
40
-20 10k 100k Frequency (Hz) 1M 10M
20 1k 10k 100k Frequency (Hz) 1M 10M
POWER SUPPLY REJECTION vs FREQUENCY 120 G = 10V/V
Power Supply Rejection (dB)
15
INPUT COMMON-MODE VOLTAGE RANGE vs OUTPUT VOLTAGE
100 80 60 G = 1V/V 40 20 0 10 100 1k 10k 100k 1M 10M Frequency (Hz) +PSR -PSR
Common-Mode Voltage (V)
10 5
y A1 ed b Limit ut Swing tp + Ou
VD/2 VD/2
+ - + - + (Any Gain)
Limit + Ou ed by A tput Swin2 g
VO
0 -5 -10 A3 - Output Swing Limit Lim it - O ed by utpu A t Sw 2 ing -10
VCM
A3 + Output Swing Limit
-15 -15
by A 1 g in ited Lim put Sw Out -
-5 0 5 10 15 Output Voltage (V)
INPUT VOLTAGE NOISE vs FREQUENCY 1k
Voltage Noise Density nV/Hz
INPUT BIAS CURRENT vs TEMPERATURE 10n 1n
Input Bias Current (A)
100p 10p 1p 100f
IB
100 G=1
IOS
G = 10 10 1 10 100 1k 10k 100k Frequency (Hz) 10f -75 -50 -25 0 25 50 75 100 125 Temperature (C)
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PGA206/207
4
TYPICAL PERFORMANCE CURVES
At TA = +25C, and VS = 15V, unless otherwise noted.
(CONT)
INPUT OVER-VOLTAGE V/I CHARACTERISTIC 6
+15V
OFFSET VOLTAGE WARM-UP TIME 100
Offset Voltage Change (V)
4
I
Input Current (mA)
50
2 0 -2 -4 -6 -40 -30
V
-15V
0
Input current increases when the applied voltage exceeds the power supply voltage. This V/I characteristic does not vary with the voltage applied to the other input. -20 -10 0 10 20 30 40
-50
-100 0 1 2 3 4
Input Voltage (V)
Time After Turn-On (minutes)
OFFSET VOLTAGE TEMPERATURE DRIFT PRODUCTION DISTRIBUTION 35 30 25
Units (%)
Typical production distribution of packaged units. G = 8, 10V/V
QUIESCENT CURRENT vs POWER SUPPLY VOLTAGE 14
Quiescent Current (mA)
13 +IQ 12 -55C +25C +125C -55C +25C +125C -IQ
20 15 10 5 0 -10 -8 -6 -4 -2 0 2 4 6 8 10 Offset Voltage Drift (V/C)
11
10
9 0 5 10 Power Supply Voltage (V) 15 20
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
0.1
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY VO = 6Vrms
Maximum Output Voltage (Vp-p)
G = 10V/V 30 G = 2V/V
THD + N (%)
RL = 2k G=1 RL = 2k RL =
20 10 Maximum output voltage without slew-rate limiting or other large-signal distortion. Dotted region is beyond small signal bandwidth. 1 100k 1M
0.01 G = 10V/V
G = 1V/V
0.001
G = 1V/V 10 100 1k Frequency (Hz) 10k 100k
10M
Frequency (Hz)
(R)
5
PGA206/207
TYPICAL PERFORMANCE CURVES
At TA = +25C, and VS = 15V, unless otherwise noted.
(CONT)
SMALL SIGNAL RESPONSE G = 1, CL = 50pF
SMALL SIGNAL RESPONSE G = 10, CL = 50pF
100mV/div
100mV/div
1s/div
1s/div
LARGE SIGNAL RESPONSE G = 1, CL = 50pF
LARGE SIGNAL RESPONSE G = 10, CL = 50pF
5V/div
5V/div
1s/div
1s/div
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PGA206/207
6
+15V 1F VO1 1 - VIN 4 Over-Voltage Protection 13 PGA206 PGA207 A1 10k 16 15 14
+ - VO = G (VIN - VIN)
Sense 12
10k
Digitally Selected Feedback Network
A3
11
VO
+ VIN
5
Over-Voltage Protection 6
A2 10k 7 VOS Adj 9 VO2 8 1F VIN -15V + VIN - 10k
Ref 10
Digital Ground GAIN PGA206 PGA207 1 2 4 8 1 2 5 10 A 1 A0 0 0 1 1 0 1 0 1
Sometimes shown in simplified form:
PGA206
VO
A1 A0
FIGURE 1. Basic Connections.
APPLICATIONS INFORMATION
Figure 1 shows the circuit diagram for basic operation of the PGA206 or PGA207. Applications with noisy or high impedance power supplies may require decoupling capacitors close to the device pins as shown. The output is referred to the output reference (Ref) terminal which is normally grounded. This must be a low-impedance connection to assure good common-mode rejection. A resistance of 2 in series with the Ref pin will cause a typical device to degrade to approximately 80dB CMR (G = 1). The output sense connection (pin 12) must be connected to the output terminal (pin 11) for proper operation. This connection can be made at the load for best accuracy. DIGITAL INPUTS The digital inputs A0 and A1 select the gain according to the logic table in Figure 1. Logic "1" is defined as a voltage greater than 2V above digital ground potential (pin 14). Digital ground can be connected to any potential ranging from the V- power supply to 4V less than V+. Digital ground is usually equal to analog ground potential and the two grounds are connected at the power supply. The digital inputs interface directly to CMOS and TTL logic. A nearly constant current of approximately 1.2mA flows in the digital ground pin. It is good practice to return digital ground through a separate connection path so that analog ground is not affected by the digital ground current. The digital inputs, A0 and A1, are not latched. A change in logic input immediately selects a new gain. Switching time of the logic is approximately 500ns. The time to respond to gain change is equal to switching time, plus the time it takes the amplifier to settle to a new output voltage in the newly selected gain (see settling time specifications). Many applications use an external logic latch to acquire gain control data from a high speed digital bus. Using an external latch isolates the high speed digital bus from sensitive analog circuitry. Locate the digital latch as far as practical from analog circuitry to avoid coupling digital noise into analog input circuitry. OFFSET VOLTAGE ADJUSTMENT The PGA206 and PGA207 are laser trimmed for very low offset voltage and drift. Many applications require no external offset adjustment. Multiplexed data acquisition systems generally correct offset by grounding the inputs of one channel to measure offset voltage. Stored offset values for each gain are then subtracted from subsequent readings of other channels. Figure 2 shows optional offset voltage trim circuits. Offset voltage changes with the selected gain. To adjust for low offset voltage in all gains, both input and output offsets must be trimmed.
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7
PGA206/207
VO1 1 - VIN 4 Over-Voltage Protection
V+ 13 PGA206 PGA207
Manual output offset trim circuit. V+ Resistors can be substituted for REF200. Power supply 100A rejection will be degraded. 1/2 REF200 100 R2 10k 100 VO 100A 1/2 REF200 V- Offset control with digital/analog converter
A1 10k 10k
12
A1 A0 Digital Ground V+
16 15 14 VREF 10k 6 7 9 VO2 8 V- 10k 10 OPA131 Digitally Selected Feedback Network A3 11
5
IN
Over-Voltage Protection
A2
Optional Input Offset Adjustment
D/A
R1 200k (100k to 500k)
V+
FIGURE 2. Optional Offset Voltage Trim Circuits. R1 adjusts the offset of the input amplifiers. Output stage offset is adjusted with R2. A buffer op amp is required in the output offset adjustment circuit, as shown, to assure that the Ref pin is driven by a low source impedance. To adjust for low offset voltage in all gains, first adjust the input stage offset in the highest gain. Then adjust the output stage offset (R2) in G = 1. Iterate the adjustments for lowest offset in all gains. Offset can also be adjusted under processor control with a D/A converter as shown in Figure 2. The D/A's output voltage can be reduced with a resistor divider for better adjustment resolution, but an op amp buffer following the divider is required to provide a low source impedance to the ref terminal. A different offset value is required for each amplifier gain. INPUT BIAS CURRENT RETURN PATH The FET inputs of the PGA206 and PGA207 provide extremely high input impedance. Still, a path must be provided for the bias current of each input. Figure 3 shows provisions for an input bias current path. Without a bias current return path, the inputs will float to a potential which exceeds the linear input voltage range and the input amplifiers will saturate. If the differential source resistance is low, a bias current return path can be connected to only one input (see thermocouple example in Figure 3). With higher source impedance, using two resistors provides a balanced input with possible advantages of lower input offset voltage due to bias current and better common-mode rejection. Many sources or sensors inherently provide a path for input bias current (e.g. the bridge sensor shown in Figure 3). These applications do not require additional resistor(s) for proper operation.
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Microphone, Hydrophone etc.
PGA
47k
47k
Thermocouple
PGA
10k
PGA
VR
Center-tap provides bias current return.
Bridge PGA
Bias current return inherrently provided by source.
FIGURE 3. Providing an Input Bias Current Path.
PGA206/207
8
+15V 14 4 5 10nF 6 7 1nF 13 12 11 10 Channel 4 Software-Zero 9 PGA207 8 2 HI-509 1nF
Input Filter See Text
- VIN
1k
Channel 1
+ VIN
1k
A/D Converter ADS7807
15
3 -15V
1
16
74HC574
CK
To Address Logic
Data Bus
FIGURE 4. Multiplexed-Input Signal Acquisition System. INPUT COMMON-MODE RANGE The linear input voltage range of the PGA206 and PGA207 is from approximately 2.3V below the positive supply voltage to 1.5V above the negative supply. As a differential input voltage causes output voltage to increase, however, the linear input range is limited by the output voltage swing of amplifiers A1 and A2. So the linear common-mode input range is related to the output voltage of the complete amplifier. This behavior also depends on supply voltage-- see performance curves "Input Common-Mode Range vs Output Voltage". Input overload can produce an output voltage that appears normal. For example, if an input overload condition drives both input amplifiers to their positive output swing limit, the difference voltage measured by the output amplifier will be near zero. The output of the PGA206 or PGA207 will be near 0V even though both inputs are overloaded. This condition can be detected by sensing the voltage on the V01 and V02 pins to determine whether they are within their linear operating range. INPUT PROTECTION The inputs of the PGA206 and PGA207 are individually protected for voltages up to 40V. For example, a condition of -40V on one input and +40V on the other input will not cause damage. Internal circuitry on each input provides low series impedance under normal signal conditions. If the input is overloaded, the protection circuitry limits the input current to a safe value. The typical performance curve "Input Overload V/I Characteristic" shows this behavior. The inputs are protected even if no power supply voltage is applied.
(R)
MULTIPLEXED INPUTS The PGA206 and PGA207 are ideally suited for multiple channel data acquisition. Figure 4 shows a typical application with an analog multiplexer used to connect one of four differential input signals to a single PGA207. Careful circuit layout will help preserve accuracy of multiplexed signals. Run the inverting and non-inverting connections of each channel parallel to each other over a ground plane, or directly adjacent on top and bottom of the circuit board. Grounded guard traces between channels help reduce stray signal pick-up. Multiplexed signals from high impedance sources require special care. As inputs are switched by the multiplexer, charge can be injected into the source, disturbing the input signal. Since many such sources involve slow signals, a simple R/C filter at the input can be used to dramatically reduce this effect. The arrangement shown filters both the differential signal and common-mode noise.
9
PGA206/207
VO1 VIN VIN
+ -
PGA207 VO2 220 A1 A0 20k Ref
VO
20k
OPA131
Equal to input common-mode voltage.
FIGURE 5. Shield Drive Circuit.
GAIN (V/V)
G = 1, 2, 5, 10
- VIN
A1 0 0 1 1 0 1 1 0 1 1
A0 0 1 0 1 1 0 1 1 0 1
A3 0 0 0 0 0 0 0 1 1 1
A2 0 0 0 0 1 1 1 0 0 0
G = 1, 10, 100 7
PGA207
+ VIN
4
PGA103 3 2 1
VO
A1 A0
A 3 A2
1 2 5 10 20 50 100 200 500 1000
FIGURE 6. Wide Gain Range Programmable IA.
(R)
PGA206/207
10

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