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Elan Microelectronics Crop.
EM65168/EM65168A 80 COM/SEG LCD DRIVER
DEC 18, 2003 Version 0.8
Version
EM65168/EM65168A Specification Revision History Content
Date
0.1 0.2 0.3 0.4 0.5
Initial version 1. Add Pin configurations
2. COB bonding diagram
December 23, 2002 March 28,2003 March 31,2003 April 29, 2003 May 28,2003
Add BF,DON,HPM,RES control registers 1. Modify the DC characteristic
2. The RF register on page 19 3. Modify some descriptions on page 20
1.
2. 3. 4.
Modify EM65168 to EM65168/EM65168A.
Add the description of compatibility of EM65168A and EM83040A on page 4. Add the attention about EM65168A control registers on page 19. Add the resistor value level limitation of Ra and Rb when using external resistor on page 17 and 19. Add FIG. 10_1 and description of adding a capacitor across V1 and Vreg, and its recommended value on page16 & 17.
5.
0.6
1.
2. 3.
Modify LCD waveform(Fig.9) on page15.
Add the description of all COM/SEG voltage state when EN=1 on page 9. Add note about RAMW and RAMR control on page 9.
SEP 17,2003
0.7 0.8
1.
Modify IOH1 and IOL1 DC values on page 23 1. Modify VEV value and REG[5:0] setting value of DC spec. on page 23
2. Modify VEV values of REG[5:0] vs VEV table on page 16.
Nov 5,2003 Dec 18,2003
Caution: The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
EM65168/EM65168A LCD DRIVER
Contents
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.
GENERAL DESCRIPTION .......................................................................................................... 4 FEATURES ..................................................................................................................................... 4 APPLICATION .............................................................................................................................. 4 PIN CONFIGURATIONS.............................................................................................................. 5 BLOCK DIAGRAM....................................................................................................................... 8 PIN DESCRIPTION....................................................................................................................... 9 FUNCTION DESCRIPTION ...................................................................................................... 10 ABSOLUTE RATING.................................................................................................................. 23 DC CHARACTERISTIC............................................................................................................. 23 AC CHARACTERISTIC......................................................................................................... 25 AC TIMING.............................................................................................................................. 25 APPLICATION CIRCUIT ...................................................................................................... 27 PACKAGE INFORMATION .................................................................................................. 30
The information in this document is subject to change without notice.
3
EM65168/EM65168A LCD DRIVER
1. General description
The EM65168/EM65168A is a dot matrix LCD driver, which is fabricated by low power CMOS technology. This chip includes 80-bits shift register, 80 bits data latch and 80 bits level driver. A LCD RAM inside can be mapping to LCD signal. It converts RAM data to parallel data and output waveform to LCD.
2. Features
(1) Supply power: 2.5~5.5V (2) LCD drive voltage: 3.6 to 15V (3) Internal RAM: 6,400 bits (4) RAM can be controlled by eight signals including 4/8 bits bus. (5) Duty: 1/32, 1/48, 1/64, 1/80 (6) Build in DC/DC converter: double, triple, quad and five times. (7) Modularized function: connect to another EM65168/EM65168A to extent LCD matrix (8) One DC converter enabled and other EM65168/EM65168A can share with this. (9) Internal regulator output for DC/DC converter controlled by control register. (10) Bias Selectable: 1/5, 1/6, 1/7, 1/8, 1/9 (11) Internal RC clock about 24 KHz. (12) CMOS process (P-type silicon substrate) (13) EM65168A is compatible with EM83040A. (14) Package (Ordering information): Part Number EM65168H EM65168AH Versions Bare chip Bare chip Description NA NA Package information Page 30 Page 30
Note: The EM65168 series has the following sub-codes depending on their shapes. H: Bare chip (Aluminum pad without bumped); GH: Gold bumped chip; F: COF package; T: TAB (TCP) package Example EM65168H EM65168: Elan number ; H: Bare chip
3.
Application
Data Bank LCD toy Education computer
4
The information in this document is subject to change without notice.
EM65168/EM65168A LCD DRIVER
4.
Pin configurations
102 103
65 64
EM65168
DDRAM
44 128 1 39
Figure 1. Pin configuration Note: With the Elan logo in the center (as shown figure) and DDRAM (black color) on the right side the pin 1 is in the down left corner.
PIN DIMENSIONS
Size X Y
Item Chip size Pad size (min.) Pad pitch (min.)
Coordinate Origin
Pad No.
-
Unit
4260 85 100
Chip center
2150 90
m
The information in this document is subject to change without notice.
5
EM65168/EM65168A LCD DRIVER
PAD Coordinates Table (Total 114 pins) Pin NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 6 Pad Name GND CA VSS2+ VSS2V2 V3 VREG V1 V4 V5 O1 VOUT O2 VSS4 O3 VSS3 O4 CB O5 O6 O25 O7 O24 O8 O23 O9 O22 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 Coordinate (X,Y) -1880.0 ,-948.8 -1770.0 ,-948.8 -1660.0 ,-948.8 -1555.0 ,-948.8 -1450.0 ,-948.8 -1350.0 ,-948.8 -1250.0 ,-948.8 -1150.0 ,-948.8 -1050.0 ,-948.8 -950.0 ,-948.8 -850.0 ,-948.8 -750.0 ,-948.8 -650.0 ,-948.8 -550.0 ,-948.8 -450.0 ,-948.8 -350.0 ,-948.8 -250.0 ,-948.8 -150.0 ,-948.8 -50.0 ,-948.8 50.0 ,-948.8 150.0 ,-948.8 250.0 ,-948.8 350.0 ,-948.8 450.0 ,-948.8 550.0 ,-948.8 650.0 ,-948.8 750.0 ,-948.8 850.0 ,-948.8 950.0 ,-948.8 1050.0 ,-948.8 1150.0 ,-948.8 1250.0 ,-948.8 1350.0 ,-948.8 1450.0 ,-948.8 1555.0 ,-948.8 1660.0 ,-948.8 1770.0 ,-948.8 1880.0 ,-948.8 2003.8 ,-948.8 Pin NO 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pad Name O33 O34 O35 O36 O37 O38 O39 O40 O41 O42 Coordinate (X,Y) 2003.8 ,-100.0 2003.8 ,0.0 2003.8 ,100.0 2003.8 ,200.0 2003.8 ,300.0 2003.8 ,400.0 2003.8 ,500.0 2003.8 ,605.0 2003.8 ,715.0 2003.8 ,825.0
O26 O27 O28 O29 O30 O31 O32
2003.8 ,-825.0 2003.8 ,-715.0 2003.8 ,-605.0 2003.8 ,-500.0 2003.8 ,-400.0 2003.8 ,-300.0 2003.8 ,-200.0
O47 O48 O49 O50 O51 O52 O53 O54 O55 O56 O57 O58 O46 O59 O45 O60 O44 O61 O43 O62 O63 O80 O64 O79 O65 O78 O66 O77 O67 O68 O69 O70 O71 O72 O73 O74 O75
2003.8 ,948.8 1880.0 ,948.8 1770.0 ,948.8 1660.0 ,948.8 1555.0 ,948.8 1450.0 ,948.8 1350.0 ,948.8 1250.0 ,948.8 1150.0 ,948.8 1050.0 ,948.8 950.0 ,948.8 850.0 ,948.8 750.0 ,948.8 650.0 ,948.8 550.0 ,948.8 450.0 ,948.8 350.0 ,948.8 250.0 ,948.8 150.0 ,948.8 50.0 ,948.8 -50.0 ,948.8 -150.0 ,948.8 -250.0 ,948.8 -350.0 ,948.8 -450.0 ,948.8 -550.0 ,948.8 -650.0 ,948.8 -750.0 ,948.8 -850.0 ,948.8 -950.0 ,948.8 -1050.0 ,948.8 -1150.0 ,948.8 -1250.0 ,948.8 -1350.0 ,948.8 -1450.0 ,948.8 -1555.0 ,948.8 -1660.0 ,948.8
The information in this document is subject to change without notice.
EM65168/EM65168A LCD DRIVER
Pin NO 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
Pad Name O76 MAIN MD
Coordinate (X,Y) -1770.0 ,948.8 -1880.0 ,948.8 -2003.8 ,948.8
Pin NO
Pad Name
Coordinate (X,Y)
M1 M0 EN RAMENB RAMADS RAMW RAMR RAMD7 RAMD6 RAMD5 RAMD4 RAMD3 RAMD2 RAMD1 RAMD0 VDD LOAD
-2003.8 ,825.0 -2003.8 ,715.0 -2003.8 ,605.0 -2003.8 ,500.0 -2003.8 ,400.0 -2003.8 ,300.0 -2003.8 ,200.0 -2003.8 ,100.0 -2003.8 ,0.0 -2003.8 ,-100.0 -2003.8 ,-200.0 -2003.8 ,-300.0 -2003.8 ,-400.0 -2003.8 ,-500.0 -2003.8 ,-607.5 -2003.8 ,-715.0 -2003.8 ,-825.0
FR
-2003.8 ,-948.8
Note : For PCB layout, IC substrate must be connected to GND.
The information in this document is subject to change without notice.
7
EM65168/EM65168A LCD DRIVER
5. Block diagram
FR,LOAD O1~ O80
Display timing generator Oscillator Circuit
LCD Driver
Common/ Segment Circuit
MAIN,M1,M0,MD
80 bits Data Latch EN RAMEN RAMADS RAMW RAMR RAMD0~D8 MPU interface
80 bits Shift Register
LCD Data Ram (DDRAM) 6,400 bits Control Register
Power Supply Circuit
V1,V2,V3,V4,V5
VOUT
VSS4
VSS3
FIG. 2 Block Diagram
VSS2+
VSS2-
CA
CB
VREG
8
The information in this document is subject to change without notice.
EM65168/EM65168A LCD DRIVER
6.
Pin description
I/O Function PIN No. Power System power supply 1 Power Ground 1 Voltage converter input/output pin Power Connect this pin to GND through capacitor 1 EN=1,VOUT=VDD-Vt Power Step-up capacitor 1 Power Step-up capacitor 1 Power Step-up capacitor 1 Power Step-up capacitor 1 Output voltage regulator terminal. Provides the voltage Power 1 between V1 and GND through a resistive voltage divider. Master or slave control signal. I MAIN=1, master unit 1 MAIN=0, slave unit This pin control whole chip power. This chip will work when this pin is connected to ground. And whole chip will disable when connect to VDD voltage. I 1 EN=0 and MAIN=1 the chip will generate VSS2+, VSS2VSS3, VSS4, VOUT, LOAD, FR signal and internal RC clock. EN=1, standby mode (all COM/SEG output to GND level) MD=0: 4-bit bus mode, the RAMD3~RAMD0 is valid, I 1 RAMD7~DAMD4 must be connected to VDD or GND level MD=1: 8-bit bus mode, the RAMD7~RAMD0 is valid I Mode select 1 I Mode select 1 RAM read and write control signal. I 1 1 => can not read and write. 0=> can read and write. RAM bus (RAMD[7:0]) select signal I 1 1=> RAM Data bus, 0=>RAM Address bus I RAM write signal, low active 1 I RAM read signal, low active 1 RAMW 1 1 0 0 RAMR 1 0 1 0 RAMD[7:0] Tri-state Output Input Tri-state RAM data or address bus For 4-bits bus mode, RAMD[3:0] is valid and RAMD[7:4] is 8 I/O not used, it must be connected to VDD or VSS level. For 8-bits bus mode, RAMD[7:0] is valid LCD load signal between one common signal to another. I/O 1 MAIN=1: The master unit will output LOAD signal. MAIN=0: The slave will accept the signal from master unit. This is the liquid crystal alternating current signal I/O terminal. I/O 1 MAIN=1: The master unit will output FR signal. MAIN=0: The slave will accept the signal from master unit. I Step-up capacitor 1 I Step-up capacitor 1 Reference voltage input, V1U V2U V3U V4U V5 I 5 O LCD waveform output 80
Pin name VDD GND VOUT VSS4 VSS3 VSS2+ VSS2VREG MAIN
EN
MD M1 M0 RAMEN RAMADS RAMW RAMR
RAMD[7:0]
LOAD
FR CA CB V1~V5 O1~O80
The information in this document is subject to change without notice.
9
EM65168/EM65168A LCD DRIVER
7.
Function description
(1) User can use MAIN pin to choose master unit or slave unit. MAIN 1 0 Unit MASTER SLAVE Function Generate these signals: FR, LOAD, V1, V2, V3, V4, V5 Internal RC clock Accept these Master unit signals: FR, LOAD, V1, V2, V3, V4, V5 No internal RC clock
(2) User can use M1, M2 to choose four modes. As followed MASTER Mode1 Mode2 Mode3 Mode4 SLAVE Mode1 Mode2 Mode3 Mode4 MAIN 1 1 1 1 MAIN 0 0 0 0 M1 0 0 1 1 M1 0 0 1 1 M0 0 1 0 1 M0 0 1 0 1 Segment O(16:1)=S(16:1) O(32:1)=S(32:1) O(48:1)=S(48:1) Segment O(80:1)=S(80:1) O(80:1)=S(80:1) O(80:1)=S(80:1) O(80:1)=S(80:1) Common O(80:17)=C(64:1) O(80:1)=C(80:1) O(80:33)=C(48:1) O(80:49)=C(32:1) Common BIAS 1/9 1/9 1/7 1/5 BIAS 1/9 1/9 1/7 1/5
* S=Segment, C=Common, * (M1, M0) for Master must same as Slave unit
(3) The relationship of FOSCB LOAD and FR frequency MAIN 1 1 1 1 M1 0 0 1 1 M0 0 1 0 1 Description 64 common (1/64 duty) 80 common (1/80 duty) 48 common (1/48 duty) 32 common (1/32 duty) fOSC 24KHz 24KHz 24KHz 24KHz
LOAD
fOSC/5=4.8K fOSC/4=6.0K fOSC/7=3.4K fOSC/10=2.4K
FR LOAD/64=75.0 Hz LOAD/80=75.0 Hz LOAD/48=71.4 Hz LOAD/32=75.0 Hz
(4) RAM control LCD RAM can be read or written via control signal. When #RAMEN pin is at low state, the RAM can be read or written in data. The RAMADS can be set as RAMD[7:4] to be used as address bus or data bus. When it used as Address and in 4-bit mode, the #RAMEN pin should remain low and users need to set three times Address as RAMD[3:0] by following the Address setting sequence: Address[11:8] (A11, A10, A9, A8), Address[7:4] (A7, A6, A5, A4), and Address[3:0] (A3, A2, A1. A0). If the Address bus is in 8-bit mode, users need to set two times Address as RAMD[7:0] by following the Address setting sequence: Address[10:8] (x,x,x,x,x,A10, A9, A8), Address[7:0] (A7, A6, A5, A4, A3, A2, A1. A0). When it used as Data bus, the #RAMEN pin will be at high state, users can read or write single data or continuously read or write multiple data. When read or write data from RAM, the
10
The information in this document is subject to change without notice.
EM65168/EM65168A LCD DRIVER
Address will plus 1, and once #RAMEN pin become at high state, users cannot read or write to RAM.
LCD RAM Write mode 4-bit bus mode
RAMEN
RAM enable
RAMADS RAMD[3:0] A3
Tdh
Tdd A2 A1 D1 D2 D3
RAMW
Tw
RAMR A3=(a11,a10,a9,a8) A2=(a7,a6,a5,a4) A1=(a3,a2,a1,a0)
FIG. 3 LCD RAM write mode for 4-bit bus 8-bit bus mode
RAMEN
RAM enable
RAMADS RAMD[7:0] A2
Tdh
Tdd A1 D1 D2 D3
RAMW
Tw
RAMR A2=(x,x,x,x,x,a10,a9,a8) A1=(a7,a6,a5,a4,a3,a2,a1,a0)
FIG. 4 LCD RAM write mode for 8-bit bus
The information in this document is subject to change without notice.
11
EM65168/EM65168A LCD DRIVER
LCD RAM Read mode 4-bit bus mode
RAMEN
RAM enable
RAMADS RAMD[3:0] A3
Tdh
Tdd A2 A1 D1 D2 D3
RAMW
Tw
Tdv
Tdh
RAMR A3=(a11,a10,a9,a8) A2=(a7,a6,a5,a4) A1=(a3,a2,a1,a0)
FIG. 5 LCD RAM read mode for 4-bit bus 8-bit bus mode
RAMEN
RAM enable
RAMADS RAMD[7:0] A2
Tdh
Tdd A1 D1 D2 D3
RAMW
Tw
Tdv
Tdh
RAMR A2=(x,x,x,x,x,a10,a9,a8) A1=(a7,a6,a5,a4,a3,a2,a1,a0)
FIG. 6 LCD RAM read mode for 8-bit bus (5) RAM mapping 4-bit bus mode: RAM address is from 000H to address A05HA control register is from A00H to A05H 8-bit bus mode: RAM address is from 000H to address 503HA control register is from 500H to 502H User fill "1" to LCD RAM, LCD driver will generate "light" waveform. Otherwise, it will generate a "dark" waveform. The LCD RAM area is mapped to segment 1 to segment 80. And user can refer to FIG. 7,8 and Table 1 to get the idea of LCD ram mapping. The other RAM(Area11) is prohibited.
12
The information in this document is subject to change without notice.
EM65168/EM65168A LCD DRIVER
Table 1: LCD mapping RAM area Master/slave Master Master Master Master Slave Slave Slave Slave Any Master Common No. 32 48 64 80 32 48 64 80 Any Segment N0. 48 32 16 0 80 80 80 80 Any LCD Display area 1,2,3 1,2,5,6 1,5,8 No mapping RAM 1,2,3,4 1,2,3,4,5,6,7 1,2,3,4,5,6,7,8,9 1,2,3,4,5,6,7,8,9,10 Area 11 is prohibited
Corlo reger (Addr. A00H~A05H) tn tsi 9FFH 9DFH 9F4H 9D4H 9F3H 9D3H 9E0H 9C0H
C80 C79 -----
Area 10
83FH 81FH 7FFH 7DFH 834H 814H 7F4H 7D4H 833H 813H 7F3H 7D3H 7E4H 7C4H 7E3H 7C3H 820H 800H
C66 C65 7E0H C64 7C0H C63 -----
Area 11
63FH 61FH 5FFH 5DFH 634H 614H 5F4H 5D4H 633H 613H 5F3H 5D3H -
Area 9
5E8H 5C8H 5E7H 5C7H 624H 604H 5E4H 5C4H
Area 8
623H 603H 5E3H 5C3H 620H 600H
C50 C49 5E0H C48 5C0H C47 -----
Area 7
43FH 41FH 3FFH 3DFH 434H 414H 3F4H 3D4H 433H 413H 3F3H 3ECH 3EBH 3CCH 3CBH 428H 408H 3E8H 3C8H
Area 6
427H 407H 3E7H 3C7H 424H 404H 3E4H 3C4H
Area 5
423H 403H 3E3H 3C3H 420H 400H
3D3H -
C34 C33 3E0H C32 3C0H C31 -----
-----------
-----------
-
Empty Area
Area 4
Prohibiton
03FH 01FH -------- 034H -------- 014H 033H 013H
Area 3
-----------
Area 2
-----------
Area 1
C18 C7 C16 C15 -----
----------------------------------------- 02CH 02BH ----------------------------------------- 00CH 00BH
------------------ 028H -------- 008H 027H 007H -------- 024H -------- 004H 023H 003H
-------- 020H -------- 000H d3d2d1d0
S15 S16 S17 S18
C2 C1
FIG. 7 RAM mapping of LCD display for 4 bits bus mode
The information in this document is subject to change without notice.
S79 S80
S63 S64 S65 S66
S47 S48 S49 S50
S31 S32 S33 S34
S1 S2
-----
-----
-----
-----
-----
13
EM65168/EM65168A LCD DRIVER
Corlo reger (Addr. 500H~502H) tn st i 4FFH 4EFH 4FAH 4F9H 4F0H 4E0H
4EAH 4E9H -
C80 C79 -----
Area 10
41FH 40FH 3FFH 3EFH 41AH 40AH 3FAH 419H 409H 3F9H 3F2H 3E2H 3F1H 3E1H 410H 400H
3EAH 3E9H -
C66 C65 3F0H C64 3E0H C63 -----
Area 11
31FH 30FH 2FFH 2EFH 31AH 30AH 2FAH 319H 309H 2F9H -
Area 9
2F4H 2E4H 2F3H 2E3H 312H 302H 2F2H 2E2H
Area 8
311H 301H 2F1H 2E1H 310H 300H
2EAH 2E9H -
C50 C49 2F0H C48 2E0H C47 -----
Area 7
21FH 20FH 1FFH 1EFH 21AH 20AH 1FAH 219H 209H 1F9H 1F6H 1E6H 1F5H 1E5H 214H 204H 1F4H 1E4H
Area 6
213H 203H 1F3H 1E3H 212H 202H 1F2H 1E2H
Area 5
211H 201H 1F1H 1E1H 210H 200H
1EAH 1E9H -
C34 C33 1F0H C32 1E0H C31 -----
-----------
-----------
-
Empty Area
Area 4
Prohibiton
01FH 00FH 01AH -------- 00AH 019H 009H 016H
Area 3
-----------
Area 2
-----------
Area 1
C18 C7 C16 C15 -----
----------------------------------------- 006H
----------015H 005H 014H -------- 004H 013H 003H 012H -------- 002H 011H 001H -
-------- 000H
d7d6d5d4d3d2d1d0
010H
C2 C1
S15 S16 S17 S18
FIG. 8 RAM mapping of LCD display for 8bits bus mode
S79 S80
S63 S64 S65 S66
S47 S48 S49 S50
S31 S32 S33 S34
S1 S2
-----
-----
-----
-----
-----
14
The information in this document is subject to change without notice.
EM65168/EM65168A LCD DRIVER
(6) LCD waveform
FR
LOAD
V1 V2 V3 V4 V5 GND
COM1
COM2
V1 V2 V3 V4 V5 GND
COM3
V1 V2 V3 V4 V5 GND
SEG1
non-light
light
SEG2
V1 V2 V3 V4 V5 GND
V1 V2 V3 V4 V5 GND
FIG. 9 LCD Waveform (7) Control register 4-bit mode data bus Address A00H A01H A02H A03H A04H A05H 8-bit mode data bus Address 500H 501H 502H Bit7 PMS1 BSE BF Bit6 PMS0 BS2 RF2 Bit5 REG5 BS1 RF1 Bit4 REG4 BS0 RF0 Bit3 REG3 IRS X Bit2 REG2 IR2 DON Bit1 REG1 IR1 HPM Bit0 REG0 IR0 RES Initial state 00000000 (00H) 00000010 (02H) 00000000 (00H) Bit3 REG3 PMS1 IRS BSE X BF Bit2 REG2 PMS0 IR2 BS2 DON RF2 Bit1 REG1 REG5 IR1 BS1 HPM RF1 Bit0 REG0 REG4 IR0 BS0 RES RF0 Initial state 0000 (0H) 0000 (0H) 0010 (2H) 0000 (0H) 0000 (0H) 0000 (0H)
The information in this document is subject to change without notice.
15
EM65168/EM65168A LCD DRIVER
The power supply circuit mode select (PMS1, PMS0) Use settings Only the internal power supply is used Only the V regulator circuit and the V/F circuit are used Only the V/F circuit is used Only the external power supply is used PMS1 PMS0 1 1 0 0 1 0 1 0 V Step-up V/F regulator circuit circuit circuit R X X X R R X X R R R X External voltage input X VOUT V1 V1 to V5
The Voltage Regulator Circuit, (REG5~REG0) is selected the voltage of VEV REG5 REG4 REG3 REG2 REG1 REG0 0 0 0 0 0 0 0 0 0 0 0 1 o 0 1 1 1 1 1 1 0 0 0 0 0 o 1 1 1 1 1 0 1 1 1 1 1 1
VOUT
VOUT
VEV 1.2 V 1.212 V o 1.593 V 1.606 V o 1.987 V 2.0 V
VEV step
0.0127V
V1
V1
Rb
C
Rb
VEV
VREG
VEV
VREG
Ra
Ra
FIG. 10
FIG. 10_1
The internal resistor select (IRS) and (IR2, IR1, IR0) is selected for the V1 voltage regulator internal resistance ratio. IRS=0: internal regulator resistor is used. IRS=1: internal regulator resistor is not used. (External resistor is used)
16
The information in this document is subject to change without notice.
EM65168/EM65168A LCD DRIVER
IR2 IR1 IR0 Resistor ratio (1+Rb/Ra) 0 0 0 3.0 0 0 1 3.5 0 1 0 4.0 0 1 1 4.5 1 0 0 5.0 1 0 1 5.5 1 1 0 6.0 1 1 1 6.5 The V1 voltage can be calculated using equation A over the range where VDDVOUT
Example: Default: IRS=0 (internal regulator resistor is used), (IR2, IR1, IR0)=(0, 1, 0), and (REG5~0)=(000000) V1=(1+Rb/Ra)*VEV*(0.97~1.03)=4.0*1.2*(0.97~1.03)= 4.656~4.944 V When IRS=0 (internal regulator resistor is used), (IR2, IR1, IR0)=(0, 1, 1), and (REG5~0)=(100000) V1=(1+Rb/Ra)*VEV*(0.97~1.03)=4.5*1.606*(0.97~1.03)= 7.01~7.44 V
The output voltage of V1 is determined by function of the V1 voltage regulator ratio register (1+Rb/Ra), and the electric volume resister (REG5~REG0). Note: When external resistor is used(FIG. 10_1), 1. Ra and Rb values must to be M[ (1+Rb/Ra) is 3.0, we give Ra=1 M[ level, for example, if the desired value of
and Rb=2 M[ .
2. Add a capacitor across V1 and Vreg, and the recommended value of C is 10nF~100nF.
EM6 5 1 6 8 111 110 101 100 011 010 001 000
12 10 8 6 4 2 0
( I R2 ~I R0 )
( REG5 ~REG0 )
FIG. 11 The output voltage curve of V1
3 FH
00H
18H
30H
The information in this document is subject to change without notice.
17
EM65168/EM65168A LCD DRIVER
LCD Bias set BSE=0: The LCD bias is not selectable M1 0 0 1 1 M0 0 1 0 1 BIAS 1/9 1/9 1/7 1/5
BSE=1: The LCD bias is selectable by setting BS2, BS1, BS0 BS2 0 0 0 0 1 1 1 1 RES The internal circuit can be initialized. This register is effective only at Master operation mode. (This register is a read-only bit.) RES = "0": Normal operation RES = "1": Initialization ON When the reset operation begins internally after RES register sets to "1", the RES register is automatically cleared to "0". [Caution: It needs to wait for more than 20 ms after setting RES bit] BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 BIAS 1/5 1/6 1/7 1/8 1/9 Prohibit (1/9) Prohibit (1/9) Prohibit (1/9)
HPM The HPM register is the power control for the power supply circuit for liquid crystal drive. HPM = "0": Normal mode HPM = "1": High power mode
DON
The DON register controls the LCD display turning on or off. DON= "0": Display OFF (All COM/SEG output GND level) DON= "1": Display ON
18
The information in this document is subject to change without notice.
EM65168/EM65168A LCD DRIVER
The RF registers (RF2, RF1, RF0) can control resistance ratio of CR oscillator. Therefore frame frequency can change RF registers setting. RF2 0 0 0 0 1 1 1 1 RF1 0 0 1 1 0 0 1 1 RF0 0 1 0 1 0 1 0 1 Operation Initial resistance ratio 1.2 times initial resistance ratio 0.9 times initial resistance ratio Initial resistance ratio 0.8 times initial resistance ratio Initial resistance ratio 1.1 times initial resistance ratio Initial resistance ratio
BF
The BF register controls the operating frequency of the booster. BF 0 1 Operating clock frequency in the booster 1.5K Hz * 4 1.5 K Hz
Note: IF Step-up capacitor (C2 showed as Fig. 12) is less 1 uF, BF control register must be set "0".
Attention: EM65168A have fixed some control bits of Control Register, so original user
using EM83040A can use external resistor and set VEV=1.56V, to get
V1 = (1 +
Rb' Rb' ) VEV = 1.56 (1 + ) by adding external resistors, Ra', Rb', but Ra' and Ra ' Ra '
level; the fixed control bits are shown below: Bit6 PMS0 BS2 RF2 Bit5 REG5 BS1 RF1 Bit4 REG4 BS0 RF0 Bit3 REG3 IRS X Bit2 REG2 IR2 DON Bit1 REG1 IR1 HPM Bit0 REG0 IR0 RES Fixed bits 11011110 0xxx1xxx 0000x100 Bit7 PMS1 BSE BF
Rb' values must to be M[ Address 500H 501H 502H Note:
1. The control register(500H) is fixed to 11011110 2. The BSE bit is fixed to 0, and the IRS bit is fixed to 1 3. The control register(502H) is fixed to 0000x100
The information in this document is subject to change without notice.
19
EM65168/EM65168A LCD DRIVER
(8) The step-up voltage circuit Placing capacitor C2 in different configurations in Fig 12 and across VOUT and VSS boosts the voltage coming from VDD and VSS n-times and outputs the boosted voltage to VOUT pin. (a) Double step-up, (b) Triple step-up, (c) Quad step-up (d) five times step-up C1=0.47 to 3.3f, C2=0.1 to 2.2uf
VOUT VSS4 VSS3 CB
C2
VOUT VSS4 VSS3 CB
C2
VOUT VSS4
C2 C2
VOUT
C2
VSS4 VSS3 CB CA
C2 C2 C2
VSS3 CB CA
C2 C2
CA
CA
EM65168
EM65168
EM65168
VSS2+ VSS2VREG
C1
C2
VSS2+ VSS2VREG V1 V2 V3 V4 V5
C2
VSS2+ VSS2VREG
EM65168
C2
VSS2+ VSS2VREG V1 V2 V3 V4 V5
C2
V1 V2 V3 V4 V5
C1
V1 V2 V3 V4 V5
C1
C1
(a) VOUT=2*VDD
(b) VOUT=3*VDD
(c) VOUT=4*VDD
(d) VOUT=5*VDD
FIG. 12
20
The information in this document is subject to change without notice.
EM65168/EM65168A LCD DRIVER
(9)Reference circuit examples are as following FIG. 13 (a)Only the internal power supply is used, control register (PS1, PS0, IRS)=(1,1,0) (b)Only the V regulator circuit and the V/F circuit are used, control register (PS1, PS0, IRS)=(1,0,0) (c)Only the internal power supply is used, control register (PS1, PS0, IRS)=(1,1,1) When internal regulator resistor is not used (external resistor is used), V1=VREG*(1+Rb'/Ra') (d)Only the V regulator circuit and the V/F circuit are used, control register (PS1, PS0, IRS)=(1,0,1), When internal regulator resistor is not used (external resistor is used), V1=VREG*(1+Rb'/Ra') (e)Only the V/F circuit is used, control register (PS1, PS0)=(0,1) (f)Only the external power supply is used, control register (PS1, PS0)=(0,0)
VDD
VOUT MAIN VSS4 VSS3 CB
C2 C2 C2
VDD
VOUT MAIN VSS4 VSS3 CB CA
EXTERNAL POWER SUPPLY
VDD
VOUT MAIN VSS4 VSS3 CB
C2 C2 C2
CA
CA
EM 65168
EM 65168
VSS2+
C2
VSS2+ VSS2VREG V1 V2 V3 V4 V5
EM 65168
VSS2+
C2
VSS2VREG V1 V2 V3 V4 V5
C1
VSS2VREG V1 V2 V3 V4 V5
Ra' Rb'
C1
C1
(a)
(b)
(c)
The information in this document is subject to change without notice.
21
EM65168/EM65168A LCD DRIVER
VOUT VDD MAIN VSS4 VSS3 CB CA
EXTERNAL POWER SUPPLY
VOUT VDD MAIN VSS4 VSS3 CB CA VDD MAIN
VOUT VSS4 VSS3 CB CA
EM65168
EM65168
VSS2+ VSS2Ra'
VSS2+ VSS2VREG
EXTERNAL POWER SUPPLY
EM65168
VSS2+ VSS2VREG V1 V2 V3 V4 V5
VREG
Rb'
V1 V2 V3 V4 V5
C1
V1 V2 V3 V4 V5
C1
EXTERNAL POWER SUPPLY
(d)
(e) FIG. 13
(f)
22
The information in this document is subject to change without notice.
EM65168/EM65168A LCD DRIVER
8. Absolute rating
Rating DC Supply Voltage INPUT VOLTAGE OPERATING TEMPERATURE RANGE Symbol VDD Vin Ta Value <6 -0.5 TO Vdd +0.5 -30 TO 80 Unit V V J
9. DC characteristic
(Test condition: If not specified, Ta=25C ;VDD=3V, VSS=0V) Symbol VDD VIH VIL IOH1 IOL1 IOH2 IOL2 ILI ILO Condition Min Typ Max Unit With double step-up 2.5 5.5 With triple step-up 2.5 5.5 Input voltage V With quad step-up 2.5 4.0 With five times step-up 2.5 3.3 High level input voltage 1 0.8VDD 0.9VDD VDD V Low level input voltage 1 0 0.1VDD 0.2VDD V High level output current VOH = VDD-0.4V 2 -2.4 -3.2 -4.5 mA Low level output current VOL= 0.4V 2 2.4 3.2 4.5 mA High level output current VOH = VDD-0.4V *3 -0.8 -1.0 -1.2 mA Low level output current VOL= 0.4V 3 0.8 1.0 1.2 mA Input leakage current VI = VSS or VDD 4 -2 0 2 A Output leakage current VI = VSS or VDD 5 -2 0 2 A EN=0. MAIN =1 (MASTER), DC converter enable, Five times step-up ;Display all 110 160 A on pattern (M1, M0)=(1,1), V1=11V 24KHz clock, No load Operating current EN=0. MAIN =1 (MASTER), DC converter enable, Three times step-up ;Display all 85 135 A on pattern (M1, M0)=(1,1), V1=11V 24KHz clock, No load Standby mode EN=1 1 2 A Voltage variation of Ta=0J ; REG[5:0]=111111 0.97*VEV TBD 1.03*VEV V regulator Ta=25J ; REG[5:0]=111111 1.94 2.0 2.06 V Ta=40J ; REG[5:0]=111111 TBD 1.03*VEV V 0.97*VEV Step-up circuit output x2/x3/x4/x5 RL=500k (Step-up 95 99 100 % voltage Capacitor =1 uF) LCD voltage capacitor V1,V2,V3,V4,V5 0.47 1 3.3 F Step-up capacitor CA,CB,VSS2+,VSS2-,VSS3,V 0.1 1 2.2 F SS4 Internal oscillator Ta=25J 20 24 28 kHz frequency LCD ON resistance 1.2 2 V1=9V, 1/9bias |V|=0.5V K Parameter
Iop
Isb VEV VOUT Cv Cs fosc RON
The information in this document is subject to change without notice.
23
EM65168/EM65168A LCD DRIVER
Note: 1 RAMD[7:0], MAIN, EN,M1,M0,RAMEN,RAMADS, RAMW,RAMR pins. 2 RAMD[7:0] pins 3 FR,LOAD pins 4 MAIN, EN,M1,M0,RAMEN,RAMADS,RAMW,RAMR pins 5 Applied when RAMD[7:0], FR and LOAD are in the state of high impedance.
24
The information in this document is subject to change without notice.
EM65168/EM65168A LCD DRIVER
10. AC Characteristic
(Ta= -30C ~ 80C, VDD=3V, VSS=0V) Symbol Vrc Tframe Tw Tdh Tdd Tdv Parameter RC clock variable Frame period Write low pulse Data hold time Data to data time Data valid time Min. -20 1/60 700 100 100 700 Typ. 1/75 Max. +20 1/90 Unit % S nS nS nS nS
11. AC timing
4-bits data bus mode
EN
RAMEN
RAM enable
RAMADS RAMD[3:0] A3
Tdh
Tdd A2 A1 D1 D2 D3
RAMW
Tw
RAMR A3=(a11,a10,a9,a8) A2=(a7,a6,a5,a4) A1=(a3,a2,a1,a0)
FIG 14 LCD RAM write mode 8-bits data bus mode
EN
RAMEN
RAM enable
RAMADS RAMD[7:0] A2
Tdh
Tdd A1 D1 D2 D3
RAMW
Tw
RAMR A2=(x,x,x,x,x,a10,a9,a8) A1=(a7,a6,a5,a4,a3,a2,a1,a0)
FIG 15 LCD RAM write mode
The information in this document is subject to change without notice.
25
EM65168/EM65168A LCD DRIVER
4-bits data bus mode
EN
RAMEN
RAM enable
RAMADS RAMD[3:0] A3
Tdh
Tdd A2 A1 D1 D2 D3
RAMW
Tw
Tdv
Tdh
RAMR A3=(a11,a10,a9,a8) A2=(a7,a6,a5,a4) A1=(a3,a2,a1,a0)
FIG 16 LCD RAM read mode
8-bits data bus mode
EN
RAMEN
RAM enable
RAMADS RAMD[7:0] A2
Tdh
Tdd A1 D1 D2 D3
RAMW
Tw
Tdv
Tdh
RAMR A2=(x,x,x,x,x,a10,a9,a8) A1=(a7,a6,a5,a4,a3,a2,a1,a0)
FIG 17 LCD RAM read mode
26
The information in this document is subject to change without notice.
EM65168/EM65168A LCD DRIVER
12. Application circuit
(1) C32 x S48
C32
LCD 32*48
S48 O80...O1 VDD GND VDD VDD VDD VDD MAIN M1 M0 MD EN S1 NC NC
C1
FR LOAD VOUT VSS4 VSS3 CB
EM65168
CA VSS2+ VSS2VREG V1 V2 V3 V4 V5 NC
MCU
RAMEN RAMADS RAMW RAMR RAMD(7:0)
MCU
MASTER
FIG. 18 32common*48segment application circuit (2) C32 x S128
C32
LCD 32*128
S128 O80...O1 VDD GND VDD VDD VDD VDD MAIN M1 M0 S81 FR LOAD VDD GND GND VDD VDD VDD MAIN M1 M0 MD EN S80 O80...O1 S1 FR LOAD VOUT VSS4 VSS3 CB FR LOAD NC NC NC NC NC NC NC NC
C1
FR LOAD VOUT VSS4 VSS3 CB
EM65168
M0 EN
VSS2+ VSS2VREG V1 V2 V3 V4 V5 NC
EM65168
CA
CA VSS2+ VSS2VREG V1 V2 V3 V4 V5
MCU
RAMEN RAMADS RAMW RAMR RAMD(7:0)
MCU
RAMEN RAMADS RAMW RAMR RAMD(7:0)
CONNECT TO MASTER CHIP
MASTER
SLAVE1
FIG. 19 32common*128segment application circuit The information in this document is subject to change without notice. 27
EM65168/EM65168A LCD DRIVER
(3) C48 x S112
C48
LCD 48*112
S112 O80...O1 VDD GND VDD VDD GND VDD MAIN M1 M0 S81 FR LOAD VDD GND GND VDD GND VDD MAIN M1 M0 MD EN S80 O80...O1 S1 FR LOAD VOUT VSS4 VSS3 CB FR LOAD NC NC NC NC NC NC NC NC
C1
FR LOAD VOUT VSS4 VSS3 CB
EM65168
MD EN
VSS2+ VSS2VREG V1 V2 V3 V4 V5 NC
EM65168
CA
CA VSS2+ VSS2VREG V1 V2 V3 V4 V5
MCU
RAMEN RAMADS RAMW RAMR RAMD(7:0)
MCU
RAMEN RAMADS RAMW RAMR RAMD(7:0)
CONNECT TO MASTER CHIP
MASTER
SLAVE1
FIG. 20 48common*112segment application circuit (4) C64 x S96
C64
LCD 64*96
S96 O80...O1 VDD GND VDD GND GND VDD MAIN M1 M0 S81 FR LOAD VDD GND GND GND GND VDD MAIN M1 M0 MD EN S80 O80...O1 S1 FR LOAD VOUT VSS4 VSS3 CB FR LOAD NC NC NC NC NC NC NC NC
C1
FR LOAD VOUT VSS4 VSS3 CB
EM65168
MD EN
VSS2+ VSS2VREG V1 V2 V3 V4 V5 NC
EM65168
CA
CA VSS2+ VSS2VREG V1 V2 V3 V4 V5
MCU
RAMEN RAMADS RAMW RAMR RAMD(7:0)
MCU
RAMEN RAMADS RAMW RAMR RAMD(7:0)
CONNECT TO MASTER CHIP
MASTER
SLAVE1
FIG. 21 64common*96segment application circuit 28 The information in this document is subject to change without notice.
EM65168/EM65168A LCD DRIVER
(5) C80*S160
C80
LCD 80*160
S80 O80...O1 VDD GND VDD GND VDD VDD MAIN M1 M0 FR LOAD VOUT VSS4 VSS3 CB GND GND VDD VDD FR LOAD O80...O1 VDD GND MAIN M1 M0 MD EN S1 FR LOAD VOUT VSS4 VSS3 CB FR LOAD NC NC NC NC NC NC NC NC
C1
EM65168
MD EN
VSS2+ VSS2VREG V1 V2 V3 V4 V5 NC
EM65168
CA
CA VSS2+ VSS2VREG V1 V2 V3 V4 V5
MCU
RAMEN RAMADS RAMW RAMR RAMD(7:0)
MCU
RAMEN RAMADS RAMW RAMR RAMD(7:0)
CONNECT TO MASTER CHIP
MASTER
SLAVE1
S160 VDD GND GND GND VDD VDD MAIN M1 M0 MD EN O80...O1 S81 FR LOAD VOUT VSS4 VSS3 CB FR LOAD NC NC NC NC NC NC NC NC
EM65168
CA VSS2+ VSS2VREG V1 V2 V3 V4 V5
MCU
RAMEN RAMADS RAMW RAMR RAMD(7:0)
CONNECT TO MASTER CHIP
SLAVE2
FIG. 22 80common*160segment application circuit
The information in this document is subject to change without notice.
29
EM65168/EM65168A LCD DRIVER
13. Package information
EM65168/EM65168A COB bonding diagram
(Recommend using the following method to improve the bonding yield)
30
The information in this document is subject to change without notice.

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