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Features
* Fast Read Access Time - 120 ns * Fast Byte Write - 200 s or 1 ms * Self-timed Byte Write Cycle
- Internal Address and Data Latches - Internal Control Timer - Automatic Clear Before Write Direct Microprocessor Control - READY/BUSY Open Drain Output - DATA Polling Low Power - 30 mA Active Current - 100 A CMOS Standby Current High Reliability - Endurance: 104 or 105 Cycles - Data Retention: 10 Years 5V 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-wide Pinout Commercial and Industrial Temperature Ranges
* * * * * * *
64K (8K x 8) Parallel EEPROMs AT28C64 AT28C64X
Description
The AT28C64 is a low-power, high-performance 8,192 words by 8-bit nonvolatile electrically erasable and programmable read only memory with popular, easy-to-use features. The device is manufactured with Atmel's reliable nonvolatile technology. (continued)
Pin Configurations
Pin Name A0 - A12 CE OE WE I/O0 - I/O7 RDY/BUSY NC DC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs Ready/Busy Output No Connect Don't Connect TSOP Top View
OE A11 A9 A8 NC WE VCC RDY/BUSY (or NC) A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2
PDIP, SOIC Top View
RDY/BUSY (or NC) A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
LCC, PLCC Top View
A7 A12 RDY/BUSY (or NC) DC VCC WE NC I/O1 I/O2 VSS DC I/O3 I/O4 I/O5 14 15 16 17 18 19 20
A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 10 11 12 13
4 3 2 1 32 31 30
29 28 27 26 25 24 23 22 21
A8 A9 A11 NC OE A10 CE I/O7 I/O6
Rev. 0001H-12/99
Note: PLCC package pins 1 and 17 are DON'T CONNECT.
1
The AT28C64 is accessed like a Static RAM for the read or write cycles without the need for external components. During a byte write, the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of a write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. The device includes two methods for detecting the end of a write cycle, level detection of RDY/BUSY (unless pin 1 is N.C.) and DATA Polling of I/O7 . Once the end of a write
cycle has been detected, a new access for a read or write can begin. The CMOS technology offers fast access times of 120 ns at low power dissipation. When the chip is deselected the standby current is less than 100 A. Atmel's AT28C64 has additional features to ensure high quality and manufacturability. The device utilizes error correction internally for extended endurance and for improved data retention characteristics. An extra 32 bytes of EEPROM are available for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
2
AT28C64(X)
AT28C64(X)
Device Operation
READ: The AT28C64 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in a high impedance state whenever CE or OE is high. This dual line control gives designers increased flexibility in preventing bus contention. BYTE WRITE: Writing data into the AT28C64 is similar to writing into a Static RAM. A low pulse on the WE or CE input with OE high and CE or WE low (respectively) initiates a byte write. The address location is latched on the falling edge of WE (or CE); the new data is latched on the rising edge. Internally, the device performs a self-clear before write. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. FAST BYTE WRITE: The AT28C64E offers a byte write time of 200 s maximum. This feature allows the entire device to be rewritten in 1.6 seconds. READY/BUSY: Pin 1 is an open drain RDY/BUSY output that can be used to detect the end of a write cycle. RDY/BUSY is actively pulled low during the write cycle and is released at the completion of the write. The open drain connection allows for OR-tying of several devices to the same RDY/BUSY line. The RDY/BUSY pin is not connected for the AT28C64X. DATA POLLING: The AT28C64 provides DATA Polling to signal the completion of a write cycle. During a write cycle, an attempted read of the data being written results in the complement of that data for I/O 7 (the other outputs are indeterminate). When the write cycle is finished, true data appears on all outputs. WRITE PROTECTION: Inadvertent writes to the device are protected against in the following ways: (a) VCC sense - if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power on delay - once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before allowing a byte write; and (c) write inhibit - holding any one of OE low, CE high or WE high inhibits byte write cycles. CHIP CLEAR: The contents of the entire memory of the AT28C64 may be set to the high state by the CHIP CLEAR operation. By setting CE low and OE to 12 volts, the chip is cleared when a 10 msec low pulse is applied to WE. D E V I C E I DE NT I FI C A TI O N : A n e x t r a 3 2 b y t e s o f EEPROM memory are available to the user for device identification. By raising A9 to 12 0.5V and using address locations 1FE0H to 1FFFH the additional bytes may be written to or read from in the same manner as the regular memory array.
3
DC and AC Operating Range
AT28C64-12 Operating Temperature (Case) VCC Power Supply Com. Ind. 0C - 70C -40C - 85C 5V 10% AT28C64-15 0C - 70C -40C - 85C 5V 10% AT28C64-20 0C - 70C -40C - 85C 5V 10% AT28C64-25 0C - 70C -40C - 85C 5V 10%
Operating Modes
Mode Read Write
(2)
CE VIL VIL VIH X X X VIL
OE VIL VIH X
(1)
WE VIH VIL X VIH X X VIL
I/O DOUT DIN High Z
Standby/Write Inhibit Write Inhibit Write Inhibit Output Disable Chip Erase Notes: 1. X can be VIL or VIH. 2. Refer to AC programming waveforms. 3. VH = 12.0V 0.5V.
X VIL VIH VH
(3)
High Z High Z
DC Characteristics
Symbol ILI ILO ISB1 ISB2 Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL Condition VIN = 0V to VCC + 1V VI/O = 0V to VCC CE = VCC - 0.3V to VCC + 1.0V Com. CE = 2.0V to VCC + 1.0V f = 5 MHz; IOUT = 0 mA CE = VIL Ind. Com. Ind. Min Max 10 10 100 2 3 30 45 0.8 2.0 IOL = 2.1 mA = 4.0 mA for RDY/BUSY IOH = -400 A 2.4 0.45 Units A A A mA mA mA mA V V V V
ICC VIL VIH VOL VOH
VCC Active Current AC Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
4
AT28C64(X)
AT28C64(X)
AC Read Characteristics
AT28C64-12 Symbol tACC tCE
(1) (2)
AT28C64-15 Min Max 150 150 10 0 0 70 50
AT28C64-20 Min Max 200 200 10 0 0 80 55
AT28C64-25 Min Max 250 250 10 0 0 100 60 Units ns ns ns ns ns
Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE High to Output Float Output Hold from OE, CE or Address, whichever occurred first
Min
Max 120 120
tOE tDF
10 0 0
60 45
(3)(4)
tOH
AC Read Waveforms(1)(2)(3)(4)
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 20 ns
Pin Capacitance
f = 1 MHz, T = 25C(1)
Symbol CIN COUT Note: Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
1. This parameter is characterized and is not 100% tested.
5
AC Write Characteristics
Symbol tAS, tOES tAH tWP tDS tDH, tOEH tCS, tCH tDB tWC Parameter Address, OE Setup Time Address Hold Time Write Pulse Width (WE or CE) Data Setup Time Data, OE Hold Time CE to WE and WE to CE Setup and Hold Time Time to Device Busy AT28C64 Write Cycle Time (option available) AT28C64E 200 s Min 10 50 100 50 10 0 50 1 1000 Max Units ns ns ns ns ns ns ns ms
AC Write Waveforms
WE Controlled
CE Controlled
6
AT28C64(X)
AT28C64(X)
Data Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay
(2)
Min 10 10
Typ
Max
Units ns ns ns
Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See "AC Read Characteristics".
0
ns
Data Polling Waveforms
Chip Erase Waveforms
tS = tH = 1 sec (min.) tW = 10 msec (min.) VH = 12.0 0.5V
7
8
AT28C64(X)
AT28C64(X)
AT28C64 Ordering Information
tACC (ns) 120 ICC (mA) Active 30 Standby 0.1 Ordering Code AT28C64(E)-12JC AT28C64(E)-12PC AT28C64(E)-12SC AT28C64(E)-12TC AT28C64(E)-12JI AT28C64(E)-12PI AT28C64(E)-12SI AT28C64(E)-12TI AT28C64(E)-15JC AT28C64(E)-15PC AT28C64(E)-15SC AT28C64(E)-15TC AT28C64(E)-15JI AT28C64(E)-15PI AT28C64(E)-15SI AT28C64(E)-15TI AT28C64(E)-20JC AT28C64(E)-20PC AT28C64(E)-20SC AT28C64(E)-20TC AT28C64(E)-20JI AT28C64(E)-20PI AT28C64(E)-20SI AT28C64(E)-20TI AT28C64(E)-25JC AT28C64(E)-25PC AT28C64(E)-25SC AT28C64(E)-25TC AT28C64(E)-25JI AT28C64(E)-25PI AT28C64(E)-25SI AT28C64(E)-25TI Package 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T Operation Range Commercial (0C to 70C)
45
0.1
Industrial (-40C to 85C)
150
30
0.1
Commercial (0C to 70C)
45
0.1
Industrial (-40C to 85C)
200
30
0.1
Commercial (0C to 70C)
45
0.1
Industrial (-40C to 85C)
250
30
0.1
Commercial (0C to 70C)
45
0.1
Industrial (-40C to 85C)
Package Type 32J 28P6 28S 28T 32-lead, Plastic J-leaded Chip Carrier (PLCC) 28-lead, 0.600" Wide, Plastic Dull Inline Package (PDIP) 28-lead, 0.300" Wide, Plastic Gull Wing, Small Outline (SOIC) 28-lead, Plastic Thin Small Outline Package (TSOP) Options Blank E Standard Device: Endurance = 10K Write Cycles; Write Time = 1 ms High Endurance Option: Endurance = 100K Write Cycles; Write Time = 200 s
9
AT28C64X Ordering Information
tACC (ns) 150 ICC (mA) Active 30 Standby 0.1 Ordering Code AT28C64X-15JC AT28C64X-15PC AT28C64X-15SC AT28C64X-15TC AT28C64X-15JI AT28C64X-15PI AT28C64X-15SI AT28C64X-15TI AT28C64X-20JC AT28C64X-20PC AT28C64X-20SC AT28C64X-20TC AT28C64X-20JI AT28C64X-20PI AT28C64X-20SI AT28C64X-20TI AT28C64X-25JC AT28C64X-25PC AT28C64X-25SC AT28C64X-25TC AT28C64X-25JI AT28C64X-25PI AT28C64X-25SI AT28C64X-25TI Package 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T Operation Range Commercial (0C to 70C)
45
0.1
Industrial (-40C to 85C)
200
30
0.1
Commercial (0C to 70C)
45
0.1
Industrial (-40C to 85C)
250
30
0.1
Commercial (0C to 70C)
45
0.1
Industrial (-40C to 85C)
Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers AT28C64 X AT28C64 X AT28C64 X AT28C64 X Speed 12 15 20 25 Package and Temperature Combinations JC, JI, PC, PI, SC, SI, TC, TI JC, JI, PC, PI, SC, SI, TC, TI JC, JI, PC, PI, SC, SI, TC, TI JC, JI, PC, PI, SC, SI, TC, TI
Die Products
Reference Section: Parallel EEPROM Die Products
Package Type 32J 28P6 28S 28T 32-lead, Plastic J-leaded Chip Carrier (PLCC) 28-lead, 0.600" Wide, Plastic Dull Inline Package (PDIP) 28-lead, 0.300" Wide, Plastic Gull Wing, Small Outline (SOIC) 28-lead, Plastic Thin Small Outline Package (TSOP)
10
AT28C64(X)
AT28C64(X)
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
28P6, 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AB
.045(1.14) X 45
PIN NO. 1 IDENTIFY
.025(.635) X 30 - 45 .012(.305) .008(.203) .530(13.5) .490(12.4) .021(.533) .013(.330)
1.47(37.3) 1.44(36.6)
PIN 1
.032(.813) .026(.660)
.553(14.0) .547(13.9) .595(15.1) .585(14.9)
.566(14.4) .530(13.5)
1.300(33.02) REF
.090(2.29) MAX .005(.127) MIN
.050(1.27) TYP
.300(7.62) REF .430(10.9) .390(9.90) AT CONTACT POINTS
.030(.762) .015(.381) .095(2.41) .060(1.52) .140(3.56) .120(3.05)
.220(5.59) MAX SEATING PLANE .161(4.09) .125(3.18) .110(2.79) .090(2.29) .065(1.65) .041(1.04) .630(16.0) .590(15.0) 0 REF 15 .690(17.5) .610(15.5)
.065(1.65) .015(.381) .022(.559) .014(.356)
.022(.559) X 45 MAX (3X) .453(11.5) .447(11.4) .495(12.6) .485(12.3)
.012(.305) .008(.203)
28S, 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) Dimensions in Inches and (Millimeters)
28T, 28-lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches)*
INDEX MARK AREA 11.9 (0.469) 11.7 (0.461) 13.7 (0.539) 13.1 (0.516)
0.55 (0.022) BSC 7.15 (0.281) REF 8.10 (0.319) 7.90 (0.311)
0.27 (0.011) 0.18 (0.007)
1.25 (0.049) 1.05 (0.041)
0.20 (0.008) 0.10 (0.004) 0 5 REF 0.20 (0.008) 0.15 (0.006)
0.70 (0.028) 0.30 (0.012)
*Controlling dimension: millimeters
11
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(c) Atmel Corporation 1999. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life suppor t devices or systems. Marks bearing
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