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| Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET FEATURES * 'Trench' technology * Very low on-state resistance * Fast switching * Stable off-state characteristics * High thermal cycling performance * Low thermal resistance PHP45N03LT SYMBOL d QUICK REFERENCE DATA VDSS = 30 V ID = 45 A g RDS(ON) 24 m (VGS = 5 V) RDS(ON) 21 m (VGS = 10 V) s GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using 'trench' technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHP45N03LT is supplied in the SOT78 (TO220AB) conventional leaded package. PINNING PIN 1 2 3 tab gate drain source drain DESCRIPTION SOT78 (TO220AB) tab 1 23 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR VGS ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 k Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 30 30 15 45 36 180 86 175 UNIT V V V A A A W C THERMAL RESISTANCES SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS in free air TYP. 60 MAX. 1.75 UNIT K/W K/W November 1997 1 Rev 1.200 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET STATIC CHARACTERISTICS Tj= 25C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C VDS = 30 V; VGS = 0 V; VGS = 5 V; VDS = 0 V VGS = 5 V; ID = 25 A VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175C Tj = 175C MIN. 30 27 1 0.5 - PHP45N03LT TYP. 1.5 0.05 10 20 16 - MAX. 2 2.3 10 500 100 24 21 45 UNIT V V V V A A nA m m m DYNAMIC CHARACTERISTICS Tj = 25C unless otherwise specified SYMBOL gfs Qg(tot) Qgs Qgd Ciss Coss Crss td on tr td off tf Ld Ld Ls PARAMETER Forward transconductance Total gate charge Gate-source charge Gate-drain (Miller) charge Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance CONDITIONS VDS = 25 V; ID = 25 A ID = 40 A; VDD = 24 V; VGS = 5 V MIN. 8 TYP. 16 23 3 12 2000 380 250 30 80 95 40 3.5 4.5 7.5 MAX. 2500 450 300 45 130 135 55 UNIT S nC nC nC pF pF pF ns ns ns ns nH nH nH VGS = 0 V; VDS = 25 V; f = 1 MHz VDD = 15 V; ID = 25 A; VGS = 5 V; RG = 5 Resistive load Measured from contact screw on tab to centre of die Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 40 A; VGS = 0 V IF = 40 A; -dIF/dt = 100 A/s; VGS = -10 V; VR = 25 V TYP. 0.95 1.0 52 0.08 MAX. 45 180 1.2 UNIT A A V ns C November 1997 2 Rev 1.200 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET AVALANCHE LIMITING VALUE SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 25 A; VDD 25 V; VGS = 10 V; RGS = 50 ; Tmb = 25 C MIN. - PHP45N03LT TYP. - MAX. 60 UNIT mJ November 1997 3 Rev 1.200 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET PHP45N03LT 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating 10 Zth j-mb / (K/W) D= 7528-30 1 0.5 0.2 0.1 0.1 0.05 0.02 0 0 20 40 60 80 100 Tmb / C 120 140 160 180 P D tp D= tp T t 0.01 1E-07 T 1E-05 1E-03 t/s 1E-01 1E+01 Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb) ID% Normalised Current Derating Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T ID / A 10 6 60 VGS / V = 40 3.5 4 5 120 110 100 90 80 70 60 50 40 30 20 10 0 80 9528-30 4.5 20 3 2.5 0 20 40 60 80 100 Tmb / C 120 140 160 180 0 0 2 4 VDS / V 6 8 10 Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS RDS(ON) / mOhm 4 9528-30 4.5 1000 ID / A 7528-30 40 100 RD S(O = N) VD S/ ID tp = 10 us 100 us 30 5 6 20 VGS / V = 10 10 10 DC 1 ms 10 ms 1 1 10 VDS / V 100 0 0 20 40 ID / A 60 80 Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS November 1997 4 Rev 1.200 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET PHP45N03LT 60 50 ID / A 9528-30 2.5 VGS(TO) / V max. BUK959-60 2 Tj / C = 25 40 175 typ. 1.5 30 1 min. 20 10 0 0.5 0 1 2 3 VGS / V 4 5 6 0 -100 -50 0 50 Tj / C 100 150 200 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj gfs / S 9528-30 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Sub-Threshold Conduction 25 1E-01 20 Tj / C = 25 15 175 1E-02 2% typ 98% 1E-03 10 1E-04 5 1E-05 0 0 10 20 30 ID / A 40 50 60 1E-05 0 0.5 1 1.5 2 2.5 3 Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID); conditions: VDS = 25 V a 2 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS C / pF 30V TrenchMOS 10000 9528-30 1.5 Ciss 1 1000 0.5 Coss Crss 0 -100 -50 0 50 Tj / C 100 150 200 100 0.1 1 VDS / V 10 100 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 25 A; VGS = 5 V Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz November 1997 5 Rev 1.200 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET PHP45N03LT 5 VGS / V 9528-30 120 110 100 90 80 70 60 50 40 30 20 10 0 WDSS% 4 VDS / V = 6 24 3 2 1 0 0 5 10 QG / nC 15 20 25 20 40 60 80 100 120 Tmb / C 140 160 180 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 40 A; parameter VDS IF / A 9528-30 Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 25 A 60 50 40 30 20 10 0 + L VDS Tj / C = 175 25 VDD VGS 0 RGS T.U.T. -ID/100 R 01 shunt 0 0.5 1 VSDS / V 1.5 2 Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj Fig.16. Avalanche energy test circuit. 2 WDSS = 0.5 LID BVDSS /(BVDSS - VDD ) + RD VDS VGS 0 RG T.U.T. VDD - Fig.17. Switching test circuit. November 1997 6 Rev 1.200 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET MECHANICAL DATA Dimensions in mm Net Mass: 2 g PHP45N03LT 4,5 max 10,3 max 1,3 3,7 2,8 5,9 min 15,8 max 3,0 max not tinned 3,0 13,5 min 1,3 max 1 2 3 (2x) 2,54 2,54 0,9 max (3x) 0,6 2,4 Fig.18. SOT78 (TO220AB); pin 2 connected to mounting base. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT78 (TO220) envelopes. 3. Epoxy meets UL94 V0 at 1/8". November 1997 7 Rev 1.200 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET DEFINITIONS Data sheet status Objective specification Product specification Limiting values PHP45N03LT This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1997 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. November 1997 8 Rev 1.200 |
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