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LH543620
FEATURES * Fast Cycle Times: 20/25/30 ns * Selectable 36/18/9-Bit Word Width for Both Input Port and Output Port * Byte-Order-Reversal Function (i.e., `Big-Endian' `Little-Endian' Conversion) * 16-mA-IOL Three-State Outputs * Automatic Byte Parity Checking * Selectable Byte Parity Generation * Five Status Flags: Full, Almost-Full, Half-Full, Almost-Empty, and Empty * All FIFO Status Flags are Synchronous (AE, HF, AF Through Programming of Control Register) * Programmed Values may be entered from either Port * Two Enable Control Signals for each Port * Mailbox Register with Synchronized Flags * Asynchronous Data-Bypass Function * `Smart' Data-Retransmit Function * Configurable for Paralleled FIFO Operation (72-Bit Data Width) * Space-Saving PQFP and TQFP Packages
1
1024 x 36 Synchronous FIFO
FUNCTIONAL DESCRIPTION
The LH543620 is a FIFO (First-In, First-Out) memory device, based on fully-static CMOS RAM technology, capable of containing up to 1024 36-bit words. It can replace four or more nine-bit-wide FIFOs in many applications. The input port and the output port operate independently of each other. Write operations are performed on the rising edge of the input clock CKI, and enabled by two enabled signals ENI1, ENI2. Read operations are performed on the rising edge of the output clock CKO and enabled by two enabled signals ENO1, ENO2. Five status flags are available to monitor the memory array status: Full, Almost-Full, Half-Full, Almost-Empty, and Empty. The Almost-Full and Almost-Empty flags are initialized to a default offset of eight locations from their respective boundaries, but they are each programmable over the entire FIFO depth. Both the input port and the output port may be set independently to operate at three data-word widths: 36 bits, 18 bits, or 9 bits. This setting may be changed during system operation. The LH543620 can perform Byte-Order-Reversal on the four nine-bit bytes of each 36-bit data word passing through it, thus accomplishing `Big Endian' `Little Endian' conversion. When data is read out of the FIFO a byte-parity check is performed. The parity flag is used to indicate that a parity error was detected in one of the 9-bit bytes of the output word. Parity generation, when selected, creates the parity bit of each 8-bit byte of the input word. The result is written into the MSB-bit of each 9-bit byte, overwriting the previous contents of the bit. The default is odd parity. However, the FIFO may be programmed to use even parity. The LH543620 has a data-bypass mode that connects the output port to the input port asynchronously. A mailbox facility with Synchronized Flags is provided from the input port to the output port. The LH543620's `Smart-Retransmit' capability sets the internal-memory read pointer to any arbitrary memory location. The `Smart-Retransmit' capability includes a Marking Function and a Programmable Offset to support data communication and digital signal processing applications.
* PQFP-to-PGA Package Conversion
2
1. This is a final data sheet; except that all references to the TQFP package have Preliminary status. 2. For PQFP-to-PGA conversion for thru-hole board designs, Sharp recommends ITT Pomona Electronics' SMT/PGA Generic Converter model #5853(R). This converter maps the LH543620 132pin PQFP to a generic 13 x 13, 132-pin PGA (100-mil pitch). For more information, contact Sharp or ITT Pomona Electronics at 1500 East Ninth Street, Pomona, CA 91766, (909) 469-2900.
1
2
EF AE BUS SWITCHING (DEFUNNELING) PARITY CHECK PF FIFO MEMORY ARRAY 1024 x 36 WRITE POINTER READ POINTER STATUS FLAGS OUTPUT PORT LOGIC ENO1 ENO2 WSO0 WSO1 CKO MAILBOX MEF PARITY GENERATOR BUS SWITCHING (FUNNELING) RESOURCE REGISTERS CONTROL MUX RETRANSMIT LOGIC RESOURCE REGISTER OUTPUT LOGIC ADO0 ADO1 ADO2 MUX AE OFFSET AF OFFSET RT OFFSET RT BASE PARITY RT RTMD0 RTMD1 OUTPUT PORT INPUT BUFFER 16 (Q [15:0]) OE MUX OUTPUT PORT OUTPUT BUFFER Q[35:0] BYE
543620-6
LH543620
FF AF HF
ENI1 ENI2 WSI0 WSI1
INPUT PORT LOGIC
CKI
MFF
ADI0 ADI1 ADI2
RESOURCE REGISTER INPUT LOGIC
Figure 1. LH543620 Block Diagram
CAPR
D[35:0]
INPUT PORT
1024 x 36 Synchronous FIFO
RS
RESET LOGIC
1024 x 36 Synchronous FIFO
LH543620
PIN DESCRIPTIONS (SUMMARY)
PIN NAME PIN TYPE * DESCRIPTION PIN NAME PIN TYPE * DESCRIPTION
DATABUS D[35:0] Q[15:0] Q[35:16] CKI CKO RS OE BYE CAPR I I/O/Z O/Z I I I I I I 36-Bit Input-Port Databus Three-State 36-Bit OutputPort Databus CLOCKS Input-Port Clock Output-Port Clock Master Reset Output Enable Data-Bypass Enable Command-Address Port Reference AE EF PF MEF VCC VSS
CONTROL SIGNALS SYNCHRONOUS TO THE OUTPUT CLOCK ENO1,ENO2 ADO[2:0] WSO[1:0] RTMD[1:0] RT I I I I I Output-Port Enables Output-Port Address Output-Port Word-Width Selection Retransmit Mode Control Retransmit
ASYNCHRONOUS CONTROL
STATUS FLAGS SYNCHRONOUS TO THE OUTPUT CLOCK O O O O V V Almost-Empty Flag Empty Flag Parity-Error Flag Mailbox-Empty Flag Positive Power Ground
CONTROL SIGNALS SYNCHRONOUS TO THE INPUT CLOCK ENI1,ENI2 ADI[2:0] WSI[1:0] I I I Input-Port Enables Input-Port Address Input-Port Word-Width Selection
VOLTAGES AND GROUNDS
STATUS FLAGS SYNCHRONOUS TO THE INPUT CLOCK FF AF HF
1
O O O O
Full Flag Almost-Full Flag Half-Full Flag Mailbox-Full Flag
MFF
* I = Input, O = Output, V = Voltage, Z = High-Impedance 1. The half-full flag is user-selectable to be synchronized to either CKI or CKO.
3
LH543620
1024 x 36 Synchronous FIFO
PIN CONNECTIONS
132-PIN PQFP
VCC D0 D1 D2 D3 D4 D5 D6 D7 D8 VSS D9 D10 D11 D12 D13 D14 D15 D16 D17 VCC CKI D18 D19 D20 D21 D22 D23 D24 D25 D26 VSS D27 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Pin 1 Pin 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
MEF MFF EF AE VSS HF AF FF PF CKO VCC Q35 Q34 VSS Q33 Q32 VCC Q31 Q30 VSS Q29 Q28 VCC Q27 Q26 VSS Q25 Q24 VCC Q23 Q22 VSS VSS 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84
CHAMFERED EDGE
TOP VIEW
D28 D29 D30 D31 D32 D33 D34 D35 VCC ENI1 ENI2 ADI0 ADI1 ADI2 WSI0 WSI1 VSS CAPR BYE ENO1 ENO2 ADO0 ADO1 ADO2 VCC WSO0 WSO1 RS RTMD0 RTMD1 RT OE VCC
VCC Q21 Q20 VCC Q19 Q18 VSS Q17 Q16 VCC Q15 Q14 VSS Q13 Q12 VCC Q11 Q10 VSS Q9 Q8 VCC Q7 Q6 VSS Q5 Q4 VCC Q3 Q2 VSS Q1 Q0
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
543620-4
Figure 2. Pin Connections for 132-Pin PQFP Package (Top View)
4
1024 x 36 Synchronous FIFO
LH543620
PIN LIST
PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO.
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MEF MFF EF AE HF AF FF PF CKO Q35 Q34 Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 Q17 Q16
1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 18 19 20 21 23 24 25 26 27 29 30 32 33 35 36 38 39 41 42 44 45 47 48 52 53 55 56 58 59
Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 OE RT RTMD1 RTMD0 RS WSO1 WSO0 ADO2 ADO1 ADO0 ENO2 EN01 BYE CAPR WSI1 WSI0 ADI2 ADI1 ADI0 ENI2 ENI1 D35 D34 D33 D32 D31 D30 D29
61 62 64 65 67 68 70 71 73 74 76 77 79 80 82 83 85 86 87 88 89 90 91 93 94 95 96 97 98 99 101 102 103 104 105 106 107 109 110 111 112 113 114 115
D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 CKI D17 D16 D15 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC VSS VCC VSS VCC
116 117 119 120 121 122 123 124 125 126 127 128 130 131 132 7 17 22 28 31 34 37 40 43 46 49 50 51 54 57 60 63 66 69 72 75 78 81 84 92 100 108 118 129
5
LH543620
1024 x 36 Synchronous FIFO
ABSOLUTE MAXIMUM RATINGS 1
PARAMETER RATING
Supply Voltage to VSS Potential Signal Pin Voltage to VSS Potential 2 DC Output Current
3
-0.5 V to 7 V -0.5 V to VCC + 0.5 V 75 mA -65oC to 150oC 2.5 Watts (Quad Flat Pack)
Storage Temperature Range Power Dissipation (Package Limit)
NOTES: 1. Stresses greater than those listed under `Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions outside those indicated in the `Operating Range' of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Negative undershoot of 1.5 V in amplitude is permitted for up to 10 ns, once per cycle. 3. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time.
OPERATING RANGE
SYMBOL PARAMETER MIN MAX UNIT oC
TA VCC VSS VIL VIH
Temperature, Ambient Supply Voltage Supply Voltage Logic LOW Input Voltage Logic HIGH Input Voltage
1
0 4.5 0 -0.5 2.2
70 5.5 0 0.8 Vcc + 0.5
V V V V
NOTE: 1. Negative undershoot of 1.5 V in amplitude is permitted for up to 10 ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ILI ILO VOL VOH ICC ICC2
Input Leakage Current I/O Leakage Current Logic LOW Output Voltage Logic HIGH Output Voltage Average Supply Current
1,2
VCC = 5.5 V, VIN = 0 V To VCC OE VIH, 0 V VOUT VCC IOL = 16.0 mA IOH = -8.0 mA Measured at fC = maximum All Inputs = VIHMIN (Clock idle) All Inputs = VCC, Outputs - open, Control - deasserted, Clocks = V CC
-10 -10
10 10 0.4
A A V V
2.4 205 40 380 85
mA mA
Average Standby Supply Current 1,3 Power-Down Supply Current 1
ICC3
0.01
1.0
mA
NOTE: 1. ICC, ICC2, and ICC3 are dependent upon actual output loading, and ICC is also dependent on cycle times. Specified values are with outputs open (for ICC: CL = 0 pF); and, for ICC, operating at minimum cycle times. 2. ICC (MAX): Using worst case conditions and data pattern. ICC (TYP): Using VCC = 5 V and average data pattern. 3. ICC2 (TYP): Using VCC = 5 V and TA = 25C.
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1024 x 36 Synchronous FIFO
LH543620
AC TEST CONDITIONS
PARAMETER RATING
Input Pulse Levels Input Rise and Fall Times (10% to 90%) Output Reference Levels Input Timing Reference Levels Output Load, Timing Tests
VSS to 3 V 3 ns 1.5 V 1.5 V Figure 3
DEVICE UNDER TEST
+5 V 1.1 k
680
30 pF *
CAPACITANCE 1,2
PARAMETER RATING
CIN MAX. (Input Capacitance) COUT MAX. (Output Capacitance)
NOTES: 1. Sample tested only. 2. Capacitances are maximum values at 25oC, measured at 1.0 MHz, with VIN = 0 V.
8 pF 10 pF
* INCLUDES JIG AND SCOPE CAPACITANCES
Figure 3. Output Load Circuit
543620-27
7
LH543620
1024 x 36 Synchronous FIFO
AC ELECTRICAL CHARACTERISTICS 1 (See Timing Diagrams Pages 21-35)
SYMBOL DESCRIPTION MIN -20 MAX MIN -25 MAX MIN -30 MAX UNIT
fC tC tCH tCL tDS tDSO tDH tDHO tA tOH tES tEH tOES tOEH tOL tOZ tOE tEF tFF tAE tAF tHF tPF tMFF tMEF tAS tAH tWSS tWSH tRTMS tRTMH tRTS tRTH tRS tRSR tRF tRO tBA tBD tSKEW1 tSKEW2 tSKEWM
NOTES:
Clock Cycle Frequency Clock Cycle Time Clock HIGH Time Clock LOW Time Data In Setup Time Data Setup Time When Writing to Resource Register From Output Port Data In Hold Time Data Hold Time When Writing to Resource Register From Output Port Data Out Access Time Data Out Hold Time Enable Setup Time Enable Hold Time Output Enable Setup Time Output Enable Hold Time OE to Data Out Low-Z 2 OE to Data Out High-Z 2 OE to Data Valid Empty Flag Access Time Full Flag Access Time AE Flag Access Time AF Flag Access Time HF Flag Access Time Parity Flag Access Time Mailbox FF Access Time Mailbox EF Access Time Address Setup Time Address Hold Time WSI and WSO Setup Time WSI and WSO Hold Time Retransmit Mode Setup Time Retransmit Mode Hold Time Retransmit Setup Time Retransmit Hold Time Reset Pulse Width Reset Recovery Time
2
50 20 8 9 5 10 2 2 14 4 5 2 6 2 1 12 10 14 14 14 14 14 14 14 14 10 2 10 2 5 2 5 2 20 10 30 18 12 12 7 7 7 9 9 9
4
40 25 10 12 6 12 2 2 16 4 6 2 7 2 1 15 12 16 16 16 16 16 16 16 16 12 2 12 2 6 2 6 2 25 12 35 20 16 16 11 11 11 14 2 14 2 7 2 7 2 30 15 4 7 2 8 2 1 30 12 14 7 14 2 2
33
MHz ns ns ns ns ns ns ns
18
ns ns ns ns ns ns ns
19 14 18 18 18 18 18 18 18 18
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Reset LOW to Flag Valid Reset to Data Out LOW Bypass LOW to Data Valid Bypass Propagation Delay Skew Time Between CKO and CKI for FF 3 Skew Time Between CKI and CKO for EF Skew Time Between Clock for Mailbox Flags
40 22 18 18
ns ns ns ns ns ns ns
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1024 x 36 Synchronous FIFO
LH543620
PIN DESCRIPTIONS (FUNCTIONAL)
PIN NAME DESCRIPTION
DATABUS 36-bit Input-Port Databus. The D port is the input port for the FIFO memory array, the resource registers, and the mailbox, or it may be directly connected to the output port. See Figure 4. D[35:0] is synchronous to the rising edge of CKI. Three-State 36-Bit Output-Port Databus. The Q port is the output port for the FIFO memory array, the resource registers, and the mailbox, or it may be directly connected to the input port. See Figure 4. Q[35:0] is synchronous to the rising edge of CKO. The lower 16 bits of the Q port (Q[15:0]) may also be used as the input port for the resource register. CLOCKS CKI Input-Port Clock. CKI is a free-running waveform controlled by an oscillator. It may be irregular or asynchronous if minimum clock-HIGH times and clock-LOW times are met. Output-Port Clock. CKO is a free-running waveform controlled by an oscillator. It may be irregular or asynchronous if minimum clock-HIGH times and clock-LOW times are met.
D[35:0]
Q[35:0]
CKO
INPUT PORT
SELECT INPUT PORT FUNCTION
OUTPUT PORT
SELECT OUTPUT PORT FUNCTION
ADI [2:0] =
MAILBOX RESOURCE REGISTER
ADO [2:0] =
MAILBOX RESOURCE REGISTER
D MAILBOX MFF = L MEF = H L CAPR H IDLE
MAILBOX Q MFF = H MEF = L L OE H
D RESOURCE REGISTER (ADI)
RESOURCE REGISTER (ADO) Q L CAPR H
IDLE
Q RESOURCE REGISTER (ADO)
* All the operations are synchronized to CKI, except MEF is set HIGH on CKO.
* All the operations are synchronized to CKO, except MFF is set HIGH on CKI.
543620-5
Figure 4. Resource Registers, Read and Write
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LH543620
1024 x 36 Synchronous FIFO
PIN NAME
DESCRIPTION
ASYNCHRONOUS CONTROL RS Master Reset. When asserted LOW, the LH543620 internal resource registers are set to their default value. See Table 1. The status flags indicate Empty FIFO. Output Enable. When asserted LOW, OE forces Q[35:0] to be active. When deasserted HIGH, OE forces Q[35:0] into a Hi-Z state. Bit 6 of the control register governs whether OE suppresses the advancement of the Read Pointer (RP). In this case, OE must obey setup time and hold time relative to CKO. Data-Bypass Enable. When asserted LOW, BYE connects Q[35:0] directly to D[35:0]. Command-Address Port Reference. CAPR determines the source of the 16-bit word to be loaded into the resource register. Whenever CAPR is LOW, the word comes from the Input Port. Whenever CAPR is HIGH (OE is HIGH), the word comes from the Output Port. NOTES: 1. The destination of the resource register is always the Output Port. 2. CAPR is assumed to be a steady signal. It is not allowed to change `on-the-fly' during operation. CONTROL SIGNALS SYNCHRONOUS TO THE INPUT CLOCK Input-Port Enables. ENI1 and ENI2 are active HIGH and synchronous to the rising edge of CKI. Data is written into the FIFO memory array when both ENI1 and ENI2 are asserted HIGH. NOTE: ENI1, ENI2 DO NOT ENABLE writing data into the Resource Registers or the Mailbox. Input-Port Address. ADI[2:0] specifies the Input-Port destination. See Table 1. ADI[2:0] is synchronized to the rising edge of CKI. Input-Port Word-Width Selection. WSI[1:0] selects the Input-Port Word-Width. See Table 2. WSI[1:0] is synchronous to the rising edge of CKI.
OE
BYE
CAPR
ENI1, ENI2
ADI[2:0]
WSI[1:0]
Table 1. Input-Port Address
ADI2 ADI1 ADI0 SELECTION DEFAULT VALUE (of the selected REGISTER) WSI1
Table 2. Input-Port Word-Width Selection
WSI 0 FUNCTION
L L H H
L H L H
L L L L H H H H
L L H H L L H H
L H L H L H L H
RBASE register ROFFSET register AF offset value Parity register AE offset value Control register Mailbox Resource registers write disabled
0 0 8 0 8 1 0
9-Bit Data-Path Width 18-Bit Data-Path Width Reserved 36-Bit Data-Path Width
Input data D[8:0] Input data D[17:0]
Input data D[35:0]
10
1024 x 36 Synchronous FIFO
LH543620
PIN NAME
DESCRIPTION
STATUS FLAGS SYNCHRONOUS TO THE INPUT CLOCK Full Flag. FF is synchronous to the rising edge of CKI. When asserted LOW, 1024 36-bit words of the FIFO memory array contain meaningful data. When FF is asserted, writing data to the FIFO is disabled. Almost-Full Flag. When asserted LOW, AF indicates that there are at most `p' vacant 36-bit words remaining in the FIFO memory array, where `p' is the value of the Almost-Full-Offset-Value. AF has two synchronization modes depending on Bit 5 of the control register. Bit 5 = 0 (Default) Asynchronous Mode Bit 5 = 1: AF is synchronous to the rising edge of CKI. Half-Full Flag. When asserted LOW, there are at least 513 36-bit words in the FIFO memory array. HF has three synchronization modes depending on Bits 3 and 4 of the control register. See Table 3. Mailbox-Full Flag. MFF is synchronized to the rising edge of CKI. When asserted LOW, it indicates that a new mail word has been placed in the mailbox. CONTROL SIGNALS SYNCHRONOUS TO THE OUTPUT CLOCK Output-Port Enables. ENO1 and ENO2 are active HIGH, synchronous to the rising edge of CKO. Data is read from the FIFO memory array when both ENO1, ENO2 are asserted. NOTE: ENO1, ENO2 DO NOT ENABLE reading data from the Resource Register or the Mailbox. Output-Port Address. ADO[2:0] specifies the Output-Port source/destination. See Table 4. ADO[2:0] is synchronous to the rising edge of CKO. NOTE: In order to read the resource register at the output bus, BYE should be deasserted and the FIFO memory array should be disabled.
FF
AF
HF
MFF
ENO1, ENO2
ADO[2:0]
Table 3. HF Synchronization Modes
CONTROL REGISTER BIT 4 BIT 3 FUNCTION ADO2
Table 4. Output-Port Address
ADO1 ADO0 SELECTION DEFAULT VALUE (of the selected REGISTER)
L* L H H
L* H L H
Asynchronous Mode: HF Synchronous Mode I: HF is synchronous to the rising edge of CKO Synchronous Mode II: HF is synchronous to the rising edge of CKI
L L L L H H H H
L L H H L L H H
L H L H L H L H
RBASE register ROFFSET register AF offset value Parity register AE offset value Control register Mailbox Resource registers read disabled
0 0 8 0 8 1 0 Not applicable
* Default Mode
11
LH543620
1024 x 36 Synchronous FIFO
PIN NAME
DESCRIPTION
CONTROL SIGNALS SYNCHRONOUS TO THE OUTPUT CLOCK (cont'd) Output-Port Word-Width Selection. WSO[1:0] is synchronous to the rising edge of CKO. WSO[1:0] selects the Output-Port Word-Width and controls byte-order-reversal according to Table 5. Retransmit Mode Control. RTMD[1:0] is synchronized to the rising edge of CKO. RTMD[1:0] controls the placement of new contents into the Read Pointer (RP) and/or the Retransmit Base (RBASE) registers. Whenever Retransmit (RT) is asserted, one of three operations is performed according to the setting of RTMD[1:0]. See Table 6. NOTES: 1. When RTMD[1:0] is set to 0, the FIFO is in depth cascade mode, and the Retransmit mechanism can not be used. In cascade mode, the Almost-Empty Flag is a handshake signal for cascading. The Almost-Empty Flag is used as an input to the ENI of the next FIFO in the chain. 2. In standard FIFO operation RTMD[1:0] must not be set to 0 and the Retransmit signal must be HIGH. Retransmit. RT is synchronized to the rising edge of CKO. When asserted LOW, RT causes one of the Retransmit Mode operations to be performed, according to the encoding of RTMD[1:0]. See Table 6. NOTE: When RTMD[1:0] = 0 (FIFO is in cascade mode) RT is ignored.
WSO[1:0]
RTMD[1:0]
RT
Table 5. Output-Port Word-Width Selection
WSO1 WSO0 FUNCTION RTMD1
Table 6. Retransmit Operation Modes
RTMD0 OPERATION ACTION TAKEN
L L
L H
9-Bit Data-Path Width 18-Bit Data-Path Width 36-Bit Data-Path Width With ByteOrder-Reversal 36-Bit Data-Path Width
Output data Q[8:0] Output data Q[17:0]
L
L
Depth Cascade Mode Retransmit
The Almost-Empty Flag is a handshake signal for cascading (RBASE) + (ROFFSET) RP (RBASE) + (ROFFSET) RP and (RBASE) + (ROFFSET) RBASE (RP) RBASE
L Output data Q[35:0] H
H
H
L
H
H
Output data Q[35:0]
L
Retransmit and Mark
H
H
Mark
12
1024 x 36 Synchronous FIFO
LH543620
PIN NAME
DESCRIPTION
STATUS FLAGS SYNCHRONOUS TO THE OUTPUT CLOCK Almost-Empty Flag. The AE flag has two modes of operation depending on the RTMD[1:0] setting. 1. RTMD[1:0] 0: AE is a standard Almost-Empty Flag. When asserted LOW, AE implies that there are at most `q' 36-bit words in the FIFO memory array, where `q' is Almost-Empty-OffsetValue register value. In this mode AE has two synchronization options depending on the setting of Bit 2 of the control register. Bit 2 = 0 (Default) Asynchronous Mode Bit 2 = 1 Synchronous Mode: AE is synchronous to the rising edge of CKO. 2. RTMD[1:0] = 0: AE is a handshake signal for cascading. Empty Flag. EF is synchronous to the rising edge of CKO. When asserted LOW, all 1024 36-bit words are vacant. When asserted, EF disables the FIFO Read operation. Parity-Error Flag. PF is synchronized to the rising edge of CKO. When asserted LOW, PF implies that a parity error has occurred in at least one 9-bit byte within a 36-bit word read from the FIFO memory array. If there are no errors, it is deasserted HIGH. When an error is detected, the parity check result of each 9-bit byte of the 36-bit output word is written to the parity register. The content of the parity register is frozen until read. The PF signal is delayed by one CKO cycle compared to the output data (i.e., if the PF is asserted, there was an error in the previous word). Mailbox-Empty Flag. MEF is synchronous to the rising edge of CKO. When asserted LOW, MEF indicates that there is no new mail word in the mailbox. VOLTAGES AND GROUNDS VCC VSS Positive Power. Ground.
AE
EF
PF
MEF
OPERATIONAL DESCRIPTION
The LH543620 has four operating modes: Normal Mode, Programmable Resource Registers, Mailbox, and Data Bypass. NORMAL MODE Normal FIFO operation refers to Read and Write operations to the FIFO memory array. Data Write operations into the FIFO memory array occur at the rising edge of
CKI. The operation is enabled if both ENI1 and ENI2 are asserted HIGH. Data Read operations from the FIFO memory occur at the rising edge of CKO. The operation is enabled if both ENO1 and ENO2 are asserted HIGH. The FIFO write and read operations are supported by the following mechanisms: Byte-Order-Reversal and Bus Funneling/Defunneling Functions, Status Flags, Retransmit Mechanism, Parity Checking, and Parity Generation.
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LH543620 Byte-Order-Reversal and Bus Funneling/ Defunneling Functions Word width can be selected at the Input Port and/or the Output Port to be 36, 18 or 9 bits wide. When the Output Port width is selected to be 36 bits, it is possible to select Byte-Order-Reversal. The funneling mechanism is controlled by the inputs WSI[1:0] and WSO[1:0] according to Tables 2 and 5. Data is packed and unpacked from a 36-bit word memory array. Table 7 describes all combinations of funneling/defunneling. Changes to the funneling/defunneling settings during system operation should be made one clock before a word boundary, as shown in Example 3.
1024 x 36 Synchronous FIFO
Example 2: 18-to-36 Defunneling With Byte Reversal
This example performs two functions: 1. 2. Bus width change Big Endian to Little Endian conversion
This configuration can be used for connecting the Intel 80286 to the Motorola 68040.
CONDITIONS WSI[1:0] WSO[1:0] RESULTS
1 -
- 2
Input 18 bits wide. Pins used are D[17:0]. Output 36 bits wide with byte order reversal.
Example 1: 36-to-9 Funneling
CONDITIONS WSI[1:0] WSO[1:0] RESULTS
The dataflow structure is illustrated by Figure 6.
3 -
- 0
Input 36 bits wide. Output 9 bits wide. Pins used are Q[8:0].
Example 3: Changing Input Bus Width From 9 to 36 During Operation
CKI WSI ACTION
The dataflow structure is illustrated by Figure 5.
0 1 2 3 4
0 0 0 3 3
Write 1st 9-bit byte Write 2nd 9-bit byte Write 3rd 9-bit byte Write 4th 9-bit byte Write 1st 36-bit word
Table 7. Bus Funneling/Defunneling *
INPUT CKI cycles WSI = 0 D[35:9] D[8:0] CKO cycles WSO = 3 Q[35:0] OUTPUT WSO = 2 Q[35:0] WSO = 1 Q[35:18] Q[17:0] WSO = 0 Q[35:9] Q[8:0]
0 1 2 3 4 5 6 7 8
xxx xxx xxx xxx xxx xxx xxx xxx xxx
WSI = 1 D[35:18]
B0 B1 B2 B3 B4 B5 B6 B7 B8
D[17:0]
0 1 2 3 4 5 6 7 8
B3 B7
B2 B1 B0 B6 B5 B4
B0 B1 B2 B3 B4 B5 B6 B7
B3 B2 B1 B0 B3 B1 B0 B3 B2 B0 B7 B6 B5 B4 B1 B5 B4 B7 B6 B2 B7
B2 B3 B0 B1 B6
B1 B2 B3 B0 B5
B0 B1 B2 B3 B4
WSO = 3 Q[35:0]
WSO = 2 Q[35:0]
WSO = 1 Q[35:18] Q[17:0]
WSO = 0 Q[35:9] Q[8:0]
0 1 2 3 4
xx xx xx xx xx
B1 B3 B5 B7 B9
WSI = 3 D[35:0]
B0 B2 B4 B6 B8
0 1 2 3 4
B3 B2 B1 B0 B0 B1 B2 B3 B3 B2 B7 B6 B5 B4 B4 B5 B6 B7 B1 B0 B7 B6 B5 B4
WSO = 3 Q[35:0] WSO = 2 Q[35:0]
B1 B3 B5 B7
B0 B3 B2 B0 B4 B1 B6 B2 B7
B2 B3 B0 B1 B6
Q[35:9]
B1 B2 B3 B0 B5
B0 B1 B2 B3 B4
Q[8:0]
WSO = 1 Q[35:18] Q[17:0]
WSO = 0
0 1
B3 B2 B1 B7 B6 B5
B0 B4
0 1
B3 B2 B1 B0 B0 B1 B2 B3 B3 B2 B7 B6 B5 B4 B4 B5 B6 B7 B1 B0 B7 B6 B5 B4
B1 B3 B5 B7
B0 B3 B2 B0 B4 B1 B6 B2 B7
B2 B3 B0 B1 B6
B1 B2 B3 B0 B5
B0 B1 B2 B3 B4
* NOTE: B0, B1, . . ., represent data bytes.
14
1024 x 36 Synchronous FIFO
LH543620
INPUT: WSI[1:0]=3
B3 BYTE #4 B7 BYTE #8
LH543620 D35 Q35
B3 BYTE #4
OUTPUT: WSO[1:0]=0
B0 B1 B2 BYTE #1 BYTE #2 BYTE #3
...
D27
B2 BYTE #3 B6 BYTE #7
D26
...
BYTE #8
Q27 Q26
B2 BYTE #3 B3 B0 B1 BYTE #4 BYTE #1 BYTE #2
...
D18
B1 BYTE #2 B5 BYTE #6
D17
...
BYTE #7
Q18 Q17
B1 BYTE #2 B2 B3 B0 BYTE #3 BYTE #4 BYTE #1
...
...
BYTE #6
D9
B0 BYTE #1 B4 BYTE #5
Q9 Q8
B0 BYTE #1 B1 B2 B3 BYTE #2 BYTE #3 BYTE #4
D8
...
D0
0
1 CKI
2
...
BYTE #5
Q0
0
1
2 CKO
3
4
NOTES: HEAVY SOLID LINES = Main data path. SHADED LINES = Not used for this application.
543620-30
Figure 5. Example of 36-to-9 Bus Funneling
INPUT: WSI[1:0]= 1
LH543620 D35 Q35
OUTPUT: WSO[1:0]= 2
B0 BYTE #1 B4 BYTE #5
...
D27 D26
...
Q27 Q26
NOT USED
...
...
Intel 80286
D18
B1 BYTE #2 B3 BYTE #4 B5 BYTE #6 B7 BYTE #8
Q18 Q17
B2 BYTE #3 B6 BYTE #7
D17
...
D9
B0 BYTE #1 B2 BYTE #3 B4 BYTE #5 B6 BYTE #7
D8
...
Q9 Q8
B3 BYTE #4 B7 BYTE #8
...
D0
0
1
2 CKI
3
4
...
Q0
0
1 CKO
2
NOTES: HEAVY SOLID LINES = Main data path. SHADED LINES = Not used for this application.
543620-31
Figure 6. Example of 18-to-36 Bus Defunneling With Byte Order Reversal
Motorola 68040
3
NOT USED
B1 BYTE #2
B5 BYTE #6
15
LH543620 Status Flags There are five status flags: FF Full Flag AF Almost-Full Flag HF Half-Full Flag AE Almost-Empty Flag EF Empty Flag The functionality and the synchronization of the status flags are detailed in the Pins Descriptions (Functional) section. All status flags are generated for 36-bit word widths, not according to selected input or output port widths. Retransmit Mechanism With standard FIFO operations, every data word can be read out of the FIFO once. The Retransmit mechanism allows reading the data more than once by providing flexible control of the Read Pointer. Associated with the Retransmit mechanism are three control lines: RTMD[1:0], RT, and two Resource registers: RBASE and ROFFSET. RTMD[1:0] sets the mode of operation. See Table 6. RT enables the operation synchronous to CKO. 5. 2. 3. 4. NOTES 1.
1024 x 36 Synchronous FIFO
The Retransmit mechanism can be used independently and parallel to the write operation. RTMD[1:0] must be selected two cycles prior to RT being asserted and remain stable during RT low. At least two words need to be in the FIFO memory array prior to performing a retransmit. When using normal read and write operations, the FF inhibits writing when the FIFO is full and the EF inhibits reading when the FIFO is empty. This behavior provides a protection from wraparound situations (i.e., the Read pointer is ahead of the Write Pointer). This protection is NOT provided when using retransmit. The user should be careful not to write more than 1024 words from the marked point. When the retransmit mechanism is not used, the recommended connection is: RTMD[1:0] = 3 RT = HIGH
The Retransmit mechanism can be useful in many applications. For example: 1. Computer-communications applications. When the receiver reads a block of data and finds no errors in the data block, it can mark the beginning of the new message by setting the FIFO in MARK mode RTMD[1:0] = 3 and assert the RT signal for one clock cycle. If the receiver finds an error in the data block, it can read the last message again by setting the FIFO in Retransmit mode RTMD[1:0] = 1 and asserting the RT signal for one cycle. 2. Overlap addressing for DSP applications. A typical DSP consists of A/D-FIFO-DSP. In many applications, the DSP needs to read a block of data where each block overlaps the previous block (like the overlap-and-save method for filtering.) The overlap addressing can be implemented by using the LH543620 with no additional hardware as follows: The FIFO is set to retransmit and mark mode: RTMD[1:0] = 2, the AF offset register is programmed to N = Block Size, and the ROFFSET register is programmed to (N - Overlap). The data is loaded into the FIFO each time CKin is triggered. The DSP can sense the AF flag of the FIFO. Whenever this flag is being asserted, a new block of data is available in the FIFO. The DSP then reads a block of data, and then asserts the FIFO's RT signal, which causes the RP and RBASE register to be set at the beginning of the new block.
Retransmit allows three modes of operation:
Mark: RTMD[1:0] = 3 and RT is asserted. The value of the Read Pointer is saved into the RBASE register. Retransmit: RTMD[1:0] = 1 and RT is asserted. The Read Pointer is loaded by the value of RBASE plus the value of ROFFSET. Retransmit and Mark: RTMD[1:0] = 2 and RT is asserted: The Read Pointer is loaded by the value of RBASE plus the value of ROFFSET. Then the value of the Read Pointer is saved into the RBASE register. The timing of the retransmit is illustrated in Figures 26 and 27. When RT is asserted and RTMD[1:0] is set to 1 or 2, the flags change their value to indicate a `Retransmit state', i.e., EF, AE, FF deasserted; AF, HF asserted. Three enable-read cycles are required to read the new data word. The flags reflect the new status. The retransmit is acknowledged even when the output is disabled (ENO = LOW), but enable-read cycles are needed to fill the pipeline with new information before reading the new data.
16
1024 x 36 Synchronous FIFO Parity Checking The Parity checking mechanism is always active. Parity checking is done separately for each of the 9-bit bytes of the 36-bit word read from the memory array. Toggling Bit 0 of the control register selects odd or even parity. When a parity error is detected in one or more bytes, the signal PF is asserted and the result of the individual parity checks are written to the parity register. See Example 3. To avoid a possible invalid PF signal, ENO1 and ENO2 should not be deasserted during the CLKO low time. The parity register is frozen until read. When read, the parity register is released and ready to store the next parity error data. Parity Generation After Reset, parity generation is not active. Parity generation is active only when Bit 1 of the control register is HIGH. The parity mechanism, when enabled, creates a parity bit for each of the bytes of the input word. The parity bit for each byte is created based on its 8 least significant bits of each 9-bit byte of the input-data word and on Bit 0 of the control register (it specifies odd or even parity). The result of the parity generation is written back to the MSB of the data byte. See Example 4.
LH543620 PROGRAMMABLE RESOURCE REGISTERS The LH543620 has six programmable resource registers. The resource registers may be loaded from either the Input Port or the Output Port. They can be read from the Output Port. The selection and loading or reading of the resource registers is controlled by ADI, ADO and CAPR. See Tables 1 and 4 and Figure 4. The resource registers are: Control (Default = 1). AE Offset - Offset value of the AE flag (Default = 8). AF Offset - Offset value of the AF flag (Default = 8). RT Offset - Offset value of the Retransmit mechanism (Default = 0). RT Base - Base register of the Retransmit mechanism (Default = 0). Parity
EXAMPLE 3
Q35
PARITY CHECK
Q0
Output word: Odd parity: Even parity: EXAMPLE 4
100111100
000111100
100111000
000111000
Parity Register = 0110; PF-Asserted Low Parity Register = 1001; PF-Asserted Low
PARITY GENERATION
D35 D0
Input word: Output, odd parity: Output, even parity:
100111100 100111100 000111100
000111100 100111100 000111100
100111000 000111000 100111000
000111000 000111000 100111000
17
LH543620 Control Register (See Figure 7) After reset, the control register's value is 1. This sets the following conditions: Odd parity Disabling parity generation (parity check is active). AF, HF, AE flags are asynchronous. OE signal does not control the Read pointer. Read/Write Resource Register Mode It is possible to write to the resource registers from either the Input Port or the Output Port. Reading from the resource register is possible only from the Output Port. The source port for the write operation is determined by the control signal CAPR. Input Port: Data from the Input Port is written to a resource register when: the value of the input-address field, ADI, selects the register (see Table 1) CAPR is LOW The operation is enabled by ADI[2:0] and synchronized to CKI. Output Port:
1024 x 36 Synchronous FIFO
Data from the Output Port is written to a resource register when: the value of the output-address field, ADO, selects the register (see Table 4) CAPR is HIGH OE is HIGH
NOTE: ADI[2:0] should remain stable whenever data is coming in from the output port.
Data is read from a resource register to the Output Port when: the value of the output-address field, ADO, selects the register (see Table 4) OE is LOW Both operations are enabled by ADO[2:0] and are synchronous to CKO. MAILBOX The mailbox mechanism includes: One 36-bit data register. Two status flags: - MFF Mailbox Full Flag - MEF Mailbox Empty Flag
654
3210
0 EVEN PARITY 1 ODD PARITY 0 PARITY GENERATION IS DISABLED 1 PARITY GENERATION IS ENABLED 0 AE ASYNCHRONOUS 1 AE SYNCHRONOUS TO CKO 0 HF ASYNCHRONOUS 1 HF SYNCHRONOUS TO CKO 2 OR 3 HF SYNCHRONOUS TO CKI 0 AF ASYNCHRONOUS 1 AF SYNCHRONOUS TO CKI 0 OE DOES NOT CONTROL THE READ POINTER 1 OE CONTROLS THE READ POINTER
543620-29
Figure 7. LH543620 Control Register
18
1024 x 36 Synchronous FIFO Writing to the Mailbox is enabled from the Input Port when the Input Port address field ADI[2:0] = 6. The write operation is synchronous to the rising edge of CKI. When writing to the Mailbox, the status flags are changed as follows: MEF is deasserted HIGH on the rising edge of CKO. MFF is asserted LOW on the rising edge of CKI. A Mailbox read is enabled from the Output Port, when the Output Port address field ADO[2:0] = 6. The Read operation is synchronized to CKO. When reading the Mailbox, the status flags are changed as follows: MEF is asserted LOW on the rising edge of CKO. MFF is deasserted HIGH on the rising edge of CKI. After reset the Mailbox is empty (i.e., MFF = HIGH, MEF = LOW). When using Mailbox, the transmitter side can transfer a message to the receiver side without interrupting the data in the FIFO memory array. DATA BYPASS MODE Data Bypass mode is selected when BYE = LOW. In this mode, data may be transferred asynchronously from the Input Port to the Output Port. The device may be placed in Data Bypass mode without voiding the contents of the FIFO memory array, the Mailbox Register, or the Resource Register. However, if the input is enabled (ENI1,2 = HIGH) then the input data D is also written to the FIFO memory array on the rising edge of CKI. If the Output is enabled, (ENO1,2 = HIGH) then the input data D is transferred to the output buffer, and the Read Pointer is incremented by CKO. The control signal OE is functioning when BYE is asserted.
LH543620 The recommended control setting for bypass is: ENI = LOW, ENO = LOW, ADI[2:0] = 7, ADO[2:0] = 7, OE = LOW, BYE = LOW OPERATIONAL MODES AND CONFIGURATIONS Interlocked Width Expansion (Figure 8A) Two LH543620s may be configured to expand the width to 72 bits. This is accomplished by: Cross-connecting the FF output of each FIFO to ENI1 (or ENI2) input of the other FIFO. Cross-connecting the EF output of each FIFO to ENO1 (or ENO2) input of the other FIFO. The composite status flags are the OR function of the individual flags. Pipeline Cascading Mode and `Two-Dimension' Pipeline Cascading Mode (Figure 8B and 8C) Depth cascading is accomplished by: Setting the upper FIFO into cascade mode: RTMD[1:0] = 0 Connecting the same free-running clock to CKO of the upper FIFO and to CKI input of the lower FIFO. Connecting the AE output of the upper FIFO to ENI1 input (or ENI2) of the lower FIFO. Connecting the FF output of the lower FIFO to ENO1 input (or ENO2) of the upper FIFO.
NOTE: RTMD[1:0] should remain stable during cascade mode operation (i.e., remain low).
19
LH543620
1024 x 36 Synchronous FIFO
CKI ENI
CKI ENI1 ENI2 FF
CKO ENO1 EF ENO2 Q[35:0]
CKO ENO
DI[71:36]
D[35:0]
DO[71:36]
CKI ENI1 FF DI[35:0] ENI2 FF D[35:0]
CKO ENO1 EF EF ENO2 Q[35:0] DO[35:0]
A. INTERLOCKED WIDTH EXPANSION
COMMON CLOCK CKI ENI1 ENI2 FF DI[35:0] CKI ENI1 ENI2 FF D[35:0] RTMD[1:0] LL CKO ENO1 AE ENO2 Q[35:0] VCC CKI ENI1 ENI2 FF D[35:0] RTMD[1:0] HH CKO ENO1 EF ENO2 Q[35:0] CKO ENO1 EF ENO2 DO[35:0]
B. PIPELINED CASCADING MODE
COMMON CLOCK CKI ENI CKI ENI1 ENI2 FF DI[71:36] D[35:0] RTMD[1:0] LL CKI ENI1 ENI2 FF DI[35:0] FF D[35:0] RTMD[1:0] LL CKO ENO1 AE ENO2 Q[35:0] CKI ENI1 ENI2 FF D[35:0] RTMD[1:0] HH CKO ENO1 AE ENO2 Q[35:0] VCC CKI ENI1 ENI2 FF D[35:0] RTMD[1:0] HH CKO ENO1 EF ENO2 Q[35:0] DO[35:0] EF CKO ENO1 EF ENO2 Q[35:0] DO[71:36] CKO ENO
VCC
C. 'TWO-DIMENSION' PIPELINED CASCADING MODE
NOTES: DI = System data input width. DO = System data output width.
543620-7
Figure 8. LH543620 Width and Depth Expansion Scheme
20
1024 x 36 Synchronous FIFO
LH543620
TIMING DIAGRAMS
t RS
RS t RF
EF, AE t RF FF, HF, AF, PF t RO OE = HIGH1 t RSR ENI1, ENI2, ENO1, ENO2 OE = LOW
Q[35:0]
ADI[2:0]3 ADO[2:0]
NOTES: 1. After reset, the outputs will be LOW if OE = LOW, and in a high-impedance state if OE = HIGH. 2. The clocks (CKI, CKO) may be free-running during a reset operation. 3. If CAPR = L, then ADO = XXX and ADI must be = H,H,H for proper reset. If CAPR = H, then ADI = XXX and ADO must be = H,H,H for proper reset.
543620-15
Figure 9. Reset Timing
21
LH543620
1024 x 36 Synchronous FIFO
tC t CL t CH
CKI t EH t ES t EH t ES
ENI1, ENI2 t DS t DH t DS t DH
D[35:0]
tC
CKO t CL t CH t EH t ES t EH t ES
ENO1, ENO2
OE t OE t OL tA t OH tA t OH t OZ t OH
Q[35:0]
PREVIOUS DATA
NOTES: 1. Both ENI1 and ENI2 must be asserted (HIGH) to enable write operations. 2. Both ENO1 and ENO2 must be asserted (HIGH) to enable read operations.
543620-8
Figure 10. Write and Read Operation
22
1024 x 36 Synchronous FIFO
LH543620
CKI tES tEH
ENI1, ENI2 tDS tDH
D[35:0]
DATA VALID tSKEW2
CKO tEF tEF
EF (NOTE) tA tOH
Q[35:0]
DATA-OUT VALID
ENO1, ENO2
OE
NOTE: If tSKEW2 < (minimum specification) then EF may change one CKO cycle later.
543620-9
Figure 11. Empty Flag Timing
23
LH543620
1024 x 36 Synchronous FIFO
NO WRITE
WRITE
CKI tFF tFF
FF (NOTE) tDS tDH
D[35:0] tES
DATA WRITE
ENI1, ENI2 tSKEW1
CKO tES tEH
ENO1, ENO2 tA tOH
Q[35:0]
DATA READ
NOTE: If tSKEW1 < (minimum specification) then FF may change one CKI cycle later.
543620-10
Figure 12. Full Flag Timing
24
1024 x 36 Synchronous FIFO
LH543620
WORD (1024 - p-1) WRITE OCCURS
WORD (1024 - p-1) READ OCCURS
CKI
CKO tSKEW1 ENI1, ENI2
ENO1, ENO2 tAF SYNCHRONOUS MODE AF tAF ASYNCHRONOUS MODE AF tAF tAF
NOTES: 1. The synchronization mode of AF is set by programming bit 5 of control register. 2. When in synchronization mode and tSKEW1 < (min specification) then AF may change one CKI later.
543620-11
Figure 13. Almost-Full Flag Synchronous and Asynchronous Modes
WORD (q + 1) READ OCCURS
WORD (q + 1) WRITE OCCURS
CKI
CKO
ENO1, ENO2
ENI1, ENI2 tSKEW2 tAE ASYNCHRONOUS MODE AE tAE SYNCHRONOUS MODE AE NOTES: 1. The synchronization mode is set by programming bit 2 of control register. 2. When AE is in synchronous mode and tSKEW2 < (min specification) then AE may change one CKO cycle later. tAE tAE
543620-12
Figure 14. Almost-Empty Flag Synchronous and Asynchronous Modes 25
LH543620
1024 x 36 Synchronous FIFO
WORD 513 WRITE OCCURS
WORD 513 READ OCCURS
CKI
CKO tSKEW2 tSKEW1
ENI1, ENI2
ENO1, ENO2 tHF ASYNCHRONOUS MODE HF tHF SYNCHRONOUS TO CKI HF tHF SYNCHRONOUS TO CKO HF NOTE: The synchronization mode of HF is determined by the state of bits 3 and 4 of the Control Register.
543620-28
tHF
tHF
tHF
Figure 15. Half-Full Flag Synchronous and Asynchronous Modes
26
1024 x 36 Synchronous FIFO
LH543620
CKI tDS tDH
D[35:0]
N1
N2
N3
N4
N5
ENI1, ENI2 tSKEW2
CKO tEF
EF tA tOH
Q[35:0] tEH
N1
N2
N3
ENO1, ENO2
OE
NOTE: 1. If tSKEW2 < (minimum specification) then EF may change one CKO later and the first word (N1) will appear on Q[35:0] one cycle later.
543620-13
Figure 16. First Word Latency
CKO
ENO1, ENO2 tPF tPF
PF tA tOH
Q[35:0]
N1
N2
N3
N4
NOTE: Parity error at word N1.
543620-14
Figure 17. Parity Flag
27
LH543620
1024 x 36 Synchronous FIFO
BYE
D[35:0]
I1 tBA
I2 tBD
I3
Q[35:0]
(FIFO OUT)
I2
I3
(FIFO OUT)
NOTES: 1. If ENI is enabled during BYE = LOW, the bypass data will be written into the FIFO. 2. If ENO is enabled the data at the Q Port is the bypass data. The RP will be updated according to CKO.
543620-16
Figure 18. Bypass
CKO tAS tAH
ADO[2:0]
7
3 tA tOH
7
Q[35:0]
N1 tEH
N2 tES tEH
PARITY R. tES
N3
N4
ENO1, ENO2
OE FIFO (N2) Q PARITY R Q FIFO (N3) Q
NOTE: N1, N2, N3, N4 are data from the FIFO and PARITY R. is the Parity Register value.
543620-17
Figure 19. Read Resource Register
28
1024 x 36 Synchronous FIFO
LH543620
CKI
CAPR tAS tAH
ADI[2:0]
7 tDS
5 tDH
7
Q[35:0] tEH
D1 tES
C tEH tES
D2
D3
D4
ENI1, ENI2 D1 FIFO C CONTROL REG. D2 FIFO D3 FIFO
543620-18
Figure 20. Write Resource Register From the Input Port
CKO
CAPR tOES tOEH
OE tAS tAH
ADO[2:0]
7 tDSO
5 tDHO
7
Q[35:0] tEH
N1 tES
C tEH tES
N2
N3
ENO1, ENO2 FIFO (N1) Q Q(C) CONTROL REG. FIFO (N2) Q FIFO (N3) Q
543620-19
Figure 21. Write Resource Register From Output Port
29
LH543620
1024 x 36 Synchronous FIFO
CKI
ENI1, ENI2 tWSS
WSI[1:0] WSI1
WSI2
DATA IS STORED ACCORDING TO:
WSI1
WSI2
WSI2
WSI2
543620-20
Figure 22. WSI[1:0] Timing
CKO
ENO1, ENO2 tWSS
WSO[1:0]
WSO1
WSO2
DATA IS READ ACCORDING TO:
WSO1
WSO2
WSO2
WSO2
543620-21
Figure 23. WSO[1:0] Timing
30
1024 x 36 Synchronous FIFO
LH543620
CKO tEH tES tEH tES
ENO1, ENO2 tAS tAH
ADO[2:0]
7
6 tMEF
7
MEF tA tOH
Q[35:0]
Q (FIFO)
MAILBOX
Q (FIFO)
CKI
MFF tSKEWM tMFF
NOTE: If tSKEWM < minimum specification MFF may be changed one CKI later.
543620-22
Figure 24. Mailbox Read
31
LH543620
1024 x 36 Synchronous FIFO
CKI tEH tES tEH tES
ENI1, ENI2 tAS tAH
ADI[2:0]
7
6 tMFF
7
MFF tDS tDH
D[35:0]
I1
M
I2
I3
I4
CKO
MEF tSKEWM tMEF
NOTE: If tSKEWM < minimum specification MEF may be changed one CKO later.
543620-23
Figure 25. Mailbox Write
32
CKO
1024 x 36 Synchronous FIFO
OE
ENO1, ENO2 tRTMH
tRTMS
RTMD 3 2
Q[35:0] tRTH tRTS
N1
N2
N3
N4
N5
N3
N4
N5
N4
N5
N6
N5
N6
RT ADDRESS (N2) RBASE ADDRESS (N3) RBASE ADDRESS (N4) RBASE ADDRESS (N5) RBASE
Figure 26. Retransmit Using Retransmit and Mark Mode
NORMAL FIFO
RETRANSMIT STATUS N3 N4 STATUS STATUS RETRANSMIT STATUS N4 STATUS
FLAGS
ROFFSET = 1
NOTES:
LH543620
1. Retransmit status: EF, AE, and FF are HIGH; HF and AF are LOW. Retransmit status for synchronous AE and HF flags (synchronized to CKO) will last for four CKO cycles. 2. RTMD[1:0] must be selected one cycle prior to RT being asserted and must remain stable during RT low.
33
543620-24
34
tRTMH tRTMS 3 tRTH tRTS 1 ADDRESS (N2) RBASE RETRANSMIT DELAY = 3 CYCLE N1 N2 N3 N4 N5 N2 N3 N4 N1 N2 N3 N4 N5 N4 N5 N6 NORMAL FLAGS STATUS
RETRANSMIT STATUS N4 STATUS N5 STATUS N6 STATUS
543620-25
LH543620
CKO
OE
ENO1, ENO2
RTMD[0:1]
RT
Figure 27. Retransmit Using Mark Mode and Retransmit Mode
Q[35:0] WITH ROFFSET=0
Q[35:0] WITH ROFFSET=2
FLAGS
1024 x 36 Synchronous FIFO
NOTES: 1. Retransmit status: EF, AE, and FF are HIGH; HF and AF are LOW. Retransmit status for synchronous AE and HF flags (synchronized to CKO) will last for four CKO cycles. 2. RTMD[1:0] must be selected one cycle prior to RT being asserted and must remain stable during RT low.
1024 x 36 Synchronous FIFO
LH543620
CKO tOES tOEH
OE
ENO1, ENO2 tA tOL tOH tOZ
Q[35:0]
543620-26
Figure 28. OE When Bit 6 of the Control Register is HIGH
35
LH543620
1024 x 36 Synchronous FIFO
PACKAGE DIAGRAM
132PQFP (PQFP132-P-S950) SECTION
0 - 8
0.15 [0.006] 0.25 [0.010] TYP.
45 CHAMFER
0.51 [0.020] MIN.
0.10 [0.004] 0.635 [0.025] TYP NON-ACCUM
28.02 [1.103] 27.86 [1.097] 27.69 [1.090] 27.18 [1.070] 24.21 [0.953] 24.05 [0.947] TOP VIEW
24.21 [0.953] 24.05 [0.947] 27.69 [1.090] 27.18 [1.070] 28.02 [1.103] 27.86 [1.097] MAXIMUM LIMIT MINIMUM LIMIT
0.51 [0.020] MIN. 4.57 [0.180] 4.06 [0.160]
DIMENSIONS IN MM [INCHES]
132 PQFP
132-pin PQFP
36
1024 x 36 Synchronous FIFO
LH543620
144TQFP (TQFP-144-P-2020)
0.50 [0.020] TYP. 0.27 [0.010] 0.17 [0.007] 0.20 [0.008] 0.09 [0.004]
20.0 [0.787] BASIC
22.0 [0.866] BASIC
20.0 [0.787] BASIC 22.0 [0.866] BASIC 1.45 [0.057] 1.35 [0.053]
DETAIL
1.60 [0.063] REF. MAX 0.15 [0.006] 0.05 [0.002] 0.75 [0.030] 0.47 [0.019] 1.00 [0.039] REF.
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
144TQFP
37
LH543620
1024 x 36 Synchronous FIFO
ORDERING INFORMATION
LH543620 Device Type X Package - ## Speed 20 25 Cycle Times (ns) 30 P 132-Pin, Plastic Quad Flat Package (PQFP132-P-S950) M 144-Pin, Thin Quad Flat Package 1024 x 36 Synchronous FIFO Example: LH543620P-20 (1024 x 36 Synchronous FIFO, 20 ns, 132-Lead, Plastic Quad Flat Package)
543620-32
38

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