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CS4124 High Side PWM FET Controller
The CS4124 is a monolithic integrated circuit designed primarily to control the rotor speed of permanent magnet, direct current (DC) brush motors. It drives the gate of an N channel power MOSFET or IGBT with a user-adjustable, fixed frequency, variable duty cycle, pulse width modulated (PWM) signal. The CS4124 can also be used to control other loads such as incandescent bulbs and solenoids. Inductive current from the motor or solenoid is recirculated through an external diode. The CS4124 accepts a DC level input signal of 0 to 5.0 V to control the pulse width of the output signal. This signal can be generated by a potentiometer referenced to the on-chip 5.0 V linear regulator, or a filtered 0% to 100% PWM signal also referenced to the 5.0 V regulator. The IC is placed in a sleep state by pulling the CTL lead below 0.5 V. In this mode everything on the chip is shutdown except for the on-chip regulator and the overall current draw is less than 275 A. There are a number of on-chip diagnostics that look for potential failure modes and can disable the external power MOSFET. Features * 150 mA Peak PWM Gate Drive Output * Patented Voltage Compensation Circuit * 100% Duty Cycle Capability * 5.0 V, 3.0% Linear Regulator * Low Current Sleep Mode * Overvoltage Protection * Boost Mode Power Supply * Output Inhibit
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16 1 DIP-16 N SUFFIX CASE 648
PIN CONNECTION AND MARKING DIAGRAM
1 OUTPUT BOOST FLT ROSC COSC CTL PGND VCC A WL, L YY, Y WW, W CS4124 AWLYYWW 16 GND INH IADJ ISENSE+ ISENSE- PMP SNI VREG = Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION*
Device CS4124YN16 Package DIP-16 Shipping 25 Units/Rail
* Contact your local sales representative for 16-lead SOIC wide package.
(c) Semiconductor Components Industries, LLC, 2000
1
November, 2000 - Rev. 6
Publication Order Number: CS4124/D
CS4124
VBAT 42.5 H 1000 F
1000 F
RS 10
470 H
1.5 F 10 k 10 nF
CFLT ROSC COSC
OUTPUT GND BOOST INH .25 F FLT IADJ 93.1 k 470 pF I + ROSC SENSE ISENSE- COSC PMP RSNI CTL SNI PGND 4 VREG VCC RCS1 CCS 51 0.022 F RCS2 51 RSENSE 4.0 m
100 F
.01 F 10 k 1.0 F P1 10 k 100 k 10 F 10 k 1.0 M MOT+ 10 k RGATE 6
PWM Input
N1 10 k
10 k
MOT-
Figure 1. Applications Diagram
ABSOLUTE MAXIMUM RATINGS*
Rating Storage Temperature Range VCC VCC Peak Transient Voltage (load dump = 26 V w/ series 10 resistor) Input Voltage Range (at any input) Maximum Junction Temperature Lead Temperature Soldering ESD Susceptibility (Human Body Model) 1. 10 seconds max. *The maximum package power dissipation must be observed. Wave Solder (through hole styles only) Note 1. Value -65 to 150 -0.3 to 30 40 -0.3 to 10 150 260 peak 2.0 Unit C V V V C C kV
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ELECTRICAL CHARACTERISTICS (4.0 V VCC 26 V; -40C < TJ < 125C; unless otherwise specified.)
Characteristic VCC Supply Operating Current Supply Quiescent Current Overvoltage Shutdown Control (CTL) Control Input Current Sleep Mode Threshold Sleep Mode Hysteresis Control Sense Differential Voltage Sense 7.0 V VCC 18 V: IADJ = 1.0 V and RCS1 = 51 IADJ = 4.0 V and RCS1 = 51 4.0 V VCC < 7.0 V: IADJ = 1.0 V and RCS1 = 51 18 V < VCC 26 V: IADJ = 1.0 V and RCS1 = 51 IADJ = 4.0 V and RCS1 = 51 4.0 V VCC 26 V, IADJ = 0 V to 5.0 V 18 104 15 15 102 -2.0 - - - - - 0.3 34 125 39 39 130 2.0 mV mV mV mV mV A 7.0 V VCC 26 V 4.0 V VCC < 7.0 V CTL = 0 V to 5.0 V - -2.0 8.0% 50 10 0.1 10% 100 - 2.0 12% 150 150 A VREG mV mV 7.0 V VCC 18 v 4.0 V VCC < 7.0 V, 18 V < VCC 26 V VCC = 12 V - - - - 26.5 5.0 - 170 - 10 15 275 29 mA mA A V Test Conditions Min Typ Max Unit
IADJ Input Current Linear Regulator Output Voltage, VREG
VCC = 4.0 V VCC = 13.2 V VCC = 26 V
2.0 4.85 4.85
- - -
- 5.15 5.20
V V V
Inhibit Inhibit Threshold Inhibit Hysteresis 4.0 V VCC 7.0 V 7.0 V VCC 26 V - 40% 100 150 50% - 325 60% 500 500 VREG mV mV
External Drive (OUTPUT) Output Frequency 4.0 V VCC < 7.0 V: ROSC = 93.1 k, COSC = 470 pF 7.0 V VCC 18 V: ROSC = 93.1 k, COSC = 470 pF 18 V < VCC 26 V: ROSC = 93.1 k, COSC = 470 pF 4.0 V VCC < 7.0 V: VCC = 13 V, CTL = 1.0 V VCC = 13 V, CTL = 2.0 V 7.0 V VCC 18 V: VCC = 13 V, CTL = 30% VREG VCC = 13 V, CTL = 55.8% VREG 18 V < VCC 26 V: VCC = 13 V, CTL = 1.5 V VCC = 13 V, CTL = 3.5 V 4.0 V VCC 26 V: RGATE = 6.0 , CGATE = 5.0 nF 4.0 V VCC 26 V: RGATE = 6.0 , CGATE = 5.0 nF 10 17 17 65 100 28.3 56.0 11.8 34.2 - - - 20 20 - - - - - - .25 .30 25 23 25 75 - 36.3 64.0 21.8 44.2 1.0 1.0 kHz kHz kHz % % % % % % s s
Voltage to Duty Cycle Conversion
Output Rise Time Output Fall Time
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CS4124
ELECTRICAL CHARACTERISTICS (continued) (4.0 V VCC 26 V; -40C < TJ < 125C; unless otherwise specified.)
Characteristic External Drive (OUTPUT) (continued) Output Sink Current 4.0 V VCC < 7.0 V: RGATE = 6.0 , CGATE = 5.0 nF 7.0 V VCC 26 V: RGATE = 6.0 , CGATE = 5.0 nF 4.0 V VCC < 7.0 V: RGATE = 6.0 , CGATE = 5.0 nF 7.0 V VCC 26 V: RGATE = 6.0 , CGATE = 5.0 nF IOUT = 1.0 mA IOUT = -1.0 mA - - - - VBOOST = 1.7 - 150 300 150 300 - - - - - - - 1.3 mA mA mA mA V V Test Conditions Min Typ Max Unit
Output Source Current
Output High Voltage Output Low Voltage Charge Pump (DRV) Boost Voltage
-
VCC + 6.4
-
-
V
PIN FUNCTION DESCRIPTION
PACKAGE PIN # 16 Lead PDIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN SYMBOL OUTPUT BOOST FLT ROSC COSC CTL PGND VCC VREG SNI PMP ISENSE- ISENSE+ IADj INH GND MOSFET gate drive. Boost voltage. Fault time out capacitor. Oscillator resistor. Oscillator capacitor. Pulse width control input. Power ground for on chip clamp. Positive power supply input. 5.0 V linear regulator. Sense inductor current. Collector of boost power transistor. Current sense minus. Current sense plus. Current limit adjust. Output Inhibit. Ground. FUNCTION
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CS4124
GND
S Q R
PMP
SNI VREG 5.0 V Regulator + _ 450 mV Overvoltage Clamp VCC PGND + _ CTL + _ Reset Triangle Oscillator S R Current Sense ISENSE+ Q + _ OUTPUT VCC
+ _ 2.5 V
INH
ISENSE- Timer Out In + _
IADJ
COSC
ROSC
FLT
Figure 2. Block Diagram
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TYPICAL PERFORMANCE CHARACTERISTICS
5.04 VCC = 26 V VCC = 13.2 V 3.11 3.01 2.91 VREG 5.00 VREG 2.81 2.71 2.0 mA VCC = 7.0 V 4.96 4.94 -50 2.61 2.51 2.41 0 50 Temperature 100 150 2.31 -50 0 50 Temperature 100 150 5.0 mA 100 A
5.02
4.98
Figure 3. VREG vs. Temperature @ ILOAD = 5.0 mA
Figure 4. VREG vs. Temperature @ VCC = 4.0 V
1.3
2.6 2.5 2.4
1.2
VREG
VREG
1.1
I = 300 mA
2.3 2.2
I = 150 mA
1.0
0.9 I = 150 mA 0.8 -50 0 50 Temperature 100 150
2.1 2.0 -50
0
50 Temperature
100
150
Figure 5. OUTPUT Voltage (Sinking Current) vs. Temperature
Figure 6. OUTPUT Saturation Voltage (Sourcing Current) vs. Temperature
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CS4124
APPLICATIONS INFORMATION
THEORY OF OPERATION Oscillator
The IC sets up a constant frequency triangle wave at the COSC lead whose frequency is related to the external components ROSC and COSC, by the following equation:
Frequency + 0.83 ROSC COSC
a 7.0 V average voltage across the load. If VCC then drops to 10 V, the IC would change the duty cycle to 70% and hence keep the average load voltage at 7.0 V.
120 100 Duty Cycle (%) 80 60 40 20 0 10 VCC = 14 V VCC = 16 V VCC = 8.0 V
The peak and valley of the triangle wave are proportional to VCC by the following:
VVALLEY + 0.1 VPEAK + 0.7 VCC VCC
This is required to make the voltage compensation function properly. In order to keep the frequency of the oscillator constant the current that charges COSC must also vary with supply. ROSC sets up the current which charges COSC. The voltage across ROSC is 50% of VCC and therefore:
IROSC + 0.5 VCC ROSC
20
30
40
50
60
70
80
90 100
CTL Voltage (% of VREG)
Figure 7. Voltage Compensation 5.0 V Linear Regulator
IROSC is multiplied by (2) internally and transferred to the COSC lead. Therefore:
V ICOSC +" CC ROSC
The period of the oscillator is:
T + 2COSC VPEAK * VVALLEY ICOSC
There is a 5.0 V, 5.0 mA linear regulator available at the VREG lead for external use. This voltage acts as a reference for many internal and external functions. It has a drop out of approximately 1.5 V at room temperature.
Current Sense and Timer
The ROSC and COSC components can be varied to create frequencies over the range of 15 Hz to 25 kHz. With the suggested values of 93.1 k and 470 pF for ROSC and COSC, the nominal frequency will be approximately 20 kHz. IROSC, at VCC = 14 V, will be 66.7 A. IROSC should not change over a more than 2:1 ratio and therefore COSC should be changed to adjust the oscillator frequency.
Voltage Duty Cycle Conversion
The IC differentially monitors the load current on a cycle by cycle basis at the ISENSE+ and ISENSE- leads. The differential voltage across these two leads is amplified internally and compared to the voltage at the IADJ lead. The gain, AV is set internally and externally by the following equation:
AV + VI(ADJ) ISENSE) * ISENSE * + 37000 1000 ) RCS
The IC translates an input voltage at the CTL lead into a duty cycle at the OUTPUT lead. The transfer function incorporates ON Semiconductor's patented Voltage Compensation method to keep the average voltage and current across the load constant regardless of fluctuations in the supply voltage. The duty cycle is varied based upon the input voltage and supply voltage by the following equation:
Duty Cycle + 100% 2.8 VCTL VCC
The current limit (ILIM) is set by the external current sense resistor (RSENSE) placed across the ISENSE+ and ISENSE- terminals and the voltage at the IADJ lead.
ILIM + 1000 ) RCS 37000 VI(ADJ) RSENSE
An internal DC voltage equal to:
VDC + (1.683 VCTL) ) VVALLEY
is compared to the oscillator voltage to produce the compensated duty cycle. The transfer is set up so that when VCC = 14 V the duty cycle will equal VCTL divided by VREG. For example at VCC = 14 V, VREG = 5.0 V and VCTL = 2.5 V, the duty cycle would be 50% at the output. This would place
The RCS resistors and CCS components form a differential low pass filter which filters out high frequency noise generated by the switching of the external MOSFET and the associated lead noise. RCS also forms an error term in the gain of the ILIM equation because the ISENSE+ and ISENSE- leads are low impedance inputs thereby creating a good current sensing amplifier. Both leads source 50 A while the chip is in run mode. IADJ should be biased between 1.0 V and 4.0 V. When the current through the external MOSFET exceeds ILIM, an internal latch is set and the output pulls the gate of the MOSFET low for the remainder of the oscillator cycle (fault mode). At the start of the next cycle, the latch is
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CS4124
reset and the IC reverts back to run mode until another fault occurs. If a number of faults occur in a given period of time, the IC "times out" and disables the MOSFET for a long period of time to let it cool off. This is accomplished by charging the CFLT capacitor each time an over current condition occurs. If a cycle goes by with no overcurrent fault occurring, an even smaller amount of charge will be removed from CFLT. If enough faults occur together, eventually CFLT will charge up to 2.4 V and the fault latch will be set. The fault latch will not be reset until CFLT discharges to 0.6 V. This action will continue indefinitely if the fault persists. The off time and on time are set by the following:
Off Time + CFLT On Time + CFLT 2.4V * 0.6V 4.5 mA 2.4V * 0.6V IAVG (1 * DC)]
inductor. The RSNI resistor sets the peak current of the inductor by tripping a comparator when the voltage across the resistor is 450 mV. The flip flop is reset and the inductor delivers its stored energy to the load. The ripple voltage (VRIPPLE) at the Boost lead is controlled by CBOOST. A snubber circuit, made up of a series resistor and capacitor, is required to dampen the ringing of the inductor. A value of 4.0 is recommended for RSNI. A zener diode is needed between the boost output voltage and the battery. This will clamp the boost lead to a specified value above the battery to prevent damage to the IC. A 9.0 volt zener diode is recommended.
Sleep State
This device will enter into a low current mode (< 275 A) when CTL lead is brought to less than 0.5 V. All functions are disabled in this mode, except for the regulator.
Inhibit
where:
IAVG + (295.5 mA DC) * [4.5 mA
IAVG + (300 mA
DC) * 4.5 mA
When the inhibit is greater than 2.5 V the internal latch is set and the external MOSFET will be turned off for the remainder of the oscillator cycle. The latch is then reset at the start of the next cycle.
Overvoltage Shutdown
DC + PWM Duty Cycle Boost Switch Mode Power Supply
The CS4124 has an integrated boost mode power supply which charges the gate of the external high-side MOSFET to greater than 5.0 V above VCC. Three leads are used for voltage boost. They are Boost, PMP and SNI. The PMP lead is the collector of a darlington tied NPN power transistor. This device charges the inductor during its on time. The boost lead is the input to chip from the external reservoir capacitor. The SNI lead is the emitter of the power NPN and is connected externally to the RSNI resistor. The power supply is controlled by the oscillator. At the start of a cycle an R-S flip flop is set the internal power NPN transistor is turned on and energy begins to build up in the
The IC will disable the output during an overvoltage event. This is a real time fault event and does not set the internal latch and therefore is independent of the oscillator timing (i.e. asynchronous). There is 325 mV (typical) of hysteresis on the overvoltage function. There is no undervoltage lockout. The device will shutdown gracefully once it runs out of headroom.
Reverse Battery
The CS4124 will not survive a reverse battery condition. A series diode is required between the battery and the VCC lead for reverse battery. A 10 resistor, (RS) is placed in series with VCC to limit the current into the IC during 40 V peak transient conditions.
Load Dump
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CS4124
PACKAGE DIMENSIONS
DIP-16 N SUFFIX CASE 648-08 ISSUE R
-A-
16 9
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical DIP-16 42 80 Unit C/W C/W
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CS4124
Notes
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CS4124
Notes
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CS4124
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CS4124/D

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