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UC1572 UC2572 UC3572
Negative Output Flyback Pulse Width Modulator
FEATURES
* Simple Single Inductor Flyback PWM for Negative Voltage Generation * Drives External PMOS Switch * Contains UVLO Circuit * Includes Pulse-by-Pulse Current Limit * Low 50A Sleep Mode Current
DESCRIPTION
The UC3572 is a negative output flyback pulse width modulator which converts a positive input voltage to a regulated negative output voltage. The chip is optimized for use in a single inductor negative flyback switching converter employing an external PMOS switch. The block diagram consists of a precision reference, an error amplifier configured for voltage mode operation, an oscillator, a PWM comparator with latching logic, and a 0.5A peak gate driver. The UC3572 includes an undervoltage lockout circuit to insure sufficient input supply voltage is present before any switching activity can occur, and a pulse-by-pulse current limit. Output current can be sensed and limited to a user determined maximum value. The UVLO circuit turns the chip off when the input voltage is below the UVLO threshold. In addition, a sleep comparator interfaces to the UVLO circuit to turn the chip off. This reduces the supply current to only 50A, making the UC3572 ideal for battery powered applications.
BLOCK DIAGRAM
UDG-94094-2
03/99
UC1572 UC2572 UC3572 ABSOLUTE MAXIMUM RATINGS
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V EAINV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to VCC IEAOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA RAMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4V CS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.7A to 0.7A I3VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15mA Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300C
CONNECTION DIAGRAM
DIL-8, SOIC-8 (TOP VIEW) D, N or J Packages
Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.
ORDERING INFORMATION
UC1572 UC2572 UC3572 TEMPERATURE RANGE -55C to +125C -40C to +85C 0C to +70C PACKAGE J D, N or J D or N
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VCC = 5V, CT = 680pF, TA = TJ.
PARAMETER Reference Section 3VREF Line Regulation Load Regulation Oscillator Section Frequency Error Amp Section EAINV IEAINV AVOL EAOUT High EAOUT Low IEAOUT Unity Gain Bandwidth Current Sense Comparator Section Threshold Input Bias Current CS Propogation Delay Gate Drive Output Section OUT High Saturation IOUT = 0 IOUT = -10mA IOUT = -100mA OUT Low Saturation Rise Time IOUT = 10mA IOUT = 100mA TJ = 25C, CLOAD = 1nF + 3.3 Ohms 0 0.7 1.5 0.1 1.5 30 0.3 1.5 2.5 0.4 2.2 80 V V V V V nS CS = 0 0.195 0.215 -0.4 300 0.235 -1 V A nS EAOUT = 2V IEANV = -1mA EAOUT = 2V EAOUT = 0.5V to 3V EAINV = -100mV EAINV = 100mV EAINV = -100mV, EAOUT = 2V EAINV = 100mV, EAOUT = 2V TJ = 25C, F = 10kHz -350 7 0.6 65 3.6 -10 0 -0.2 -0.2 90 4 0.1 -500 20 1 4.4 0.2 10 -0.9 -1.0 mV V A dB V V A mA MHz VCC = 5V to 30V 85 100 115 kHz VCC = 4.75 to 30V I3VREF = 0V to -5mA 2.94 3 1 1 3.06 10 10 V mV mV TEST CONDITIONS MIN TYP MAX UNITS
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UC1572 UC2572 UC3572 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VCC = 5V, CT = 680pF, TA = TJ.
PARAMETER Fall Time Pulse Width Modulator Section Maximum Duty Cycle Minimum Duty Cycle Modulator Gain Undervoltage Lockout Section Start Threshold Hysteresis Sleep Mode Section Threshold Supply Current Section IVCC VCC = 5V, 30V VCC = 30, CS = 3V 9 50 12 150 mA A 1.8 2.2 2.6 V 3.5 100 4.2 200 4.5 300 V mV EAINV = +100mV, VCC = 5V to 30V EAINV = -100mV, VCC = 5V to 30V EAOUT = 1.5V to 2.5V 45 55 92 96 0 65 % % %/V TEST CONDITIONS TJ = 25C, CLOAD = 1nF + 3.3 Ohms MIN TYP 30 MAX UNITS 80 nS
UDG-94095
Figure 1. Typical waveforms.
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UC1572 UC2572 UC3572 PIN DESCRIPTIONS
3VREF: Precision 3V reference. Bypass with 100nF capacitor to GND. CS: Current limit sense pin. Connect to a ground referenced current sense resistor in series with the flyback inductor. OUT will be held high (PMOS switch off) if CS exceeds 0.2V. EAINV: Inverting input to error amplifier. Summing junction for 3VREF and VOUT sense. The non-inverting input of the error amplifier is internally connected to GND. This pin will source a maximum of 1mA. EAOUT: Output of error amplifier. Use EAOUT and EAINV for loop compensation components. GND: Circuit Ground. OUT: Gate drive for external PMOS switch connected between VCC and the flyback inductor. OUT drives the gate of the PMOS switch between VCC and GND. RAMP: Oscillator and ramp for pulse width modulator. Frequency is set by a capacitor to GND by the equation
F=
1 15k * CRAMP
Recommended operating frequency range is 10kHz to 200kHz. VCC: Input voltage supply to chip. Range is 4.75 to 30V. Bypass with a 1F capacitor.
VIN
SLEEP
RSLEEP3 1MEG MSLEEP CVCC 10F C3V REF 100nF CRAMP 680pF RREF 4 VCC UC1572 OUT 5 MSWITCH 8 3VREF RSLEEP1 56k LFLYBACK RSLEEP2 33k CS 3 RCS CIN 10F
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RAMP
1 RCOMP 2 CCOMP 6 GND
EAINV
EAOUT
DFLYBACK
GND
GND
RV SENSE 40k
COUT 100F VOUT
-12V OUT
UDG-99057
Figure 2. Typical application: +5V to -12V flyback converter.
UNITRODE CORPORATION 7 CONTINENTAL BLVD. * MERRIMACK, NH 03054 TEL. (603) 424-2410 * FAX (603) 424-3460
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Copyright (c) 1999, Texas Instruments Incorporated

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