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TMS320 SECOND-GENERATION DIGITAL SIGNAL PROCESSORS
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
* * * * * * * * * * * * * * * * * * *
80-ns Instruction Cycle Time 544 Words of On-Chip Data RAM 4K Words of On-Chip Secure Program EPROM (TMS320E25) 4K Words of On-Chip Program ROM (TMS320C25) 128K Words of Data/Program Space 32-Bit ALU/Accumulator 16 x 16-Bit Multiplier With a 32-Bit Product Block Moves for Data/Program Management Repeat Instructions for Efficient Use of Program Space Serial Port for Direct Codec Interface Synchronization Input for Synchronous Multiprocessor Configurations Wait States for Communication to Slow Off-Chip Memories/Peripherals On-Chip Timer for Control Operations Single 5-V Supply Packaging: 68-Pin PGA, PLCC, and CER-QUAD 68-to-28 Pin Conversion Adapter Socket for EPROM Programming Commercial and Military Versions Available NMOS Technology: -- TMS32020 . . . . . . . . . 200-ns cycle time CMOS Technology: -- TMS320C25 . . . . . . . . 100-ns cycle time -- TMS320E25 . . . . . . . . 100-ns cycle time -- TMS320C25-50 . . . . . . 80-ns cycle time
VSS D7 D6 D5 D4 D3 D2 D1 D0 SYNC INT0 INT1 INT2 VCC DR FSR A0
68-Pin GB Package (Top View)
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L
68-Pin FN and FZ Packages (Top View)
READY CLKR CLKX V CC V CC D8 D9 D10 D11 D12 D13 D14 D15
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 10 59 11 58 12 57 13 56 14 55 15 54 16 53 17 52 18 51 19 50 20 49 21 48 22 47 23 46 24 45 25 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
IACK MSC CLKOUT1 CLKOUT2 XF HOLDA DX FSX X2 CLKIN X1 BR STRB R/W PS IS DS VSS
description
This data sheet provides complete design documentation for the second-generation devices of the TMS320 family. This facilitates the selection of the devices best suited for user applications by providing all specifications and special features for each TMS320 member. This data sheet is divided into four major sections: architecture, electrical specifications (NMOS and CMOS), timing diagrams, and mechanical data. In each of these sections, generic information is presented first, followed by specific device information. An index is provided for quick reference to specific information about a device.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
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Copyright (c) 1991, Texas Instruments Incorporated
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ADVANCE INFORMATION
TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
PGA AND PLCC/CER-QUAD PIN ASSIGNMENTS
FUNCTION A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 PIN K1/26 K2/28 L3/29 K3/30 L4/31 K4/32 L5/33 K5/34 K6/36 L7/37 K7/38 L8/39 FUNCTION A12 A13 A14 A15 BIO BR PIN K8/40 L9/41 K9/42 L10/43 B7/68 G11/50 FUNCTION D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 PIN E1/16 D2/15 D1/14 C2/13 C1/12 B2/11 A2/9 B3/8 A3/7 B4/6 A4/5 B5/4 FUNCTION D14 D15 DR DS DX FSR FSX HOLD HOLDA IACK INT0 INT1 PIN A5/3 B6/2 J1/24 K10/45 E11/54 J2/25 F10/53 A7/67 E10/55 B11/60 G1/20 G2/21 FUNCTION INT2 IS PIN H1/22 FUNCTION VCC VCC VSS VSS VSS XF X1 X2/CLKIN PIN H2/23 L6/35 B1/10 K11/44 L2/27 D11/56 G10/51 F11/52
J11/46 MP/MC A6/1 MSC PS READY RS R/W STRB SYNC VCC VCC C10/59 J10/47 B8/66 A8/65 H11/48 H10/49 F2/19 A10/61 B10/62
CLKOUT1 C11/58 CLKOUT2 D10/57 CLKR CLKX D0 D1 B9/64 A9/63 F1/18 E2/17
On the TMS32020, MP/MC must be connected to VCC. SIGNALS VCC VSS X1 X2/CLKIN CLKOUT1 CLKOUT2 D15-D0 A15-A0 PS, DS, IS R/W STRB RS INT2-INT0 MP/MC MSC IACK READY BR XF HOLD HOLDA SYNC BIO DR CLKR FSR DX CLKX FSX I/O/Z I I O I O O I/O/Z O/Z O/Z O/Z O/Z I I I O O I O O I O I I I I I O/Z I I/O/Z DEFINITION 5-V supply pins Ground pins Output from internal oscillator for crystal Input to internal oscillator from crystal or external clock Master clock output (crystal or CLKIN frequency/4) A second clock output signal 16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data, and I/O spaces. 16-bit address bus A15 (MSB) through A0 (LSB) Program, data, and I/O space select signals Read/write signal Strobe signal Reset input External user interrupt inputs Microprocessor/microcomputer mode select pin Microstate complete signal Interrupt acknowledge signal Data ready input. Asserted by external logic when using slower devices to indicate that the current bus transaction is complete. Bus request signal. Asserted when the TMS320C2x requires access to an external global data memory space. External flag output (latched software-programmable signal) Hold input. When asserted, TMS320C2x goes into an idle mode and places the data, address, and control lines in the high impedance state. Hold acknowledge signal Synchronization input Branch control input. Polled by BIOZ instruction. Serial data receive input Clock for receive input for serial port Frame synchronization pulse for receive input Serial data transmit output Clock for transmit output for serial port Frame synchronization pulse for transmit. Configuration as either an input or an output.
I/O/Z denotes input/output/high-impedance state.
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TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
description
The TMS320 family of 16/32-bit single-chip digital signal processors combines the flexibility of a high-speed controller with the numerical capability of an array processor, thereby offering an inexpensive alternative to multichip bit-slice processors. The highly paralleled architecture and efficient instruction set provide speed and flexibility to produce a MOS microprocessor family that is capable of executing more than 12.5 MIPS (million instructions per section). The TMS320 family optimizes speed by implementing functions in hardware that other processors implement through microcode or software. This hardware-intensive approach provides the design engineer with processing power previously unavailable on a single chip. The TMS320 family consists of three generations of digital signal processors. The first generation contains the TMS32010 and its spinoffs. The second generation includes the TMS32020, TMS320C25, and TMS320E25, which are described in this data sheet. The TMS320C30 is a floating-point DSP device designed for even higher performance. Many features are common among the TMS320 processors. Specific features are added in each processor to provide different cost/performance tradeoffs. Software compatibility is maintained throughout the family to protect the user's investment in architecture. Each processor has software and hardware tools to facilitate rapid design.
introduction
The TMS32010, the first NMOS digital signal processor in the TMS320 family, was introduced in 1983. Its powerful instruction set, inherent flexibility, high-speed number-crunching capabilities, and innovative architecture have made this high-performance, cost-effective processor the ideal solution to many telecommunications, computer, commercial, industrial, and military applications. Since that time, the TMS320C10, a low-power CMOS version of the industry-standard TMS32010, and other spinoff devices have been added to the first generation of the TMS320 family. The second generation of the TMS320 family (referred to as TMS320C2x) includes four members, the TMS32020, TMS320C25, TMS320C25-50, and TMS320E25. The architecture of these devices is based upon that of the TMS32010. The TMS32020, processed in NMOS technology, is source-code compatible with he TMS32010 and in many applications is capable of two times the throughput of the first-generation devices. Its enhanced instruction set (109 instructions), large on-chip data memory (544 words), large memory spaces, on-chip serial port, and hardware timer make the TMS32020 a powerful addition to the TMS320 family. The TMS320C25 is the second member of the TMS320 second generation. It is processed in CMOS technology, is capable of an instruction cycle time of 100 ns, and is pin-for-pin and object-code compatible with the TMS32020. The TMS320C25's enhanced feature set greatly increases the functionality of the device over the TMS32020. Enhancements included 24 additional instructions (133 total), eight auxiliary registers, an eight-level hardware stack, 4K words of on-chip program ROM, a bit-reversed indexed-addressing mode, and the low-power dissipation inherent to the CMOS process. An extended-temperature range version (TMS320C25GBA) is also available. The TMS320C25-50 is a high-speed version of the TMS320C25. It is capable of an instruction cycle time of less than 80 ns. It is architecturally identical to the original 40-MHz version of the TMS320C25 and, thus, is pin-for-pin and object-code compatible with the TMS320C25. The TMS320E25 is identical to the TMS320C25, with the exception that the on-chip 4K-word program ROM is replaced with a 4K-word on-chip program EPROM. On-chip EPROM allows realtime code development and modification for immediate evaluation of system performance.
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TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
Key Features: TMS32020
+5 V
GND
* * * * * * * * * * *
200-ns Instruction Cycle Time 544 Words of On-Chip Data RAM
Interrupts 128K Words of Total Data/Program Memory Space Wait States for Communication to Slower Off-Chip Memories 256-Word Data/Prog RAM 288-Word Data RAM Data (16) MultiProcessor Interface Serial Interface Shifters Address (16) Timer
Multiplier 32-BIT ALU/ACC
Source Code Compatible With the TMS320C1x Single-Cycle Multiply/Accumulate Instructions Repeat Instructions Global Data Memory Interface Block Moves for Data/Program Management Five Auxiliary Registers With Dedicated Arithmetic Unit Serial Port for Multiprocessing or Interfacing to Codecs, Serial Analog-to-Digital Converters, etc.
* * * *
On-Chip Clock Generator Single 5-V Supply NMOS Technology 68-Pin Grid Array (PGA) Package
+5 V GND
Key Features: TMS320C25, TMS320C25-50, TMS320E25
* * * * * * * * * * * * * * *
80-ns Instruction Cycle Time (TMS320C25-50) 100-ns Instruction Cycle Time (TMS320C25) 4K Words of On-Chip Secure Program EPROM (TMS320E25) 4K Words of On-Chip Program ROM (TMS320C25) 544 Words of On-Chip RAM 128K Words of Total Program/Data Memory Space Wait States for Communications to Slower Off-Chip Memories Object-Code Compatible With the TMS32020 Source-Code Compatible With TMS320C1x 24 Additional Instructions to Support Adaptive Filtering, FFTs, and Extended-Precision Arithmetic Block Moves for Data/Program Management Single-Cycle Multiply/Accumulate Instructions Eight Auxiliary Registers With Dedicated Arithmetic Unit Bit-Reversed Indexed-Addressing Mode for Radix-2 FFTS Double-Buffered Serial Port
Interrupts
256-Word 288-Word Data/Prog Data RAM RAM 4K-Words ROM/EPROM Multiplier 32-Bit ALU/ACC Shifters
Data (16)
MP/MC
MultiProcessor Interface Serial Interface Address (16)
Timer
* * * * * * * *
On-Chip Clock Generator Single 5-V Supply Internal Security Mechanism (TMS320E25) 68-to-28 Pin Conversion Adapter Socket CMOS Technology 68-Pin Grid Array (PGA) Package (TMS320C25) 68-Lead Plastic Leaded Chip Carrier (PLCC) Package (TMS320C25, TMS320C25-50) 68-Lead CER-QUAD Package (TMS320E25)
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SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
Table 1 provides an overview of the second-generation TMS320 processors with comparisons of memory, I/O, cycle timing, power, package type, technology, and military support. For specific availability, contact the nearest TI Field Sales Office. Table 1. TMS320 Second-Generation Device Overview
MEMORY DEVICE RAM TMS32020 TMS320C25 TMS320C25-50 TMS320E25 (NMOS) (CMOS) (CMOS) (CMOS) 544 544 544 544 ON-CHIP OFF-CHIP ROM/EPROM PROG DATA SER -- 4K 4K 4K 64K 64K 64K 64K 64K 64K 64K 64K YES YES YES YES
I/O
TIMER PAR 16 x 16 16 x 16 16 x 16 16 x 16 DMA YES CON CON CON YES YES YES YES
CYCLE TIME (ns) 200 100 80 100
TYP POWER (mW) 1250 500 500 500
PACKAGE TYPE
PGA 68 68 -- -- PLCC -- 68 68 -- CER-QUAD -- -- -- 68
SER = serial; PAR = parallel; DMA = direct memory access; CON = concurrent DMA. Military version available; contact nearest TI Field Sales Office for availability. Military version planned; contact nearest TI Field Sales Office for details.
architecture
The TMS320 family utilizes a modified Harvard architecture for speed and flexibility. In a strict Harvard architecture, program and data memory lie in two separate spaces, permitting a full overlap of instruction fetch and execution. The TMS320 family's modification of the Harvard architecture allows transfers between program and data spaces, thereby increasing the flexibility of the device. This modification permits coefficients stored in program memory to be read into the RAM, eliminating the need for a separate coefficient ROM. It also makes available immediate instructions and subroutines based on computed values. Increased throughput on the TMS320C2x devices for many DSP applications is accomplished by means of single-cycle multiply/accumulate instructions with a data move option, up to eight auxiliary registers with a dedicated arithmetic unit, and faster I/O necessary for data-intensive signal processing. The architectural design of the TMS320C2x emphasizes overall speed, communication, and flexibility in processor configuration. Control signals and instructions provide floating-point support, block-memory transfers, communication to slower off-chip devices, and multiprocessing implementations. 32-bit ALU/accumulator The 32-bit Arithmetic Logic Unit (ALU) and accumulator perform a wide range of arithmetic and logical instructions, the majority of which execute in a single clock cycle. The ALU executes a variety of branch instructions dependent on the status of the ALU or a single bit in a word. These instructions provide the following capabilities:
* * *
Branch to an address specified by the accumulator Normalize fixed-point numbers contained in the accumulator Test a specified bit of a word in data memory
One input to the ALU is always provided from the accumulator, and the other input may be provided from the Product Register (PR) of the multiplier or the input scaling shifter which has fetched data from the RAM on the data bus. After the ALU has performed the arithmetic or logical operations, the result is stored in the accumulator. The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The contents of the accumulator remain unchanged.
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TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
functional block diagram (TMS320C2x)
X1 X2/CLKIN CLKOUT1 CLKOUT2 SYNC IS DS PS R/W STRB READY BR XF HOLD HOLDA MSC BIO RS IACK MP/MC INT(2-0) MUX 16 A15-A0 3 16 Program Bus
16 PFC(16) 16 MUX 16
16
16 QIR(16) IR(16) STO(16) ST1(16) RPTC(8) IFR(6) DR CLKR FSR DX CLKX FSX RSR(16) XSR(16)
Controller
16 16 MCS(16) 16 PC(16)
16 16 Address Program ROM/ EPROM (4096 x 16) Instruction 16 MUX 16 16 16
16 Stack (8 x 16)
16 16 16
16 16 16 16 6 8 16 16
DRR(16) DXR(16) TIM(16) PRD(16) IMR(6) GREG(8)
D15-D0
Data Bus 16 16 3 AR0(16) 3 ARP(3) AR1(16) AR2(16) AR3(16) AR4(16) 3 AR5(16) AR6(16) AR7(16) ARB(3) 16 3 ARAU(16) 16 MUX 16 Block B2 (32 x 16) Data RAM Block B1 (256 x 16) 16 Data Bus MUX 16 MUX 16 MUX 16 DATA/PROG RAM (256 x 16) Block B0 16 MUX 16 16 32 32 16 9 Shifter(0-16) DP(9) 16 16 9 7 LSB From IR
Program Bus
16 TR(16)
16
16
MUX Multiplier 16
PR(32) 32 Shifter(-6, 0, 1, 4) 32
32
ALU(32) 32 C ACCH(16) 32 Shifters (0-7) 16 ACCL(16)
LEGEND: ACCH = ACCL = ALU = ARAU = ARB = ARP = DP = DRR = DXR =
Accumulator high Accumulator low Arithmetic logic unit Auxiliary register arithmetic unitMCS Auxiliary register pointer buffer Auxiliary register pointer Data memory page pointer Serial port data receive registerTIM Serial port data transmit register
IFR IMR IR = QIR PR PRD = TR
= Interrupt flag register PC = Interrupt mask register PFC = Instruction register RPTC Microcall stack GREG = = Queue instruction register RSR = Product register XSR = Period register for timer AR0-AR7 Timer ST0, ST1 = Temporary register C
= Program counter = Prefetch counter = Repeat instruction counter Global memory allocation register = Serial port receive shift register = Serial port transmit shift register = Auxiliary registers = Status registers = Carry bit
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SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
scaling shifter The TMS320C2x scaling shifter has 16-bit input connected to the data bus and a 32-bit output connected to the ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed in the instruction. The LSBs of the output are filled with zeroes, and the MSBs may be either filled with zeroes or sign-extended, depending upon the status programmed into the SXM (sign-extension mode) bit of status register ST1. 16 x 16-bit parallel multiplier The 16 x 16-bit hardware multiplier is capable of computing a signed or unsigned 32-bit product in a single machine cycle. The multiplier has the following two associated registers.
* *
A 16-bit Temporary Register (TR) that holds one of the operands for the multiplier, and A 32-bit Product Register (PR) that holds the product.
Incorporated into the instruction set are single-cycle multiply/accumulate instructions that allow both operands to be processed simultaneously. The data for these operations may reside anywhere in internal or external memory, and can be transferred to the multiplier each cycle via the program and data buses. Four product shift modes are available at the Product Register (PR) output that are useful when performing multiply/accumulate operations, fractional arithmetic, or justifying fractional products. timer The TMS320C2x provides a memory-mapped 16-bit timer for control operations. The on-chip timer (TIM) register is a down counter that is continuously clocked by CLKOUT1 on the TMS320C25. The timer is clocked by CLKOUT1/4 on the TMS32020. A timer interrupt (TINT) is generated every time the timer decrements to zero. The timer is reloaded with the value contained in the period (PRD) register within the next cycle after it reaches zero so that interrupts may be programmed to occur at regular intervals of PRD + 1 cycles of CLKOUT 1 on the TMS320C25 or 4 x PRD x CLKOUT 1 cycles on the TMS32020. memory control The TMS320C2x provides a total of 544 16-bit words of on-chip data RAM, divided into three separate blocks (B0, B1, and B2). Of the 544 words, 288 words (blocks B1 and B2) are always data memory, and 256 words (block B0) are programmable as either data or program memory. A data memory size of 544 words allows the TMS320C2x to handle a data array of 512 words (256 words if on-chip RAM is used for program memory), while still leaving 32 locations for intermediate storage. When using block B0 as program memory, instructions can be downloaded from external program memory into on-chip RAM and then executed. When using on-chip program RAM, ROM, EPROM, or high-speed external program memory, the TMS320C2x runs at full speed without wait states. However, the READY line can be used to interface the TMS320C2x to slower, less-expensive external memory. Downloading programs from slow off-chip memory to on-chip program RAM speeds processing while cutting system costs. The TMS320C2x provides three separate address spaces for program memory, data memory, and I/O. The on-chip memory is mapped into either the 64K-word data memory or program memory space, depending upon the memory configuration (see Figure 1). The CNFD (configure block B0 as data memory) and CNFP (configure block B0 as program memory) instructions allow dynamic configuration of the memory maps through software. Regardless of the configuration, the user may still execute from external program memory. The TMS320C2x has six registers that are mapped into the data memory space: a serial port data receive register, serial port data transmit register, timer register, period register, interrupt mask register, and global memory allocation register.
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TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
Program
0(0000h) Interrupts and Reserved (External) 31(001Fh) 32(0020h ) 31(001Fh) 32(0020h ) 4015(0FAFh) 4016(0FB0h) 0(0000h)
Program
Interrupts and Reserved (On-Chip ROM/EPROM) 0(0000h)
Data
On-Chip Memory-Mapped Registers 5(0005h) 6(0006h) Reserved 95(005Fh) 96(0060h ) 127(007Fh) 128(0080h) On-Chip Block B2 Page 0
On-Chip ROM/EPROM
Reserved 4095(0FFFh) 4096(1000h)
Reserved 511(01FFh) 512(0200h)
Pages 1-3
External 767(02FFh) 768(0300h) External 1023(03FFh) 1024(0400h)
On-Chip Block B0 On-Chip Block B1
Pages 4-5
Pages 6 -7
External
Pages 8 -511
65,535(FFFFh) If MP/MC = 1 (Microprocessor Mode)
65,535(0FFFFh)
65,535(0FFFFh)
If MP/MC = 0 (Microcomputer Mode on TMS320C25)
(a) Memory Maps After a CNFD Instruction Program
0(0000h) Interrupts and Reserved (External) 0(0000h)
Program
Interrupts and Reserved (On-Chip ROM/EPROM) On-Chip ROM/EPROM Reserved 0(0000h)
Data
On-Chip Memory-Mapped Registers 5(0005h) 6(0006h) Reserved 95(005Fh) 96(0060h ) On-Chip Block B2 Page 0
31(001Fh) 32(0020h )
31(001Fh) 32(0020h ) 4015(0FAFh) 4016(0FB0h) 4095(0FFFh) 4096(1000h)
127(007Fh) 128(0080h) Reserved Pages 1-3
External
511(01FFh) 512(0200h) Does Not Exist External 767(02FFh) 768(0300h) On-Chip Block B1 1023(03FFh) 1024(0400h) Pages 6 -7 Pages 4-5
65,279(0FEFFh) 65,280(0FF00h) On-Chip Block B0 65,535(0FFFFh) If MP/MC = 1 (Microprocessor Mode)
65,279(0FEFFh) 65,280(0FF00h) On-Chip Block B0 65,535(0FFFFh) 65,535(0FFFFh)
External
Pages 8 -511
If MP/MC = 0 (Microcomputer Mode on TMS320C25)
(b) Memory Maps After a CNFP Instruction
Figure 1. Memory Maps
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TMS320 SECOND-GENERATION DEVICES
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interrupts and subroutines The TMS320C2x has three external maskable user interrupts INT2-INT0, available for external devices that interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT), and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS) having the highest priority and the serial port transmit interrupt (XINT) having the lowest priority. All interrupt locations are on two-word boundaries so that branch instructions can be accommodated in those locations if desired. A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle instruction, the interrupt is not processed until the instruction is completed. This mechanism applies to instructions that are repeated and to instructions that become multicycle due to the READY signal. external interface The TMS320C2x supports a wide range of system interfacing requirements. Program, data, and I/O address spaces provide interface to memory and I/O, thus maximizing system throughput. I/O design is simplified by having I/O treated the same way as memory. I/O devices are mapped into the I/O address space using the processor's external address and data buses in the same manner as memory-mapped devices. Interface to memory and I/O devices of varying speeds is accomplished by using the READY line. When transactions are made with slower devices, the TMS320C2x processor waits until the other device completes its function and signals the processor via the READY line. Then, the TMS320C2x continues execution. A full-duplex serial port provides communication with serial devices, such as codecs, serial A/D converters, and other serial systems. The interface signals are compatible with codecs and many other serial devices with a minimum of external hardware. The serial port may also be used for intercommunication between processors in multiprocessing applications. The serial port has two memory-mapped registers: the data transmit register (DXR) and the data receive register (DRR). Both registers operate in either the byte mode or 16-bit word mode, and may be accessed in the same manner as any other data memory location. Each register has an external clock, a framing synchronization pulse, and associated shift registers. One method of multiprocessing may be implemented by programming one device to transmit while the others are in the receive mode. The serial port on the TMS320C25 is double-buffered and fully static. multiprocessing The flexibility of the TMS320C2x allows configurations to satisfy a wide range of system requirements and can be used as follows:
* * * *
A standalone processor A multiprocessor with devices in parallel A slave/host multiprocessor with global memory space A peripheral processor interfaced via processor-controlled signals to another device.
For multiprocessing applications, the TMS320C2x has the capability of allocating global data memory space and communicating with that space via the BR (bus request) and READY control signals. Global memory is data memory shared by more than one processor. Global data memory access must be arbitrated. The 8-bit memory-mapped GREG (global memory allocation register) specifies part of the TMS320C2x's data memory as global external memory. The contents of the register determine the size of the global memory space. If the current instruction addresses an operand within that space, BR is asserted to request control of the bus. The length of the memory cycle is controlled by the READY line. The TMS320C2x supports DMA (direct memory access) to its external program/data memory using the HOLD and HOLDA signals. Another processor can take complete control of the TMS320C2x's external memory by asserting HOLD low. This causes the TMS320C2x to place its address data and control lines in a high-impedance state, and assert HOLDA. On the TMS320C2x, program execution from on-chip ROM may proceed concurrently when the device is in the hold mode.
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TMS320 SECOND-GENERATION DEVICES
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instruction set
The TMS320C2x microprocessor implements a comprehensive instruction set that supports both numeric-intensive signal processing operations as well as general-purpose applications, such as multiprocessing and high-speed control. The TMS32020 source code is upward-compatible with TMS320C25 source code. TMS32020 object code runs directly on the TMS320C25. For maximum throughput, the next instruction is prefetched while the current one is being executed. Since the same data lines are used to communicate to external data/program or I/O space, the number of cycles may vary depending upon whether the next data operand fetch is from internal or external memory. Highest throughput is achieved by maintaining data memory on-chip and using either internal or fast external program memory. addressing modes The TMS320C2x instruction set provides three memory addressing modes: direct, indirect, and immediate addressing. Both direct and indirect addressing can be used to access data memory. In direct addressing, seven bits of the instruction word are concatenated with the nine bits of the data memory page pointer to form the 16-bit data memory address. Indirect addressing accesses data memory through the auxiliary registers. In immediate addressing, the data is based on a portion of the instruction word(s). In direct memory addressing, the instruction word contains the lower seven bits of the data memory address. This field is concatenated with the nine bits of the data memory page pointer to form the full 16-bit address. Thus, memory is paged in the direct addressing mode with a total of 512 pages, each page containing 128 words. Up to eight auxiliary registers (AR0-AR7) provide flexible and powerful indirect addressing (five on the TMS32020, eight on the TMS320C25). To select a specific auxiliary register, the Auxiliary Register Pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively. There are seven types of indirect addressing: auto-increment or auto-decrement, post-indexing by either adding or subtracting the contents of AR0, single indirect addressing with no increment or decrement, and bit-reversal addressing (used in FFTs on the TMS320C25 only) with increment or decrement. All operations are performed on the current auxiliary register in the same cycle as the original instruction, following which the current auxiliary register and ARP may be modified. repeat feature A repeat feature, used with instructions such as multiply/accumulates, block moves, I/O transfers, and table read/writes, allows a single instruction to be performed up to 256 times. The repeat counter (RPTC) is loaded with either a data memory value (RPT instruction) or an immediate value (RPTK instruction). The value of this operand is one less than the number of times that the next instruction is executed. Those instructions that are normally multicycle are pipelined when using the repeat feature, and effectively become single-cycle instructions.
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TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
instruction set summary Table 2 lists the symbols and abbreviations used in Table 3, the TMS320C25 instruction set summary. Table 3 consists primarily of single-cycle, single-word instructions. Infrequently used branch, I/O, and CALL instructions are multicycle. The instruction set summary is arranged according to function and alphabetized within each functional grouping. The symbol () indicates those instructions that are not included in the TMS320C1x instruction set. The symbol () indicates instructions that are not included in the TMS32020 instruction set. Table 2. Instruction Symbols
SYMBOL B CM D FO I K PA PM AR S X DEFINITION 4-bit field specifying a bit code 2-bit field specifying compare mode Data memory address field Format status bit Addressing mode bit Immediate operand field Port address (PA0 through PA15 are predefined assembler symbols equal to 0 through 15, respectively.) 2-bit field specifying P register output shift code 3-bit operand field specifying auxiliary register 4-bit left-shift code 3-bit accumulator left-shift field
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TMS320C25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
Table 3. TMS320C25 Instruction Set Summary
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS MNEMONIC DESCRIPTION NO. WORDS 15 ABS ADD ADDC ADDH ADDK ADDS ADDT ADLK AND ANDK CMPL LAC LACK LACT LALK NEG NORM OR ORK ROL ROR SACH SACL SBLK SFL SFR SUB SUBB SUBC SUBH SUBK SUBS Absolute value of accumulator Add to accumulator with shift Add to accumulator with carry Add to high accumulator Add to accumulator short immediate Add to low accumulator with sign extension suppressed Add to accumulator with shift specified by T register Add to accumulator long immediate with shift AND with accumulator AND immediate with accumulator with shift Complement accumulator Load accumulator with shift Load accumulator immediate short Load accumulator with shift specified by T register Load accumulator long immediate with shift Negate accumulator Normalize contents of accumulator OR with accumulator OR immediate with accumulator with shift Rotate accumulator left Rotate accumulator right Store high accumulator with shift Store low-order accumulator with shift Subtract from accumulator long immediate with shift Shift accumulator left Shift accumulator right Subtract from accumulator with shift Subtract from accumulator with borrow Conditional subtract Subtract from high accumulator Subtract from accumulator short immediate Subtract from low accumulator with sign extension suppressed 1 1 1 1 1 1 1 2 1 2 1 1 1 1 2 1 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 1 0 1 1 0 1 0 1 1 1 0 1 1 1 0 0 1 1 1 0 0 0 0 1 0 14 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 13 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 S 1 1 0 0 0 1 1 0 1 1 I 1 1 1 0 S 1 1 0 0 1 1 1 1 1 1 1 1 S 1 1 X X 0 0 1 0 0 0 S 1 1 0 0 0 1 1 1 S 1 1 0 0 I 0 0 1 I 0 0 0 I I 0 0 0 I I I I K D 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 1 1 0 0 X 0 1 X 0 0 X 1 1 S 1 0 0 1 1 1 1 0 0 1 0 0 S 1 0 INSTRUCTION BIT CODE 11 1 10 1 S 1 0 0 0 1 1 0 0 1 0 I I 0 I 0 0 I K D 0 0 0 D 0 0 0 D D 0 1 1 D D D D 0 0 0 1 0 0 1 0 1 1 1 1 0 0 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 9 1 8 0 7 0 I I I K D D 0 D 0 0 D 1 1 0 1 0 1 0 1 0 6 0 5 0 4 1 3 1 D D D 2 0 1 1 0 1
These instructions are not included in the TMS320C1x instruction set. These instructions are not included in the TMS32020 instruction set.
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TMS320C25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
Table 3. TMS320C25 Instruction Set Summary (continued)
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS MNEMONIC DESCRIPTION NO. WORDS 15 SUBT XOR XORK ZAC ZALH ZALR ZALS Subtract from accumulator with shift specified by T register Exclusive-OR with accumulator Exclusive-OR immediate with accumulator with shift Zero accumulator Zero low accumulator and load high accumulator Zero low accumulator and load high accumulator with rounding Zero accumulator and load low accumulator with sign extension suppressed 1 1 2 1 1 1 1 0 0 1 1 0 0 0 14 1 1 1 1 1 1 1 13 0 0 0 0 0 1 0 12 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 INSTRUCTION BIT CODE 11 0 1 10 1 1 S 1 0 1 0 0 0 1 1 9 1 0 8 0 0 7 I I 0 0 I I I 0 0 0 0 0 0 6 5 4 3 D D 0 0 D D D 1 0 1 0 0 0 2 1 0
AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS MNEMONIC ADRK CMPR LAR LARK LARP LDP LDPK LRLK MAR SAR SBRK DESCRIPTION NO. WORDS 15 Add to auxiliary register short immediate Compare auxiliary register with auxiliary register AR0 Load auxiliary register Load auxilliary register short immediate Load auxilliary register pointer Load data memory page pointer Load data memory page pointer immediate Load auxiliary register long immediate Modify auxiliary register Store auxiliary register Subtract from auxiliary register short immediate 1 1 1 1 1 1 1 2 1 1 1 0 1 0 1 0 0 1 1 0 0 0 14 1 1 0 1 1 1 1 1 1 1 1 13 1 0 1 0 0 0 0 0 0 1 1 12 1 0 1 0 1 1 0 1 1 1 1 INSTRUCTION BIT CODE 11 1 1 0 0 0 0 1 0 0 0 1 1 1 1 0 0 10 1 1 9 1 1 R R 0 1 0 R 0 R 1 1 1 0 I I K 0 0 1 0 1 I DP 0 0 D D 0 0 0 0 0 0 8 0 0 0 I 1 0 1 7 6 5 4 3 K 0 D K 1 D R 0 CM 2 1 0
These instructions are not included in the TMS320C1x instruction set. These instructions are not included in the TMS32020 instruction set.
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TMS320C25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
Table 3. TMS320C25 Instruction Set Summary (continued)
T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS MNEMONIC APAC LPH LT LTA LTD LTP LTS MAC MACD MPY MPYA MPYK MPYS MPYU PAC SPAC SPH SPL SPM SQRA SQRS DESCRIPTION NO. WORDS 15 Add P register to accumulator Load high P register Load T register Load T register and accumulate previous product Load T register, accumulate previous product, and move data Load T register and store P register in accumulator Load T register and subtract previous product Multiply and accumulate Multiply and accumulate with data move Multiply (with T register, store product in P register) Multiply and accumulate previous product Multiply immediate Multiply and subtract previous product Multiply unsigned Load accumulator with P register Subtract P register from accumulator Store high P register Store low P register Set P register output shift mode Square and accumulate Square and subtract previous product 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 0 14 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 0 1 13 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 0 1 1 1 0 0 1 0 0 1 0 I I 0 0 I I 0 I I 0 0 0 0 0 0 0 1 1 12 0 1 1 1 1 1 1 1 1 1 1 INSTRUCTION BIT CODE 11 1 0 1 1 1 1 1 1 1 1 1 10 1 0 1 1 1 1 0 1 1 0 0 9 1 1 0 0 1 1 1 0 0 0 1 8 0 1 0 1 1 0 1 1 0 0 0 7 0 I I I I I I I I I I K D D 0 0 D D 1 D D 0 PM 1 1 0 1 0 0 6 0 5 0 4 1 3 0 D D D D D D D D D D 2 1 1 0 0 1
These instructions are not included in the TMS320C1x instruction set. These instructions are not included in the TMS32020 instruction set.
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TMS320C25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
Table 3. TMS320C25 Instruction Set Summary (continued)
BRANCH/CALL INSTRUCTIONS NO. WORDS 15 B BACC BANZ BBNZ BBZ BC BGEZ BGZ BIOZ BLEZ BLZ BNC BNV BNZ BV BZ CALA CALL RET Branch unconditionally Branch to address specified by accumulator Branch on auxiliary register not zero Branch if TC bit 0 Branch if TC bit = 0 Branch on carry Branch if accumulator 0 Branch if accumulator > 0 Branch on I/O status = 0 Branch if accumulator 0 Branch if accumulator < 0 Branch on no carry Branch if no overflow Branch if accumulator 0 Branch on overflow Branch if accumulator = 0 Call subroutine indirect Call subroutine Return from subroutine 2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 13 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 12 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 11 1 1 1 1 1 1 0 0 1 0 0 1 0 0 0 0 1 1 1 INSTRUCTION BIT CODE 10 1 1 0 0 0 1 1 0 0 0 0 1 1 1 0 1 1 1 1 9 1 1 1 0 0 1 0 0 1 1 1 1 1 0 0 1 1 1 1 8 1 0 1 1 0 0 0 1 0 0 1 1 1 1 0 0 0 0 0 7 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 1 0 0 D 1 1 0 0 1 0 0 D D D D D D D D D D D D D D 1 0 0 6 5 4 3 D 1 0 1 2 1 0
MNEMONIC
DESCRIPTION
I/O AND DATA MEMORY OPERATIONS NO. WORDS 15 BLKD BLKP DMOV FORT IN OUT RFSM RTXM RXF SFSM STXM SXF TBLR TBLW Block move from data memory to data memory Block move from program memory to data memory Data move in data memory Format serial port registers Input data from port Output data to port Reset serial port frame synchronization mode Reset serial port transmit mode Reset external flag Set serial port frame synchronization mode Set serial port transmit mode Set external flag Table read Table write 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 14 1 1 1 1 0 1 1 1 1 1 1 1 1 1 13 1 1 0 0 0 1 0 0 0 0 0 0 0 0 12 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 11 1 1 0 1 INSTRUCTION BIT CODE 10 1 1 1 1 9 0 0 1 1 PA PA 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 8 1 0 0 0 7 I I I 0 I I 0 0 0 0 0 0 I I 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 1 0 0 0 0 1 0 0 1 D D 0 0 0 1 D D 1 0 1 1 0 1 1 0 0 1 0 0 0 0 0 1 1 1 6 5 4 3 D D D 1 1 FO 2 1 0
MNEMONIC
DESCRIPTION
These instructions are not included in the TMS320C1x instruction set. These instructions are not included in the TMS32020 instruction set.
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TMS320C25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
Table 3. TMS320C25 Instruction Set Summary (concluded)
CONTROL INSTRUCTIONS MNEMONIC BIT BITT CNFD CNFP DINT EINT IDLE LST LST1 NOP POP POPD PSHD PUSH RC RHM ROVM RPT RPTK RSXM RTC SC SHM SOVM SST SST1 SSXM STC TRAP Test bit Test bit specified by T register Configure block as data memory Configure block as program memory Disable interrupt Enable interrupt Idle until interrupt Load status register STO Load status register ST1 No operation Pop top of stack to low accumulator Pop top of stack to data memory Push data memory value onto stack Push low accumulator onto stack Reset carry bit Reset hold mode Reset overflow mode Repeat instruction as specified by data memory value Repeat instruction as specified by immediate value Reset sign-extension mode Reset test/control flag Set carry bit Set hold mode Set overflow mode Store status register ST0 Store status register ST1 Set sign-extension mode Set test/control flag Software interrupt DESCRIPTION NO. WORDS 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 14 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 13 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 12 1 1 0 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 INSTRUCTION BIT CODE 11 10 B 1 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 I I 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 1 1 0 9 8 7 I I 0 0 0 0 0 I I 0 0 I I 0 0 0 0 I K 0 1 1 1 0 0 0 0 1 0 D D 0 0 1 1 0 1 1 1 1 1 1 0 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 6 5 4 3 D D 0 0 0 0 1 D D 0 1 D D 1 0 1 0 D 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 2 1 0
These instructions are not included in the TMS320C1x instruction set. These instructions are not included in the TMS32020 instruction set.
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TMS32020
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
TMS32020 PRODUCT NOTIFICATION
Texas Instruments has identified an unusual set of circumstances that will cause the BIT (Test Bit) instruction on the TMS32020 to affect the contents of the accumulator; ideally, the BIT instruction should not affect the accumulator. This set of conditions is: 1. The overflow mode is set (the OVM status register bit is set to one.) 2. And, the two LSBs of the BIT instruction opcode word are zero. a. When direct memory addressing is used, every fourth data word is affected; all other locations are not affected. b. When indirect addressing is used, the two LSBs will be zero if a new ARP is not selected or if a new ARP is selected and that ARP is 0 or 4. 3. And, adding the contents of the accumulator with the contents of the addressed data memory location, shifted by 2 (bit code), causes an overflow of the accumulator. If all of these conditions are met, the contents of the accumulator will be replaced by the positive or negative saturation value, depending on the polarity of the overflow. Various methods for avoiding this phenomenon are available:
* * * * * *
If the TMS32020 is not in the saturation mode when the BIT instruction is executed, the device operates properly and the accumulator is not affected. Execute the Reset Overflow Mode (ROVM) instruction immediately prior to the BIT instruction and the Set Overflow Mode (SOVM) instruction immediately following the BIT instruction. If direct memory addressing is being used during the BIT instructions, reorganize memory so that the page relative locations 0, 4, 8, C, 10 . . . are not used. If indirect addressing is being used during the Bit instruction, select a new ARP which is not AR0 or AR4. If necessary, follow the instruction with a LARP AR0 or LARP AR4 to restore the code. Use the Test Bit Specified by T Register (BITT) instruction instead of the BIT instruction. The BITT instruction operates correctly and will not affect the accumulator under any circumstances. Replace TMS32020 with TMS320C25 for ideal pin-to-pIn and object-code compatibility. The BIT instruction on the TMS320C25 executes properly and will not affect the accumulator under any circumstances.
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TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
development support
Together, Texas Instruments and its authorized third-party suppliers offer an extensive line of development support products to assist the user in all aspects of TMS320 second-generation-based design and development. These products range from development and application software to complete hardware development and evaluation systems. Table 4 lists the development support products for the second-generation TMS320 devices. System development may begin with the use of the simulator, Software Development System (SWDS), or emulator (XDS) along with an assembler/linker. These tools give the TMS320 user various means of evaluation, from software simulation of the second-generation TMS320s (simulator) to full-speed in-circuit emulation with hardware and software breakpoint trace and timing capabilities (XDS). Software and hardware can be developed simultaneously by using the macro assembler/linker, C compiler, and simulator for software development, the XDS for hardware development, and the Software Development System for both software development and limited hardware development. Many third-party vendors offer additional development support for the second-generation TMS320s, including assembler/linkers, simulators, high-level languages, applications software, algorithm development tools, application boards, software development boards, and in-circuit emulators. Refer to the TMS320 Family Development Support Reference Guide (SPRU011A) for further information about TMS320 development support products offered by both Texas Instruments and its third-party suppliers. Additional support for the TMS320 products consists of an extensive library or product and applications documentation. Three-day DSP design workshops are offered by the TI Regional Technology Centers (RTCs). These workshops provide insight into the architecture and the instruction set of the second-generation TMS320s as well as hands-on training with the TMS320 development tools. When technical questions arise regarding the TMS320 family, contact the Texas Instruments TMS320 Hotline at (713) 274-2320. Or, keep informed on the latest TI and third-party development support tools by accessing the DSP Bulletin Board Service (BBS) at (713) 274-2323. The BBS serves 2400-, 1200- and 300-bps modems. Also, TMS320 application source code may be downloaded from the BBS.
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TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
Table 4. TMS320 Second-Generation Software and Hardware Support
SOFTWARE TOOLS Macro Assembler/Linker IBM MS/PC-DOS VAX/VMS VAX ULTRIX SUN UNIX Simulator IBM MS/PC-DOS VAX/VMS C Compiler IBM MS/PC-DOS VAX/VMS VAX ULTRIX SUN UNIX Digital Filter Design Package (DFDP) IBM PC-DOS DSP Software Library IBM MS/PC-DOS VAX/VMS HARDWARE TOOLS Analog Interface Board 2 (AIB2) Analog Interface Board Adaptor EPROM Programmer Adaptor Socket (68 to 28-pin) Software Development System (SWDS) XDS/22 Emulator (see Note) XDS/22 Upgrade (TMS32020 to TMS320C2x) TMDC3240812-12 TMDC3204212-18 PART NUMBER RTC/AIB320A-06 RTC/ADP320A-06 DFDP-IBM002 TMDX3242855-02 TMDX3242255-08 TMDX3242265-08 TMDX3242555-08 TMDS3242851-02 TMDS3242251-08 TMDS3242850-02 TMDS3242250-08 TMDS3242260-08 TMDS3242550-08 PART NUMBER
TMDX3270120
TMDX3268821 TMDS3262221 TMDX3282226
NOTE: Emulation support for the TMS320C25-50 is available from Macrochip Research, Inc.; refer to the TMS320 Family Development Support Reference Guide (SPRU011A) for the mailing address.
IBM is a trademark of International Business Machines Corporation. PC-DOS is a trademark of International Business Machines Corporation. VAX and VMS are trademarks of Digital Equipment Corporation. XDS is a trademark of Texas Instruments Incorporated.
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TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
documentation support
Extensive documentation supports the second-generation TMS320 devices from product announcement through applications development. The types of documentation include data sheets with design specifications, complete user's guides, and 750 pages of application reports published in the book, Digital Signal Processing Applications with the TMS320 Family (SPRA012A). An application report, Hardware Interfacing to the TMS320C25 (SPRA014A), is available for that device. A series of DSP textbooks is being published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 customers on product information. The TMS320 DSP bulletin board service provides access to large amounts of information pertaining to the TMS320 family. Refer to the TMS320 Family Development Support Reference Guide (SPRU011A) for further information about TMS320 documentation. To receive copies of second-generation TMS320 literature, call the Customer Response Center at 1-800-232-3200.
specification overview
The electrical specifications for the TMS32020, TMS320C25, TMS320E25, and TMS320C25-50 are given in the following pages. Note that the electrical specifications for the TMS320E25 are identical to those for the TMS320C25, with the addition of EPROM-related specifications. A summary of differences between TMS320C25 and TMS320C25-50 specifications immediately follows the TMS320C25-50 specification.
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TMS32020
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
absolute maximum ratings over specified temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VSS VIH VIL IOH IOL TA Supply voltage Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature (see Notes 1 and 2) 0 All inputs except CLKIN CLKIN All inputs except CLKIN CLKIN 2 2.4 - 0.3 - 0.3 4.75 NOM 5 0 VCC + 0.3 VCC + 0.3 0.8 0.8 300 2 70 MAX 5.25 UNIT V V V V V A mA C V
NOTES: 1. Case temperature (TC) must be maintained below 90C. 2. RJA = 36C/Watt, RJC = 6C/Watt.
electrical characteristics over specified free-air temperature range (unless otherwise noted)
PARAMETER VOH VOL IZ II ICC CI CO High-level output voltage Low-level output voltage Three-state current Input current Supply current Input capacitance Output capacitance TEST CONDITIONS VCC = MIN, IOH = MAX VCC = MIN, IOL = MAX VCC = MAX VI = VSS to VCC TA = 0C, VCC = MAX, fx = MAX TA = 25C, VCC = MAX, fx = MAX TC = 90C, VCC = MAX, fx = MAX MIN 2.4 -20 -10 250 285 15 15 TYP 3 0.3 0.6 20 10 360 MAX UNIT V V A A mA mA mA pF pF
All typical values for ICC are at VCC = 5 V, TA = 25C.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions should be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either V CC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
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ADVANCE INFORMATION
TMS32020
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
CLOCK CHARACTERISTICS AND TIMING
The TMS32020 can use either its internal oscillator or an external frequency source for a clock.
internal clock option
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 2). The frequency of CLKOUT1 is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and parallel resonant, with an effective series resistance of 30 , a power dissipation of 1 mW, and be specified at a load capacitance of 20 pF.
PARAMETER fx fxs C1, C2 Input clock frequency Serial port frequency TEST CONDITIONS TA = 0C to 70C TA = 0C to 70C TA = 0C to 70C MIN 6.7 50 10 TYP MAX 20.5 2563 UNIT MHz MHz pF
Value derived from characterization data; minimum fsx at test = 825 kHz.
ADVANCE INFORMATION
X1
X2/CLKIN Crystal
C1
C2
Figure 2. Internal Clock Option
external clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left unconnected. The external frequency injected must conform to the specifications listed in the following table.
switching characteristics over recommended operating conditions (see Note 3)
PARAMETER tc(C) td(CIH-C) tf(C) tr(C) tw(CL) tw(CH) td(C1-C2) CLKOUT1/CLKOUT2 cycle time CLKIN high to CLKOUT1/CLKOUT2/STRB high/low CLKOUT1/CLKOUT2/STRB fall time CLKOUT1/CLKOUT2/STRB rise time CLKOUT1/CLKOUT2 low pulse duration CLKOUT1/CLKOUT2 high pulse duration CLKOUT1 high to CLKOUT2 low, CLKOUT2 high to CLKOUT1 high, etc. 2Q - 15 2Q - 15 Q - 10 2Q 2Q Q MIN 195 25 NOM MAX 597 60 10 10 2Q + 15 2Q + 15 Q + 10 UNIT ns ns ns ns ns ns ns
NOTE 3: Q = 1/4tc(C).
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TMS32020
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
timing requirements over recommended operating conditions (see Note 3)
MIN tc(C) tf(CI) tr(CI) tw(CIL) tw(CIH) tsu(S) th(S) CLKIN cycle time CLKIN fall time CLKIN rise time CLKIN low pulse duration, tc(CI) = 50 ns (see Note 4) CLKIN high pulse duration, tc(CI) = 50 ns (see Note 4) SYNC setup time before CLKIN low SYNC hold time from CLKIN low 40 40 10 15 Q - 10 195 NOM MAX 597 10 10 UNIT ns ns ns ns ns ns ns
Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 4. CLKIN duty cycle [tr(CI) + tw(CIH)] / tc(CI) must be within 40-60%. 2.15 V RL = 825 From Output Under Test Test Point CL = 100 pF
Figure 3. Test Load Circuit
2.0 V 1.88 V 0.92 V 0.80 V 0 (a) Input
VIH (Min)
VIL (Max)
2.4 V 2.2 V 0.8 V 0.6 V 0 (b) Output
VOH (Min)
VOL (Max)
Figure 4. Voltage Reference Levels
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ADVANCE INFORMATION
TMS32020
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions (see Note 3)
PARAMETER td(C1-S) td(C2-S) tsu(A) th(A) tw(SL) tw(SH) tsu(D)W th(D)W ten(D) tdis(D) td(MSC) STRB from CLKOUT1 (if STRB is present) CLKOUT2 to STRB (if STRB is present) Address setup hold time before STRB low (see Note 5) Address hold time after STRB high (see Note 5) STRB low pulse duration (no wait states, see Note 6) STRB high pulse duration (between consecutive cycles, see Note 6) Data write setup time before STRB high (no wait states) Data write hold time from STRB high Data bus starts being driven after STRB low (write cycle) Data bus three-state after STRB high (write cycle) MSC valid from CLKOUT1 - 25 2Q - 45 Q - 15 0 Q 0 Q + 30 25 Q MIN Q - 15 - 15 Q - 30 Q - 15 2Q 2Q TYP Q 0 MAX Q + 15 15 UNIT ns ns ns ns ns ns ns ns ns ns ns
ADVANCE INFORMATION
Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as "address". 6. Delays between CLKOUT1/CLKOUT2 edges and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with no wait states.
timing requirements over recommended operating conditions (see Note 3)
MIN ta(A) tsu(D)R th(D)R td(SL-R) td(C2H-R) th(SL-R) th(C2H-R) td(M-R) th(M-R) Read data access time from address time (read cycle, see Notes 5 and 7) Data read setup time before STRB high Data read hold time from STRB high READY valid after STRB low (no wait states) READY valid after CLKOUT2 high READY hold time after STRB low (no wait states) READY hold after CLKOUT2 high READY valid after MSC valid READY hold time after MSC valid 0 Q-5 Q-5 2Q - 50 40 0 Q - 40 Q - 40 NOM MAX 3Q - 70 UNIT ns ns ns ns ns ns ns ns ns
Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as "address". 7. Read data access time is defined as ta(A) = tsu(A) + tw(SL) - tsu(D)R.
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TMS32020
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
RS, INT, BIO, AND XF TIMING switching characteristics over recommended operating conditions (see Note 3 and 8)
PARAMETER td(RS) td(IACK) td(XF) CLKOUT1 low to reset state entered CLKOUT1 to IACK valid XF valid before falling edge of STRB - 25 Q - 30 0 MIN TYP MAX 45 25 UNIT ns ns ns
NOTES: 3. Q = 1/4tc(C). 8. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met, the exact sequence shown in the timing diagrams will occur.
timing requirements over recommended operating conditions (see Note 3 and 8)
MIN tsu(IN) th(IN) tf(IN) tw(IN) tw(RS) INT/BIO/RS setup before CLKOUT1 high INT/BIO/RS hold after CLKOUT1 high INT/BIO fall time INT/BIO low pulse duration RS low pulse duration tc(C) 3tc(C) 50 0 15 NOM MAX UNIT ns
ns ns ns
Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 8. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met, the exact sequence shown in the timing diagrams will occur.
HOLD TIMING switching characteristics over recommended operating conditions (see Note 3)
PARAMETER td(C1L-AL) tdis(AL-A) tdis(C1L-A) td(HH-AH) ten(A-C1L) HOLDA low after CLKOUT1 low HOLDA low to address three-state Address three-state after CLKOUT1 low (HOLD mode, see Note 9) HOLD high to HOLDA high Address driven before CLKOUT1 low (HOLD mode, see Note 9) MIN -25 TYP 15 30 50 10 MAX 25 UNIT ns ns ns ns ns
Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 9. A15-A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as "address."
timing requirements over recommended operating conditions (see Note 3)
MIN td(C2H-H) HOLD valid after CLKOUT2 high NOM MAX Q - 45 UNIT ns
NOTE 3: Q = 1/4tc(C).
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25
ADVANCE INFORMATION
ns
TMS32020
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
SERIAL PORT TIMING switching characteristics over recommended operating conditions (see Note 3)
PARAMETER td(CH-DX) td(FL-DX) td(CH-FS) DX valid after CLKX rising edge (see Note 10) DX valid after FSX falling edge (TXM = 0, see Note 10) FSX valid after CLKX rising edge (TXM = 1) MIN TYP MAX 100 50 60 UNIT ns ns ns
NOTES: 3. Q = 1/4tc(C). 10. The last occurrence of FSX falling and CLKX rising.
timing requirements over recommended operating conditions (see Note 3)
MIN tc(SCK) tf(SCK) Serial port clock (CLKX/CLKR) cycle time Serial port clock (CLKX/CLKR) fall time Serial port clock (CLKX/CLKR) rise time Serial port clock (CLKX/CLKR) low pulse duration (see Note 11) Serial port clock (CLKX/CLKR) high pulse duration (see Note 11) FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0) FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0) DR setup time before CLKR falling edge DR hold time after CLKR falling edge 150 150 20 20 20 20 390 NOM MAX 20 000 50 50 12 000 12 000 UNIT ns ns ns ns ns ns ns ns ns
ADVANCE INFORMATION
tr(SCK) tw(SCK) tw(SCK) tsu(FS) th(FS) tsu(DR) th(DR)
Value derived from characterization data; minimum fsx at test = 825 kHz. Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 11. The duty cycle of the serial port clock must be within 40-60%.
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TMS320C25, TMS320E25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
absolute maximum ratings over specified temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Input voltage range: TMS320E25 pins 24 and 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 15 V All other inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 W Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VSS VIH Supply voltage Supply voltage All inputs except CLKIN/CLKX/CLKR/INT (0-2) High-level input voltage INT (0-2) CLKIN / CLKX / CLKR VIL IOH IOL TA All inputs except MP/ MC Low-level input voltage High-level output current Low-level output current TMS320C25, TMS320E25 Operating free-air temperature TMS320C25GBA 0 - 40 MP/ MC 2.35 2.5 3.5 - 0.3 - 0.3 4.75 NOM 5 0 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.8 0.8 300 2 70 85 MAX 5.25 UNIT V V V V V V V A mA C C
electrical characteristics over specified free-air temperature range (unless otherwise noted)
PARAMETER VOH VOL IZ II ICC CI High-level output voltage Low-level output voltage Three-state current Input current Low-level input voltage Input capacitance Normal Idle/HOLD TEST CONDITIONS VCC = MIN, IOH = MAX VCC = MIN, IOL = MAX VCC = MAX VI = VSS to VCC TA = 0C, VCC = MAX, fx = MAX MIN 2.4 - 20 - 10 110 50 15 15 TYP 3 0.3 0.6 20 10 185 100 MAX UNIT V V A A mA pF pF
CO Output capacitance All typical values are at VCC = 5 V, TA = 25.
Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions to be taken to avoid application of any voltage higher than maximum rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication "Guidelines for Handling Electrostatic-Discharge Sensitive (ESDS) Devices and Assemblies" available from Texas Instruments
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ADVANCE INFORMATION
TMS320C25, TMS320E25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
CLOCK CHARACTERISTICS AND TIMING
The TMS32025 can use either its internal oscillator or an external frequency source for a clock.
internal clock option
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 2). The frequency of CLKOUT1 is one-fourth the crystal fundamental frequency. The crystal should be either fundamental or overtone mode, and parallel resonant, with an effective series resistance of 30 , a power dissipation of 1 mW, and be specified at a load capacitance of 20 pF. Note that overtone crystals require an additional tuned LC circuit; see the application report, Hardware Interfacing to the TMS320C25 (SPRA014A).
PARAMETER fx fxs C1, C2 Input clock frequency Serial port frequency TEST CONDITIONS TA = 0C to 70C TA = 0C to 70C TA = 0C to 70C MIN 6.7 0 10 TYP MAX 40.96 5 120 UNIT MHz MHz pF
The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down to fsx = 0 Hz.
ADVANCE INFORMATION
X1
X2/CLKIN Crystal
C1
C2
Figure 2. Internal Clock Option
external clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left unconnected. The external frequency injected must conform to the specifications listed in the following table.
switching characteristics over recommended operating conditions (see Note 3)
PARAMETER tc(C) td(CIH-C) tf(C) tr(C) tw(CL) tw(CH) td(C1-C2) CLKOUT1/CLKOUT2 cycle time CLKIN high to CLKOUT1/CLKOUT2/STRB high/low CLKOUT1/CLKOUT2/STRB fall time CLKOUT1/CLKOUT2/STRB rise time CLKOUT1/CLKOUT2 low pulse duration CLKOUT1/CLKOUT2 high pulse duration CLKOUT1 high to CLKOUT2 low, CLKOUT2 high to CLKOUT1 high, etc. 2Q - 8 2Q - 8 Q-5 2Q 2Q Q MIN 97.7 5 TYP MAX 597 30 5 5 2Q + 8 2Q + 8 Q+5 UNIT ns ns ns ns ns ns ns
NOTE 3: Q = 1/4tc(C).
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TMS320C25, TMS320E25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
timing requirements over recommended operating conditions (see Note 3)
MIN tc(CI) tf(CI) tr(CI) tw(CIL) tw(CIH) tsu(S) th(S) CLKIN cycle time CLKIN fall time CLKIN rise time CLKIN low pulse duration, tc(CI) = 50 ns (see Note 4) CLKIN high pulse duration, tc(CI) = 50 ns (see Note 4) SYNC setup time before CLKIN low SYNC hold time from CLKIN low 20 20 5 8 Q-5 24.4 NOM MAX 150 5 5 UNIT ns ns ns ns ns ns ns
Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 4. CLKIN duty cycle [tr(CI) + tw(CIH)]/tc(CI) must be within 40-60%. TMS320C25 +5 V fcrystal
10 k 74HC04 F11 CLKIN C = 20 pF 47 pF 74AS04 10 k L 0.1 F 4.7 k
fcrystal, (MHz) TMS320C25 TMS320C25-50 TMS320E25 40.96 51.20 40.96
L, (H) 1.8 1.0 1.8
Figure 3. External Clock Option Shown above is a crystal oscillator circuit suitable for providing the input clock signal to the TMS320C25, TMS320E25, and TMS320C25-50. Please refer to Hardware Interfacing to the TMS320C25 (document number SPRA014A) for details on circuit operation.
2.15 V RL = 825 From Output Under Test Test Point CL = 100 pF
Figure 4. Test Load Circuit
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ADVANCE INFORMATION
TMS320C25, TMS320E25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
2.0 V 1.88 V 0.92 V 0.80 V 0 (a) Input
VIH (Min) VIL (Max)
2.4 V 2.2 V 0.8 V 0.6 V 0 (b) Output
VOH (Min) VOL (Max)
Figure 5. Voltage Reference Levels
MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions (see Note 3)
PARAMETER MIN Q-6 -6 Q - 12 Q-8 2Q - 5 2Q - 5 2Q - 20 Q - 10 0 Q - 12 0 Q + 15 12 Q 2Q + 5 2Q + 5 TYP Q 0 MAX Q+6 6 UNIT ns ns ns ns ns ns ns ns ns ns ns
ADVANCE INFORMATION
td(C1-S) td(C2-S) tsu(A) th(A) tw(SL) tw(SH) tsu(D)W th(D)W ten(D) tdis(D) td(MSC)
STRB from CLKOUT1 (if STRB is present) CLKOUT2 to STRB (if STRB is present) Address setup time before STRB low (see Note 5) Address hold time after STRB high (see Note 5) STRB low pulse duration (no wait states, see Note 6) STRB high pulse duration (between consecutive cycles, see Note 6) Data write setup time before STRB high (no wait states) Data write hold time from STRB high Data bus starts being driven after STRB low (write cycle) Data bus three-state after STRB high (write cycle) MSC valid from CLKOUT1
Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as "address". 6. Delays between CLKOUT1/CLKOUT2 edges and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with no wait states.
timing requirements over recommended operating conditions (see Note 3)
MIN ta(A) tsu(D)R th(D)R td(SL-R) td(C2H-R) th(SL-R) th(C2H-R) td(M-R) th(M-R) Read data access time from address time (read cycle, see Notes 5 and 7) Data read setup time before STRB high Data read hold time from STRB high READY valid after STRB low (no wait states) READY valid after CLKOUT2 high READY hold time after STRB low (no wait states) READY hold after CLKOUT2 high READY valid after MSC valid READY hold time after MSC valid 0 Q+3 Q+3 2Q - 25 23 0 Q - 20 Q - 20 NOM MAX 3Q - 35 UNIT ns ns ns ns ns ns ns ns ns
NOTES: 3. Q = 1/4tc(C). 5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as "address". 7. Read data access time is defines as ta(A) = tsu(A) + tw(SL) - tsu(D)R.
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TMS320C25, TMS320E25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
RS, INT, BIO, AND XF TIMING switching characteristics over recommended operating conditions (see Note 3 and 8)
PARAMETER td(RS) td(IACK) td(XF) CLKOUT1 low to reset state entered CLKOUT1 to IACK valid XF valid before falling edge of STRB -6 Q - 15 0 MIN TYP MAX 22 12 UNIT ns ns ns
NOTES: 3. Q = 1/4tc(C). 8. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met, the exact sequence shown in the timing diagrams will occur.
timing requirements over recommended operating conditions (see Note 3 and 8)
MIN tsu(IN) th(IN) tf(IN) tw(IN) tw(RS) INT/BIO/RS setup before CLKOUT1 high INT/BIO/RS hold after CLKOUT1 high INT/BIO fall time INT/BIO low pulse duration RS low pulse duration tc(C) 3tc(C) 32 0 8 NOM MAX UNIT ns
ns ns ns
Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 8. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met, the exact sequence shown in the timing diagrams will occur.
HOLD TIMING switching characteristics over recommended operating conditions (see Note 3)
PARAMETER td(C1L-AL) tdis(AL-A) tdis(C1L-A) td(HH-AH) ten(A-C1L) HOLDA low after CLKOUT1 low HOLDA low to address three-state Address three-state after CLKOUT1 low (HOLD mode, see Note 9) HOLD high to HOLDA high Address driven before CLKOUT1 low (HOLD mode, see Note 9) MIN 0 0 20 25 8 TYP MAX 10 UNIT ns ns ns ns ns
Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 9. A15-A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as "address."
timing requirements over recommended operating conditions (see Note 3)
MIN td(C2H-H) NOTE 3: HOLD valid after CLKOUT2 high NOM MAX Q - 24 UNIT ns
Q = 1/4tc(C).
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31
ADVANCE INFORMATION
ns
TMS320C25, TMS320E25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
SERIAL PORT TIMING switching characteristics over recommended operating conditions (see Note 3)
PARAMETER td(CH-DX) td(FL-DX) td(CH-FS) DX valid after CLKX rising edge (see Note 10) DX valid after FSX falling edge (TXM = 0, see Note 10) FSX valid after CLKX rising edge (TXM = 1) MIN TYP MAX 75 40 40 UNIT ns ns ns
NOTES: 3. Q = 1/4tc(C). 10. The last occurrence of FSX falling and CLKX rising.
timing requirements over recommended operating conditions (see Note 3)
MIN tc(SCK) tf(SCK) Serial port clock (CLKX/CLKR) cycle time Serial port clock (CLKX/CLKR) fall time Serial port clock (CLKX/CLKR) rise time Serial port clock (CLKX/CLKR) low pulse duration (see Note 11) Serial port clock (CLKX/CLKR) high pulse duration (see Note 11) FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0) FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0) DR setup time before CLKR falling edge DR hold time after CLKR falling edge 80 80 18 20 10 20 200 25 25 NOM MAX UNIT ns ns ns ns ns ns ns ns ns
ADVANCE INFORMATION
tr(SCK) tw(SCK) tw(SCK) tsu(FS) th(FS) tsu(DR) th(DR)
The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down to fsx = 0 Hz. Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 11. The duty cycle of the serial port clock must be within 40-60%.
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TMS320E25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
EPROM PROGRAMMING absolute maximum ratings over specified temperature range (unless otherwise noted)
Supply voltage range, VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 15 V Input voltage range on pins 24 and 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 15 V
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND.
recommended operating conditions
MIN VCC VCC VPP VPP Programming mode supply voltage (see Note 13) Read mode supply voltage Programming mode supply voltage Read mode supply voltage (see Note 12) 4.75 12 NOM 6 5 12.5 VCC 5.25 13 MAX UNIT V V V V
NOTES: 12. VPP can be connected to VCC directly (except in the program mode). VCC supply current in this case would be ICC + IPP. During programming, VPP must be maintained at 12.5 V ( 0.25 V). 13. VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. This device must not be inserted into or removed from the board when VPP or VCC is applied.
electrical characteristics over specified temperature range (unless otherwise noted)
PARAMETER IPP1 IPP2 VPP supply current VPP supply current (during program pulse) TEST CONDITIONS VPP = VCC = 5.25 V VPP = 13 V MIN TYP 30 MAX 100 50 UNIT A mA
All typical values for ICC are at VCC = 5 V, TA = 25C.
recommended timing requirements for programming, TA = 25C, VCC = 6 V, VPP = 12.5 V
(see Notes 14 and 15)
tw(IPGM) tw(FPGM) tsu(A) tsu(E) tsu(G) tdis(G) ten(G) tsu(D) tsu(VPP) tsu(VCC) th(A) th(D) MIN Initial program pulse duration Final pulse duration Address setup time E setup time G setup time Output disable time from G Output enable time from G Data setup time VPP setup time VCC setup time Address hold time Data hold time 2 2 2 0 2 0.95 2.85 2 2 2 0 130 150 NOM 1 MAX 1.05 78.75 UNIT ms ms s s s ns ns s s s s s
Value derived from characterization data and not tested. NOTES: 14. For all switching characteristics and timing measurements, input pulse levels are 0.4 V to 2.4 V and VPP = 12.5 V 0.5 V during programming. 15. Common test conditions apply for tdis(G) except during programming.
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33
ADVANCE INFORMATION
TMS320C25-50
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
absolute maximum ratings over specified temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 W Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VSS Supply voltage Supply voltage INT0-INT2 VIH High-level input voltage CLKIN, CLKX, CLKR Other inputs MP/MC VIL IOH IOL TA Low-level input voltage High-level output current Low-level output current Operating free-air temperature 0 CLKIN Other inputs 2.5 3.5 2.35 0.8 0.8 0.8 300 2 70 4.75 NOM 5 0 MAX 5.25 UNIT V V V V V V V V A mA C
ADVANCE INFORMATION
electrical characteristics over specified free-air temperature range (unless otherwise noted)
PARAMETER VOH VOL IZ II ICC CI High-level output voltage Low-level output voltage High-impedance current Input current Normal Supply current Input capacitance Idle, HOLD TEST CONDITIONS VCC = MIN, IOH = MAX VCC = MIN, IOL = MAX VCC = MAX VI = VSS to VCC TA = 0C, VCC = MAX, fx = MAX MIN 2.4 0.6 - 20 - 10 110 50 15 15 20 10 185 100 mA pF pF TYP MAX UNIT V V A A
CO Output capacitance All typical values are at VCC = 5 V, TA = 25C.
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TMS320C25-50
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
CLOCK CHARACTERISTICS AND TIMING
The TMS320C25-50 can use either its internal oscillator or an external frequency source for a clock. internal clock option The internal oscillator is enabled by connecting a crystal across X1 and X2, CLKIN. The frequency of CLKOUT1 is one-fourth the crystal fundamental frequency. The crystal should be in either fundamental or overtone mode, and parallel resonant, with an effective series resistance of 30 , a power dissipation of 1 mW, and be specified at a load capacitance of 20 pF. Note that overtone crystals require an additional tuned LC circuit.
PARAMETER fx fsx C1, C2 Input clock frequency Serial port frequency TEST CONDITIONS TA = 0C to 70C TA = 0C to 70C TA = 0C to 70C MIN 6.7 0 10 TYP MAX 51.2 6.4 UNIT MHz MHz pF
The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down to fsx = 0 Hz.
X1
X2/CLKIN Crystal
C1
C2
Figure 6. Internal Clock Option external clock option An external frequency source can be used by injecting the frequency directly into X2/CLK, with X1 left unconnected. The external frequency injected must conform to specifications listed in the following table.
switching characteristics over recommended operating conditions (see Note 3)
MIN tc(C) td(CIH-C) tf(C) tr(C) tw(CL) tw(CH) td(C1-C2) CLKOUT1, CLKOUT2 cycle time CLKIN high to CLKOUT1, CLKOUT2, STRB high, low CLKOUT1, CLKOUT2, STRB fall time CLKOUT1, CLKOUT2, STRB rise time CLKOUT1, CLKOUT2, STRB low pulse duration CLKOUT1, CLKOUT2, STRB high pulse duration CLKOUT1 high to CLKOUT2 low, CLKOUT2 high to CLKOUT1 high, etc. 2Q - 7 2Q - 3 Q-6 78.13 12 NOM MAX 597 27 4 4 2Q + 3 2Q + 7 Q+2 UNIT ns ns ns ns ns ns ns
NOTE 3: Q = 1/4 tc(C)
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ADVANCE INFORMATION
TMS320C25-50
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
TMS320C25
+5 V
fcrystal
10 k 74HC04 F11 CLKIN C = 20 pF 47 pF 74AS04 10 k L 0.1 F 4.7 k
fcrystal, (MHz) TMS320C25 TMS320C25-50 TMS320E25 40.96 51.20 40.96
L, (H) 1.8 1.0 1.8
ADVANCE INFORMATION
Figure 7. External Clock Option
timing requirements over recommended operating conditions (see Note 3)
MIN tc(CI) tf(CI) tr(CI) tw(CIL) tw(CIH) tsu(S) th(S) CLKIN cycle time CLKIN fall time CLKIN rise time CLKIN low pulse duration, tc(CI) = 50 ns (see Note 4) CLKIN high pulse duration, tc(CI) = 50 ns (see Note 4) SYNC setup time before CLKIN low SYNC hold time from CLKIN low 20 20 4 4 Q-4 19.5 3 NOM MAX 150 5 5 UNIT ns ns ns ns ns ns ns
Value derived from characterization data and not tested. NOTES: 3. Q = 1/4 tc(C) 4. CLKIN duty cycle [tr(CI) + tw(CIH)]/tc(CI) must be within 40-60%.
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TMS320C25-50
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions (see Note 3)
PARAMETER td(C1-S) td(C2-S) tsu(A) tn(A) tw(SL) tw(SH) tsu(D)W th(D)W ten(D) tdis(D) td(MSC) STRB from CLKOUT (if STRB is present) CLKOUT2 to STRB (if STRB is present) Address setup time before STRB low (see Note 5) Address hold time after STRB high (see Note 5) STRB low pulse duration (no wait states, see Note 6) STRB high pulse duration (between consecutive cycles, see Note 6) Data write setup time before STRB high (no wait) Data write hold time from STRB high Data bus starts being driven after STRB low (write) Data bus high-impedance state after STRB high, (write) MSC valid from CLKOUT1 -1 MIN Q-5 -2 Q - 11 Q-4 2Q - 5 2Q - 2 2Q - 17 Q-5 0 Q Q + 15 9 2Q + 2 2Q + 5 TYP MAX Q+3 5 UNIT ns ns ns ns ns ns ns ns ns ns ns
Value derived from characterization data and not tested. NOTES: 3. Q = 1/4 tc(C) 5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as "address". 6. Delay between CLKOUT1, CLKOUT2, and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with no wait states.
timing requirements over recommended operating conditions (see Note 3)
MIN ta(A) tsu(D)R th(D)R td(SL-R) td(C2H-R) th(SL-R) th(C2H-R) td(M-R) th(M-R) Read data access time from address time (see Notes 5 and 7) Data read setup time before STRB high Data read hold time from STRB high READY valid after STRB low (no wait states) READY valid after CLKOUT2 high READY hold time after STRB low (no wait states) READY valid after CLKOUT2 high READY valid after MSC valid READY hold time after MSC valid 0 Q-1 Q-1 2Q - 24 19 0 Q - 21 Q - 21 NOM MAX 3Q - 30 UNIT ns ns ns ns ns ns ns ns ns
NOTES: 3. Q = 1/4 tc(C) 5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as "address". 7. Read data access time is defined as ta(A) = tsu(A) + tw(SL) - tsu(D)R.
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TMS320C25-50
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
RS, INT, BIO, AND XF TIMING switching characteristics over recommended operating conditions (see Notes 3 and 16)
PARAMETER td(RS) td(IACK) td(XF) CLKOUT1 low to reset state entered CLKOUT1 to IACK valid XF valid before falling edge of STRB -5 Q-8 MIN TYP MAX 22 7 UNIT ns ns ns
Value derived from characterization data and not tested. NOTES: 3. Q = 1/4 tc(C) 16. RS, INT, BIO are asynchronous inputs and can occur at any time during a clock cycle.
timing requirements over recommended operating conditions (see Notes 3 and 16)
MIN tsu(IN) th(IN) tf(IN) tw(IN) tw(RS) INT, BIO, RS setup before CLKOUT1 high INT, BIO, RS hold after CLKOUT1 high INT, BIO fall time INT, BIO low pulse duration RS low pulse duration tc(C) 3tc(C) 25 0 8 NOM MAX UNIT ns ns ns ns ns
ADVANCE INFORMATION
Value derived from characterization data and not tested. NOTES: 3. Q = 1/4 tc(C) 16. RS, INT, BIO are asynchronous inputs and can occur at any time during a clock cycle.
HOLD TIMING switching characteristics over recommended operating conditions (see Note 3)
PARAMETER td(CIL-AL) tdis(AL-A) tdis(CIL-A) td(HH-AH) ten(A-CIL) HOLDA low after CLKOUT1 low HOLDA low to address high-impedance Address high-impedance after CLKOUT1 low (HOLD mode, see Note 17) HOLD high to HOLDA high Address driven before CLKOUT1 low (HOLD mode, see Note 17) MIN 1 TYP 0 20 19 8 MAX 11 UNIT ns ns ns ns ns
Value derived from characterization data and not tested. NOTES: 3. Q = 1/4 tc(C) 17. A15-A0, PS, DS, STRB, and R/W timings are all included in timings referenced as "address".
timing requirements over recommended operating conditions (see Note 3)
MIN td(C2H-H) HOLD valid after CLKOUT2 high NOM MAX Q - 19 UNIT ns
NOTE 3: Q = 1/4 tc(C)
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TMS320C25-50
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
SERIAL PORT TIMING switching characteristics over recommended operating conditions (see Note 3)
PARAMETER td(CH-DX) td(FL-DX) td(CH-FS) DX valid after CLKX rising edge (see Note 18) DX valid after falling edge (TXM = 0, see Note 18) FSX valid after CLKX raising edge (TXM = 1) MIN TYP MAX 75 40 40 UNIT ns ns ns
NOTES: 3. Q = 1/4 tc(C) 18. The last occurrence of FSX falling and CLKX rising.
timing requirements over recommended operating conditions (see Note 3)
MIN tc(SCK) tf(SCK) tr(SCK) tw(SCK) tsu(FS) th(FS) tsu(DR) th(DR) Serial port clock (CLKX/CLKR) cycle time Serial port clock (CLKX/CLKR) fall time Serial port clock (CLKX/CLKR) rise time Serial port clock (CLKX/CLKR) low or high pulse duration (see Note 19) FSX or FSR setup time before CLKX, CLKR falling edge (TXM = 0) FSX or FSR hold time before CLKX, CLKR falling edge (TXM = 0) DR setup time before CLKR falling edge DR hold time after CLKR falling edge 64 5 10 5 10 160 25 25 NOM MAX UNIT ns ns
ns ns ns ns ns
The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down to fsx = 0 Hz. Value derived from characterization data and not tested. NOTES: 3. Q = 1/4 tc(C) 19. The cycle of the serial port must be within 40%-60%.
CONTRAST SUMMARY OF ELECTRICAL SPECIFICATIONS
The following table presents electrical parameters which differ between TMS320C25 (40 MHz, 100 ns) and TMS320C25-50 (50 MHz, 80 ns).
clock characteristics and timing
PARAMETER tc(SCK) td(CIH-C) tf(C) tr(C) tw(CL) tw(CH) td(C1-C2) tsu(S) th(S) 2Q - 8 2Q - 8 Q-5 5 8 2Q 2Q Q TMS320C25 MIN 97.7 5 TYP MAX 597 30 5 5 2Q + 8 2Q + 8 Q+5 Q-5 2Q - 7 2Q - 3 Q-6 4 4 TMS320C25-50 MIN 78.13 12 TYP MAX 597 27 4 4 2Q + 3 2Q + 7 Q+2 Q-4 UNIT ns ns ns ns ns ns ns ns ns
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ns
TMS320C25-50
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
memory and peripheral interface timing
PARAMETER td(C1-S) td(C2-S) tsu(A) th(A) tw(SL) tw(SH) tsu(D)W th(D)W td(MSC) ta(A) tsu(D)R th(D)R 2Q - 20 Q - 10 - 12 23 0 Q - 20 Q - 20 Q+3 Q+3 2Q - 25 0 0 Q-1 Q-1 2Q - 24 Q 0 12 3Q - 35 19 0 Q - 21 Q - 21 TMS320C25 MIN Q -6 -6 Q - 12 Q-8 2Q 2Q TYP Q 0 MAX Q+6 6 TMS320C25-50 MIN Q-5 -2 Q - 11 Q-4 2Q - 5 2Q - 2 2Q - 17 Q-5 -1 9 3Q - 30 2Q + 2 2Q + 5 TYP MAX Q+3 5 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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td(SL-R) td(C2H-R) th(SL-R) th(C2H-R) td(M-R) th(M-R)
RS, INT, BIO, and XF timing
PARAMETER td(IACK) td(XF) tsu(IN) th(IN) TMS320C25 MIN -6 Q - 15 32 0 TYP 0 MAX 12 TMS320C25-50 MIN -5 Q-8 25 0 TYP MAX 7 UNIT ns ns ns ns
HOLD timing
TMS320C25 PARAMETER td(C1L-AL) td(HH-AH) td(C2H-H) MIN 0 TYP MAX 10 25 Q - 24 TMS320C25-50 MIN 1 TYP MAX 11 19 Q - 19 UNIT ns ns ns
serial port timing
TMS320C25 PARAMETER td(CH-DX) td(FL-DX) td(CH-FS) tsu(FS) th(FS) tsu(DR) th(DR) 18 20 10 20 MIN TYP MAX 75 40 40 5 10 5 10 TMS320C25-50 MIN TYP MAX 70 40 40 UNIT ns ns ns ns ns ns ns
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TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
TIMING DIAGRAMS
This section contains all the timing diagrams for the TMS320 second-generation devices. Refer to the top corner of page for the specific device. Timing measurements are referenced to and from a low voltage of 0.8 voltage and a high voltage of 2 volts, unless otherwise noted.
clock timing
tc(CI) tf(CI) tr(CI) X/2CLKIN th(S) tsu(S) SYNC tc(C) td(CIH-C) CLKOUT1 tw(CH) td(CIH-C) STRB td(CIH-C) tr(C) tf(C) tw(CL) td(CIH-C) tsu(S) tw(CIH) tw(CIL)
tc(C) tw(CL)
CLKOUT2 td(C1-C2) td(C1-C2) td(C1-C2) td(C1-C2) tw(CH) tf(C) tr(C)
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TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
memory read timing
td(C1-S) CLKOUT1 td(C1-S) CLKOUT2 td(C2-S) STRB tw(SH) tsu(A) tw(SL) th(A) td(C2-S)
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42
A15-A0, BR, PS, DS or IS ta(A) R/W td(SL-R)
Valid
tsu(D)R READY
th(SL-R) D15-D0 Data In
th(D)R
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TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
memory write timing
CLKOUT1
CLKOUT2
STRB th(A) tsu(A) A15-A0, BR, PS, DS or IS Valid
R/W
READY tsu(D)W
th(D)W
D15-D0
Data Out
ten(D)
tdis(D)
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TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
one wait-state memory access timing
CLKOUT1
CLKOUT2
STRB th(C2H-R) A15-A0, BR, PS, DS, R/W or IS td(C2H-R) READY td(M-R) D15-D0 (For Read Operation) D15-D0 (For Write Operation) td(MSC) MSC td(MSC) th(M-R) td(M-R) th(M-R) Data In th(C2H-R) Valid td(C2H-R)
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44
Data Out
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TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
reset timing
CLKOUT1 tsu(IN) td(RS) tsu(IN) th(IN)
RS tw(RS) A15-A0 Valid Fetch Location 0 D15-D0 Valid PS Begin Program Execution
STRB
Control Signals
IACK
Serial Port Control Control signals are DS, IS, R/W, and XF. Serial port controls are DX and FSX.
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TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
interrupt timing (TMS32020)
CLKOUT1
STRB tsu(IN) tw(IN) INT2-INT0 tf(IN) A15-A0 FETCH N td(IACK) IACK FETCH N + 1 td(IACK) FETCH I FETCH I + 1 th(IN)
ADVANCE INFORMATION
interrupt timing (TMS320C25)
CLKOUT1 tsu(IN) STRB th(IN) tw(IN) INT2-INT0 tf(IN) A15-A0 FETCH N td(IACK) IACK td(IACK) FETCH N + 1 FETCH N + 2 N+3 FETCH I
46
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TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
serial port receive timing
tc(SCK) tr(SCK) tw(SCK) CLKR th(DR) th(FS)
tf(SCK) tw(SCK)
FSR tsu(FS) DR
tsu(DR)
serial port transmit timing
tc(SCK) tw(SCK) CLKX td(CH-DX) tf(SCK) th(FS) FSX (Input, TXM = 0) tsu(FS) DX td(FL-DX) N=1 td(CH-FS) td(CH-DX) N = 8,16 tw(SCK) tr(SCK)
td(CH-FS) FSX (Output, TXM = 1)
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TMS32020
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
BIO timing
CLKOUT1
STRB FETCH Branch Address A15-A0 FETCH BIOZ PC = N tsu(IN) th(IN) PC = N + 1 PC = N + 2 PC = N + 3 or Branch Address FETCH Next Instruction
ADVANCE INFORMATION
BIO
Valid
external flag timing
CLKOUT1
STRB td(XF) A15-A0 Valid PC = N - 1 XF FETCH SXF/RXF PC = N Valid PC = N + 1 Valid PC = N + 2 Valid
48
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TMS320C25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
BIO timing
CLKOUT1
STRB FETCH Branch Address A15-A0 FETCH BIOZ PC = N tsu(IN) th(IN) BIO Valid PC = N + 1 PC = N + 2 or Branch Address FETCH Next Instruction
external flag timing
CLKOUT1
STRB td(XF) A15-A0 FETCH SXF/RXF PC = N XF Valid PC = N + 1 Valid PC = N + 2 Valid PC = N + 3 Valid
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TMS32020
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
HOLD timing (part A)
CLKOUT1
CLKOUT2
STRB td(C2H-H) HOLD
ADVANCE INFORMATION
50
A15-A0
N
N+1
N+2
PS, DS, or IS
Valid
Valid
R/W tdis(C1L-A) D15-D0 In In tdis(AL-A) HOLDA td(C1L-AL) N N-1 N+1 N N/A Dummy N/A Dead
FETCH EXECUTE
HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur.
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TMS32020
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
HOLD timing (part B)
CLKOUT1
CLKOUT2 ten(A-C1L) STRB td(C2H-H) HOLD
A15-A0
Valid
Valid
PS, DS, or IS
R/W td(HH-AH) D15-D0
In
In
HOLDA N/A Dead N /A Dead
N+2 N+2 N+1
N+3 N+3 N+2
FETCH EXECUTE
HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur.
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TMS320C25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
HOLD timing (part A)
CLKOUT1
CLKOUT2
STRB td(C2H-H) HOLD
ADVANCE INFORMATION
52
A15-A0
N
N+1
N+2
PS, DS, or IS
Valid
Valid
R/W tdis(C1L-A) D15-D0 In In tdis(AL-A) HOLDA td(C1L-AL) N N-2 N+1 N -1 - N - -
FETCH EXECUTE
HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur.
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TMS320C25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
HOLD timing (part B)
CLKOUT1
CLKOUT2 ten(A-C1L) STRB td(C2H-H) HOLD
PS, DS, or IS
Valid
R/W
D15-D0 td(HH-AH) HOLDA
In
A15-A0 - - - -
N+2 - -
N+2 N+2 N+1
FETCH EXECUTE
HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur.
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TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
TYPICAL SUPPLY CURRENT CHARACTERISTICS FOR TMS320C25
ICC vs f(CLKIN) and VCC Normal Operating Mode 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 4 8 80 TA = 25C VCC = 5.50 V VCC = 5.25 V VCC = 5.00 V VCC = 4.75 V VCC = 4.50 V 70 60 ICC, mA 50 40 30 20 10 0 12 16 20 24 28 32 36 40 44 48 52 f(CLKIN), MHz 4 8 12 16 20 24 28 32 36 40 44 48 52 f(CLKIN), MHz VCC = 5.50 V VCC = 5.25 V VCC = 5.00 V VCC = 4.75 V VCC = 4.50 V ICC vs f(CLKIN) and VCC Powerdown Mode
TMS320C25FNL (PLCC) reflow soldering precautions
ICC, mA
ADVANCE INFORMATION
54
Recent tests have identified an industry-wide problem experienced by surface mounted devices exposed to reflow soldering temperatures. This problem involves a package cracking phenomenon sometimes experienced by large (e.g., 68-lead) plastic leaded chip carrier (PLCC) packages during surface mount manufacturing. This phenomenon occur if the TMS320C25FNL is exposed to uncontrolled levels of humidity prior to reflow solder. This moisture can flash to steam during solder reflow, causing sufficient stress to crack the package and compromise device integrity. If the TMS320C25FNL is being socketed, no special handling precautions are required. In addition, once the device is soldered into the board, no special handling precautions are required. In order to minimize moisture absorption, TI ships the TMS320C25FNL in "dry pack" shipping bags with a RH indicator card and moisture-absorbing desiccant. These moisture-barrier shipping bags will adequately block moisture transmission to allow shelf storage for 12 months from date of seal when stored at less than 60% relative humidity (RH) and less than 30C. Devices may be stored outside the sealed bags indefinitely if stored at less than 25% RH and 30C. Once the bag seal is broken, the devices should be stored at less than 60% RH and 30C as well as reflow soldered within two days of removal. In the event that either of the above conditions is not met, TI recommends these devices be baked in a clean oven at 125C and 10% maximum RH for 24 hours. This restores the devices to their "dry packed" moisture level.
NOTE Shipping tubes will not withstand the 125C baking process. Devices should be transferred to a metal tray or tube before baking. Standard ESD precautions should be followed.
In addition, TI recommends that the reflow process not exceed two solder cycles and the temperature not exceed 220C. If you have any additional questions or concerns, please contact your local TI representative.
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TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
MECHANICAL DATA 68-pin GB grid array ceramic package (TMS32020, TMS320C25)
28,448 (1.120) 27,432 (1.080) Thermal Resistance Characteristics PARAMETER RJA RJC Junction-to-free-air thermal resistance Junction-to-case thermal resistance MAX 36 6 UNIT C/W C/W 17,02 (0.670) Nom 28,448 (1.120) 27,432 (1.080) 17,02 (0.670) Nom
4,953 (0.195) 2,032 (0.080)
1,397 (0.055) Max
3,302 (0.130) 2,794 (0.110)
0,508 (0.020) 0,406 (0.016)
1,575 (0.062) Dia 1,473 (0.058)
L K J H G F E D C B A
2,54 (0.100) T.P. 2,54 (0.100) T.P.
1,524 (0.060) Nom 4 Places 1 2 3 4 5 6 7 8 9 10 11
1,27 (0.050) Nom ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
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TMS320C25 TMS320C25-50
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
68-lead plastic leaded chip carrier package (TMS320C25 and TMS320C25-50)
Seating Plane 0,25 (0.010) R Max 3 Places 1,27 (0.050) T.P. (see Note B)
24,33 (0.956) 24,13 (0.950) (see Note A)
23,62 (0.930) 23,11 (0.910) (At Seating Plane)
25,27 (0.995) 25,02 (0.985)
ADVANCE INFORMATION
56
1,22 (0.048) x 45 1,07 (0.042) 24,33 (0.956) 24,13 (0.950) (see Note A) 25,27 (0.995) 25,02 (0.985)
0,94 (0.037) 0,69 (0.027) R 1,35 (0.053) x 45 1,19 (0.047) 2,79 (0.110) 2,41 (0.095) 4,50 (0.177) 4,24 (0.167)
Thermal Resistance Characteristics PARAMETER RJA RJC Junction-to-free-air thermal resistance Junction-to-case thermal resistance MAX 46 11 UNIT C/W C/W
0,81 (0.032) 0,66 (0.026)
1,52 (0.060) Min
0,64 (0.025) Min
0,51 (0.020) 0,36 (0.014) Lead Detail ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTES: A. Centerline of center pin, each side, is within 0,10 (0.004) of package centerline as determined by this dimension. B. Location of each pin is within 0,127 (0.005) of true position with respect to center pin on each side.
WARNING When reflow soldering is required, refer to page 54 for special handling instructions.
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TMS320E25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
MECHANICAL DATA 68-lead FZ CER-QUAD, ceramic leaded chip carrier package (TMS320E25 only)
This hermetically-sealed chip carrier package consists of a ceramic base, ceramic cap, and a 68-lead frame. Hermetic sealing is accomplished with glass. The FZ package is intended for both socket- or surface- mounting. Having a Sn/Pb ratio of 60/40, the tin/lead-coated leads do not require special cleaning or processing when being surface-mounted.
A (see Note 2) B 1,02 (0.040) x 45 3,55 (0.140) 3,05 (0.120)
4,57 (0.180) 3,94 (0.155)
1,27 (0.050) Typ (see Note 3)
A B (see Note 2)
0,81 (0.032) 0,66 (0.026)
C (At Seating Plane)
(see Note 1)
0,64 (0.025) R Max 3 Places
0,51 (0.020) 0,36 (0.014) 1,016 (0.040) Min Ref 3,05 (0.120) 2,29 (0.090)
Thermal Resistance Characteristics PARAMETER RJA RJC Junction-to-free-air thermal resistance Junction-to-case thermal resistance MAX 49 8 UNIT C/W C/W
Seating Plane (see Note 4)
JEDEC OUTLINE MO-087AA MO-087AB ---
NO. OF TERMINALS 28 44 68
A MIN 12,32 (0.485) 17,40 (0.685) 25,02 (0.985) MAX 12,57 (0.465) 17,65 (0.695) 25,27 (0.995) MIN 10,92 (0.430) 16,00 (0.630) 23,62 (0.930)
B MAX 11,56 (0.455) 16,64 (0.655) 24,26 (0.955) MIN 10,41 (0.410) 15,49 (0.610) 23,11 (0.910)
C MAX 10,92 (0.430) 16,00 (0.630) 23,62 (0.930)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTES: 1. 2. 3. 4. Glass is optional, and the diameter is dependent on device application. Centerline of center pin, each side, is within 0,10 (0.004) of package centerline as determined by dimension B. Location of each pin is within 0,127 (0.005) of true position with respect to center pin on each side. The lead contact points are within 0,15 (0.006) of being planar.
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TMS320E25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
programming the TMS320E25 EPROM cell
The TMS320E25 includes a 4K x 16-bit EPROM, implemented from an industry-standard EPROM cell, to perform prototyping and early field testing and to achieve low-volume production. When used with a 4K-word masked-ROM TMS320C25, the TMS320E25 yields a high-volume, low-cost production as a result of more migration paths for data. An EPROM adapter socket (part # TMDX3270120), shown in Figure 8, is available to provide 68-pin to 28-pin conversion for programming the TMS320E25.
ADVANCE INFORMATION
fast programming and verification
58
Figure 8. EPROM Adapter Socket Key features of the EPROM cell include standard programming and verification. For security against copyright violations, the EPROM cell features an internal protection mechanism to prevent proprietary code from being read. The protection feature can be used to protect reading the EPROM contents. This section describes erasure, fast programming and verification, and EPROM protection and verification. The TMS320E25 EPROM cell is programmed using the same family and device codes as the TMS27C64 8K x 8-bit EPROM. The TMS27C64 EPROM series are ultraviolet-light erasable, electrically programmable read-only memories, fabricated using HVCMOS technology. The TMS27C64 is pin-compatible with existing 28-pin ROMs and EPROMs. The TMS320E25, like the TMS27C64, operates from a single 5-V supply in the read mode; however, a 12.5-V supply is needed for programming. All programming signals are TTL level. For programming outside the system, existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random. When programmed in blocks, the data is loaded into the EPROM cell one byte at a time, the high byte first and the low byte second.
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TMS320E25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
Figure 9 shows the wiring conversion to program the TMS320E25 using the 28-pin pinout of the TMS27C64. The pin nomenclature table provides a description of the TMS27C64 pins. The code to be programmed into the device should be serial mode. The TMS320E25 uses 13 address lines to address the 4K-word memory in byte format.
TMS27C64 VCC 28 PGM 27 26 25 24 23 22 21 20 19 18 17 16 15 EPT A8 A9 A11 G A10 E Q8 Q7 Q6 Q5 Q4
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 10 D7 D6 D5 D4 D3 D2 D1 D0 11 12 13 14 15 16 17 18 19 20 21 E EPT VPP A0 22 23 24 25 TMS320E25 68-Pin (FZ) 59 58 57 56 55 54 53 51 50 49 48 47 46 45
RS
44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 V SS A10 A12 A1 A2 A3 A4 A5 A6 A7 V CC A8 3.9 K A9 A11 PGM G
8
V PP
A12
Q1
Q2
TMS27C64
10
12
13
Q3
A7
A6
A5
A4
A3
A2
A1
A0
Pin Nomenclature (TMS320E25)
SIGNALS A12 (MSB) - A0 (LSB) CLIN E EPT G GND PGM Q8 (MSB) - Q1 (LSB) RS VCC VPP I/O I I I I I I I I/O I I I DEFINITION On-chip EPROM programming address lines Clock oscillator input EPROM chip select EPROM test mode select EPROM read/verify select Ground EPROM write/program select Data lines for byte-wide programming of on-chip 8K bytes of EPROM Reset for initializing the device 5-V power supply 12.5-V power supply
Figure 9. TMS320E25 EPROM Conversion to TMS27C64 EPROM Pinout
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14
11
1
2
3
4
5
6
7
8
9
GND
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ADVANCE INFORMATION
52
CLKIN
TMS320E25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
Table 5 shows the programming levels required for programming, verifying and reading the EPROM cell. The paragraphs following the table describe the function of each programming level. Table 5. TMS320E25 Programming Mode Levels
SIGNAL NAME E G PGM VPP VCC VSS CLKIN RS EPT Q1-Q8 TMS320E25 PIN 22 42 41 25 61,35 27,44,10 52 65 24 18-11 40-38 37,36,34 33 32 31 TMS27C64 PIN 20 22 27 1 28 14 14 14 26 11-13,15-19 2,23,21, 24,25,3 4 5 3 PROGRAM VIL VIH PULSE VPP VCC + 1 VSS VSS VSS VSS DIN ADDR ADDR ADDR ADDR ADDR PROGRAM VERIFY VIL PULSE VIH VPP VCC + 1 VSS VSS VSS VSS QOUT ADDR ADDR ADDR ADDR ADDR PROGRAM INHIBIT VIH X X VPP VCC + 1 VSS VSS VSS VSS HI-Z X X X X X X READ VIL PULSE VIH VCC VCC VSS VSS VSS VSS QOUT ADDR ADDR ADDR ADDR ADDR ADDR OUTPUT DISABLE VIL VIH VIH VCC VCC VSS VSS VSS VSS HI-Z X X X X X X
ADVANCE INFORMATION
A12-A10 A9-A7 A6 A5 A4
A3-A0 30-28,26 7-10 ADDR ADDR In accordance with TMS27C64. LEGEND; VIH = TTL high level; VIL = TTL low level; ADDR = byte address bit VPP = 12.5 V 0.5 V; VCC = 5 0.25 V; X = don't care PULSE = low-going TTL level pulse; DIN = byte to be programmed at ADDR QOUT = byte stored at ADDR; RBIT = ROM protect bit.
erasure Before programming, the device is erased by exposing the chip through the transparent lid to high-intensity ultraviolet light (wavelength 2537 A). The recommended minimum exposure dose (UV-intensity x exposure-time) is 15 W*s/cm2. A typical 12 mW/cm2, filterless UV lamp will erase the device in 21 minutes. The lamp should be located approximately 2.5 cm above the chip during erasure. After erasure, all bits are in the high state. Note that normal ambient light contains the correct wavelength for erasure. Therefore, when using the TMS320E25, the window should be covered with an opaque label. fast programming After erasure (all memory bits in the cell are logic one), logic zeroes are programmed into the desired locations. The fast programming algorithm, shown in Figure 10, is normally used to program the entire EPROM contents, although individual locations may be programmed separately. A programmed logic zero can be erased only by ultraviolet light. Data is presented in parallel (eight bits) on pins Q8-Q1. Once addresses and data are stable, PGM is pulsed. The programming mode is achieved when VPP = 12.5 V, PGM = VIL, VCC = 6 V, G = VIH, and E = VIL More than one TMS320E25 can be programmed when the devices are connected in parallel. Locations can be programmed in any order. Programming uses two types of programming pulses: prime and final. The length of the prime pulse is 1 ms. After each prime pulse, the byte being programmed is verified. If correct data is read, the final programming pulse is applied; if correct data is not read, an additional 1-ms prime pulse is applied up to a maximum of 15 times. The final programming pulse is 4 ms times the number of prime programming pulses applied. This sequence of programming and verification is performed at VCC = 6 V, and VPP = 12.5 V. When the full fast programming routine is complete, all bits are verified with VCC = VPP = 5 V.
60
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SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
program verify Programmed bits may be verified with VPP = 12.5 V when G = VIL, E = VIL, and PGM = VIH. Figure 11 shows the timing for the program and verify operation.
Start
Address = First Location
VCC = 6 0.25 V VPP = 12.5 V 0.25 V X=0
Increment X No Yes X = 25? Fail Verify One Byte Pass Program One Pulse of 3X-ms Duration
Device Failed
Last Address? Yes
No
Increment Address
VCC = VPP = 5 V 0.25 V
Fail
Compare All Bytes to Original Data Pass Device Passed
Figure 10. Fast Programming Flowchart
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ADVANCE INFORMATION
Program One 1-ms Pulse
TMS320E25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
Program
Verify VIH
A12-A0
Address Stable
Address N + 1 VIL VIH/VOH
Q8-Q1
Data In Stable
HI-Z
Data Out Valid VIL/VOL VPP
VPP VCC VCC + 1 VCC VCC
ADVANCE INFORMATION
VIH E VIL VIH PGM VIL VIH G VIL
Figure 11. Fast Programming Timing program inhibit Programming may be inhibited by maintaining a high level input on the E pin or PGM pin. read The EPROM contents may be read independent of the programming cycle, provided the RBIT (ROM protect bit) has not been programmed. The read is accomplished by setting E to zero and pulsing G low. The contents of the EPROM location selected by the value on the address inputs appear on Q8-Q1. output disable During the EPROM programming process, the EPROM data outputs may be disabled, if desired, by establishing the output disable state. This state is selected by setting the G and PGM pins high. While output disable is selected, Q8-Q1 are placed in the high-impedance state. ROM protection and verification This section describes the code protection feature included in the EPROM cell, which protects code against copyright violations. Table 6 shows the programming levels required for protecting and verifying the EPROM. The paragraphs following the table describe the protect and verify functions.
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SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
Table 6. TMS320E25 Protect and Verify EPROM Mode Levels
SIGNAL E G PGM VPP VCC VSS CLKIN RS EPT Q8-Q1 A12-A10 A9-A7 A6 A5 A4 A3-A0 TMS320E25 PIN 22 42 41 25 61,35 10, 27, 44 52 65 24 18-11 40-38 37, 36, 34 33 32 31 30-28, 26 TMS27C64 PIN 20 22 27 1 28 14 14 14 26 11-13, 15-19 2, 23, 21, 24, 25, 3 4 5 6 7-10 ROM PROTECT VIH VIH VIH VPP VCC + 1 VSS VSS VSS VPP Q8 = PULSE X X X X VIH X PROTECT VERIFY VIL VIL VIH VCC VCC VSS VSS VSS VPP Q8 = RBIT X X VIL X X X
In accordance with TMS27C64. LEGEND; VIH = TTL high level; VIL = TTL low level; VCC = 5 V 0.25 V VPP = 12.5 V 0.5 V; X = don't care PULSE = low-going TTL level pulse; RBIT = ROM protect bit.
EPROM protect The EPROM protect facility is used to completely disable reading of the EPROM contents to guarantee security of propietary algorithms. This facility is implemented through a unique EPROM cell called the RBIT (EPROM protect bit) cell. Once the contents to be protected are programmed into the EPROM, the RBIT is programmed, disabling access to the EPROM contents and disabling the microprocessor mode on the device. Once programmed, the RBIT can be cleared only by erasing the entire EPROM array with ultraviolet light, thereby maintaining security of the propietary algorithm. Programming the RBIT is accomplished using the EPROM protect cycle, which consists of setting the E, G, PGM, and A4 pins high, VPP and EPT to 2.5 V 0.5 V, and pulsing Q8 low. The complete sequence of operations involved in programming the RBIT is shown in the flowchart of Figure 12. The required setups in the figure are detailed in Table 6.
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ADVANCE INFORMATION
TMS320E25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
Start Program One Pulse of 3X-ms Duration
X=0
EPROM Protect Setup
Protect Verify Setup
Program One 1-ms Pulse Device Failed X=X+1 Verify RBIT Device Passed
Yes X = 25? No Protect Verify Setup
ADVANCE INFORMATION
protect verify
64
Fail
Verify RBIT Pass EPROM Protect Setup
Figure 12. EPROM Protect Flowchart
Protect verify is used following the EPROM protect to verify correct programming of the RBIT (see Figure 12). When using protect verify, Q8 outputs the state of the RBIT. When RBIT = 1, the EPROM is unprotected; when RBIT = 0, the EPROM is protected. The EPROM protect and verify timings are shown in Figure 13.
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TMS320E25
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
Protect Verify VIH A4 VIL VPP VPP VCC VCC + 1 VCC VIH VIL VIH VIL VIH G VIL VIH/VOH Q8 HI-Z HI-Z HI-Z VIL/VOL VPP EPT VSS VIH A6 VIL
VCC
PGM
Figure 13. EPROM Protect Timing
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ADVANCE INFORMATION
E
TMS320 SECOND-GENERATION DEVICES
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
INDEX
ADVANCE INFORMATION
66
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NIL NIL NIL
SPRS010B -- MAY 1987 -- REVISED NOVEMBER 1990
accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . adapter socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 58 10 5 5
microcomputer/microprocessor mode multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 multiprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 operation conditions TMS32020 . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 21 TMS320C25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TMS320C25-50 . . . . . . . . . . . . . . . . . . . . . . . . . 34 TMS320E25 . . . . . . . . . . . . . . . . . . . . . . . . . 27, 33 overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 overview TMS320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pin nomenclature TMS32020/C25/C25-50 . . . . . . . . . . . . . . . . . . . 2 TMS320E25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 pinouts TMS32020/C25/C25-50 . . . . . . . . . . . . . . . . . . . 1 TMS320E25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 programming levels for EPROM . . . . . . . . . . 58-65 repeat feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 reflow soldering precaution . . . . . . . . . . . . . . . . . . 54 serial port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 9 shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 specification overview . . . . . . . . . . . . . . . . . . . . . . 20 subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 supply current characteristics . . . . . . . . . . . . . . . . 54 switching characteristics TMS32020 . . . . . . . . . . . . . . . . . . . . . . . 21, 23-26 TMS320C25/E25 . . . . . . . . . . . . . . . . . . 27, 28-33 TMS320C25-50 . . . . . . . . . . . . . . . . . . . 34, 35-40 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 timing diagrams . . . . . . . . . . . . . . . . . . 41-53, 62, 65 TMS320 Second-Generation . . . . . . . . . . . 41-47 TMS32020 . . . . . . . . . . . . . . . . . . . 46, 48, 50, 51 TMS320C25/E25 . . . . . . . . . . . . . . 46, 49, 52, 53 TMS3220 product notification . . . . . . . . . . . . . 17
BIT instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bulletin board Service . . . . . . . . . . . . . . . . . . . . . . 18 clock TMS32020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 TMS320C25/E25 . . . . . . . . . . . . . . . . . . . . . 28, 29 TMS320C25-50 . . . . . . . . . . . . . . . . . . . . . . 35, 36 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 development support . . . . . . . . . . . . . . . . . . . . 18, 19 direct addressing . . . . . . . . . . . . . . . . . . . . . . . 10, 17 DMA documentation support . . . . . . . . . . . . . . . . 20 EPROM protection/verification . . . . . . . . . . . . 58-65 external interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 flowcharts EPROM protect . . . . . . . . . . . . . . . . . . . . . . . . . 63 fast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60, 61 hotline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 immediate addressing . . . . . . . . . . . . . . . . . . . . . . 10 indirect addressing . . . . . . . . . . . . . . . . . . . . . . 10, 17 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 key features TMS320 family . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 TMS32020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 TMS320C25/C25-50/E25 . . . . . . . . . . . . . . . . . . 4 mechanical data TMS32020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 TMS320C25 . . . . . . . . . . . . . . . . . . . . . . . . . 55, 56 TMS320C25-50 . . . . . . . . . . . . . . . . . . . . . . . . . 56 TMS320E25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 memory addressing modes . . . . . . . . . . . . . . . . . . . . 10, 17 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
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PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2005
PACKAGING INFORMATION
Orderable Device TMS320C25FNA TMS320C25FNAR TMS320C25FNL TMS320C25FNLR TMS320C25FNLW TMS320C25GBA TMS320C25GBL TMS320C25PHL
(1)
Status (1) NRND NRND NRND NRND OBSOLETE NRND NRND NRND
Package Type PLCC PLCC PLCC PLCC PLCC CPGA CPGA QFP
Package Drawing FN FN FN FN FN GB GB PH
Pins Package Eco Plan (2) Qty 68 68 68 68 68 68 68 80 21 21 66 18 250 18 250 TBD TBD TBD TBD TBD TBD TBD TBD
Lead/Ball Finish CU SNPB CU SNPB CU SNPB CU SNPB CU SNPB AU AU A42 SNPB
MSL Peak Temp (3) Level-3-220C-168HR Level-3-220C-168HR Level-3-220C-168HR Level-3-220C-168HR Level-3-220C-168HR Level-NC-NC-NC Level-NC-NC-NC Level-4-220C-72HR
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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