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19-3549; Rev 0; 2/05
KIT ATION EVALU BLE AVAILA
7.5Msps, Ultra-Low-Power Analog Front-End
General Description Features
Dual 10-Bit Rx ADC and Dual 10-Bit Tx DAC Ultra-Low Power 36.3mW at fCLK = 5.12Msps, Fast Mode 19.8mW at fCLK = 5.12Msps, Slow Mode Low Standby and Shutdown Current Integrated TD-SCDMA Filters with >55dB Stopband Rejection Excellent Dynamic Performance SINAD = 54.9dB at fIN = 1.87MHz (Rx ADC) SFDR = 76.5dBc at fOUT = 620kHz (Tx DAC) Excellent Gain/Phase Match 0.22 Phase, 0.02dB Gain (Rx ADC) at fIN = 1.87MHz at -0.5dBFS Three 12-Bit, 1s Aux-DACs Single-Supply Operation Multiplexed Parallel Digital I/O Serial-Interface Control Versatile Power-Control Circuits Shutdown, Standby, Idle, Tx-Rx Disable Miniature 48-Pin Thin QFN Package (7mm x 7mm x 0.8mm)
MAX19700
The MAX19700 is an ultra-low-power, mixed-signal analog front-end (AFE) designed for TD-SCDMA handsets and data cards. Optimized for high dynamic performance at ultra-low power, the MAX19700 integrates a dual 10-bit, 7.5Msps receive (Rx) ADC, dual 10-bit, 7.5Msps transmit (Tx) DAC with TD-SCDMA baseband filters, and three fast-settling 12-bit aux-DAC channels for ancillary RF front-end control. The typical operating power in Tx-Rx FAST mode is 36.3mW at a 5.12Msps clock frequency. The Rx ADCs feature 54.9dB SINAD and 78dBc SFDR at a 1.87MHz input frequency with a 7.5Msps sample frequency. The analog I/Q input amplifiers are fully differential and accept 1.024V P-P full-scale signals. Typical I/Q channel matching is 0.22 phase and 0.02dB gain. The Tx DACs with TD-SCDMA lowpass filters feature -3dB cutoff frequency of 1.27MHz and >55dB stopband rejection at fIMAGE = 4.32MHz. The analog I/Q full-scale output voltage range is selectable at 410mV or 500mV. The output common-mode voltage is selectable from 0.9V to 1.4V and the I/Q channel offset is adjustable. The typical I/Q channel matching is 0.05dB gain and 0.16 phase. The Rx ADC and Tx DAC share a single, 10-bit parallel, high-speed digital bus allowing half-duplex operation for time-division duplex (TDD) applications. A 3-wire serial interface controls power-management modes and the aux-DAC channels. The MAX19700 operates on a single +2.7V to +3.3V analog supply and +1.8V to +3.3V digital I/O supply. The MAX19700 is specified for the extended (-40C to +85C) temperature range and is available in a 48-pin, thin QFN package.
Pin Configuration
VDD DAC1
39 38
48
47
46
45
44
43
42
41
40
37 36 35 34 33 32 31 30 29 28
DAC2
REFN
QDP QDN VDD
GND IDP IDN
TOP VIEW
COM REFIN
Applications
TD-SCDMA Handsets TD-SCDMA Data Cards Portable Communication Equipment
REFP VDD IAP IAN GND CLK GND VDD QAN QAP VDD GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
DAC3 N.C. N.C. VDD GND VDD CS SCLK DIN T/R DR SHDN
Ordering Information
PART* MAX19700ETM MAX19700ETM+ PIN-PACKAGE 48 Thin QFN-EP** 48 Thin QFN-EP** PKG CODE T4877-4 T4877-4
MAX19700
EXPOSED PADDLE (GND)
27 26 25
*All devices are specified over the -40C to +85C operating range. **EP = Exposed paddle. +Denotes lead-free package. Functional Diagram appears at end of data sheet.
D1 D2 D3 D4 D5 OGND
OVDD D6
D0
THIN QFN
________________________________________________________________ Maxim Integrated Products
D7 D8 D9
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
ABSOLUTE MAXIMUM RATINGS
VDD to GND, OVDD to OGND ..............................-0.3V to +3.4V GND to OGND.......................................................-0.3V to +0.3V IAP, IAN, QAP, QAN, IDP, IDN, QDP, QDN, REFP, REFN, REFIN, COM, DAC1, DAC2, DAC3 to GND .................-0.3V to (VDD + 0.3V) D0-D9, DR, T/R, SHDN, SCLK, DIN, CS, CLK to OGND .....................................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 48-Pin Thin QFN (derate 26.3mW/C above +70C) .......2.1W Thermal Resistance JA ..................................................38C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F. Typical values are at TA = +25C, unless otherwise noted. CL < 5pF on all aux-DAC outputs.) (Note 1)
PARAMETER POWER REQUIREMENTS Analog Supply Voltage Output Supply Voltage VDD OVDD Ext1-Tx, Ext3-Tx, and SPI2-Tx states; transmit DAC operating mode (Tx), fCLK = 5.12MHz, fOUT = 620kHz on both channels; aux-DACs ON and at midscale Ext2-Tx, Ext4-Tx, and SPI4-Tx states; transmit DAC operating mode (Tx), fCLK = 5.12MHz, fOUT = 620kHz on both channels; aux-DACs ON and at midscale Ext1-Rx, Ext4-Rx, and SPI3-Rx states; receive ADC operating mode (Rx), fCLK = 5.12MHz, fIN = 1.87MHz on both channels; aux-DACs ON and at midscale VDD Supply Current Ext2-Rx, Ext3-Rx, and SPI1-Rx modes; receive ADC operating mode (Rx), fCLK = 5.12MHz, fIN = 1.87MHz on both channels; aux-DACs ON and at midscale Ext2-Tx, Ext4-Tx, and SPI4-Tx modes; transmit DAC operating mode (Tx), fCLK = 7.5MHz, fOUT = 620kHz on both channels; aux-DACs ON and at midscale Ext1-Tx, Ext3-Tx, and SPI2-Tx modes; transmit DAC operating mode (Tx), fCLK = 7.5MHz, fOUT = 620kHz on both channels; aux-DACs ON and at midscale 6.6 2.7 1.8 3.0 3.3 VDD V V SYMBOL CONDITIONS MIN TYP MAX UNITS
10.3
12.4
12.1 mA
13.1
16
10.4
2
_______________________________________________________________________________________
7.5Msps, Ultra-Low-Power Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F. Typical values are at TA = +25C, unless otherwise noted. CL < 5pF on all aux-DAC outputs.) (Note 1)
PARAMETER SYMBOL CONDITIONS Ext1-Rx, Ext4-Rx, and SPI3-Rx modes; receive ADC operating mode (Rx), fCLK = 7.5MHz, fIN = 1.87MHz on both channels; aux-DACs ON and at midscale Ext2-Rx, Ext3-Rx, and SPI1-Rx modes; receive ADC operating mode (Rx), fCLK = 7.5MHz, fIN = 1.87MHz on both channels; aux-DACs ON and at midscale Standby mode, CLK = 0 or OVDD; aux-DACs ON and at midscale Idle mode, fCLK = 7.5MHz; aux-DACs ON and at midscale Shutdown mode, CLK = 0 or OVDD Ext1-Rx, Ext2-Rx, Ext3-Rx, Ext4-Rx, SPI1-Rx, SPI3-Rx modes; receive ADC operating mode (Rx), fCLK = 7.5MHz, fIN = 1.87MHz on both channels; aux-DACs ON and at midscale Ext1-Tx, Ext2-Tx, Ext3-Tx, Ext4-Tx, SPI2-Tx, SPI4-Tx modes; transmit DAC operating mode (Tx), fCLK = 7.5MHz, fOUT = 620kHz; aux-DACs ON and at midscale Idle mode, fCLK = 7.5MHz; aux-DACs ON and at midscale Shutdown mode, CLK = 0 or OVDD Standby mode, CLK = 0 or OVDD; aux-DACs ON and at midscale Rx ADC DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error DC Gain Matching Offset Matching Gain Temperature Coefficient Power-Supply Rejection PSRR Offset error (VDD 5%) Gain error (VDD 5%) INL DNL Residual DC offset error Include reference error 10 0.85 0.55 0.5 1.1 0.01 4.5 15.7 0.2 0.04 5 5 0.25 Bits LSB LSB %FS %FS dB LSB ppm/C LSB %FS MIN TYP MAX UNITS
MAX19700
12.8
16
VDD Supply Current
7
mA
2.7 4.7 0.7
4 6 A
1.38
mA
OVDD Supply Current
72.9
10.9 0.01 0.03
A
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3
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F. Typical values are at TA = +25C, unless otherwise noted. CL < 5pF on all aux-DAC outputs.) (Note 1)
PARAMETER Rx ADC ANALOG INPUT Input Differential Range Input Common-Mode Voltage Range Input Impedance Rx ADC CONVERSION RATE Maximum Clock Frequency Data Latency (Figure 3) Rx ADC DYNAMIC CHARACTERISTICS (Note 3) Signal-to-Noise Ratio Signal-to-Noise Plus Distortion Spurious-Free Dynamic Range Third-Harmonic Distortion Intermodulation Distortion Third-Order Intermodulation Distortion Total Harmonic Distortion Aperture Delay Overdrive Recovery Time Rx ADC INTERCHANNEL CHARACTERISTICS Crosstalk Rejection Amplitude Matching Phase Matching fINX,Y = 1.875MHz at -0.5dBFS, fINX,Y = 1MHz at -0.5dBFS (Note 4) fIN = 1.875MHz at -0.5dBFS (Note 5) fIN = 1.875MHz at -0.5dBFS (Note 5) -85 0.02 0.22 dB dB Degrees 1.5x full-scale input SNR SINAD SFDR HD3 IMD IM3 THD fIN = 1.875MHz, fCLK = 7.5MHz fIN = 3.5MHz, fCLK = 7.5MHz fIN = 1.875MHz, fCLK = 7.5MHz fIN = 3.5MHz, fCLK = 7.5MHz fIN = 1.875MHz, fCLK = 7.5MHz fIN = 3.5MHz, fCLK = 7.5MHz fIN = 1.875MHz, fCLK = 7.5MHz fIN = 3.5MHz, fCLK = 7.5MHz f1 = 1.8MHz, -7dBFS; f2 = 1MHz, -7dBFS f1 = 1.8MHz, -7dBFS; f2 = 1MHz, -7dBFS fIN = 1.875MHz, fCLK = 7.5MHz fIN = 3.5MHz, fCLK = 7.5MHz 66 53.6 53.7 55 54.8 54.9 54.7 78 70.1 -84 -72.1 -75.6 -78 -77.9 -71 3.5 2 -64 dB dB dBc dBc dBc dBc dBc ns ns fCLK (Note 2) Channel I Channel Q 5 5.5 7.5 MHz Clock Cycles VID VCM RIN CIN Switched capacitor load Differential or single-ended inputs 0.512 VDD / 2 720 5 V V k pF SYMBOL CONDITIONS MIN TYP MAX UNITS
4
_______________________________________________________________________________________
7.5Msps, Ultra-Low-Power Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F. Typical values are at TA = +25C, unless otherwise noted. CL < 5pF on all aux-DAC outputs.) (Note 1)
PARAMETER Tx DAC DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Residual DC Offset Full-Scale Gain Error TRANSMIT-PATH DYNAMIC PERFORMANCE Corner Frequency Passband Ripple Group Delay Variation in Passband Error-Vector Magnitude Stopband Rejection EVM 3dB corner DC to 640kHz (Note 6) DC to 640kHz, guaranteed by design DC to 700kHz fIMAGE = 4.32MHz, fOUT = 800kHz, fCLK = 5.12MHz 2MHz 4MHz Baseband Attenuation Spot relative to 100kHz 5MHz 10MHz 20MHz DAC Conversion Rate In-Band Noise Density Third-Order Intermodulation Distortion Glitch Impulse Spurious-Free Dynamic Range to Nyquist Total Harmonic Distortion to Nyquist Signal-to-Noise Ratio to Nyquist SFDR THD SNR fCLK = 7.5MHz, fOUT = 620kHz fCLK = 7.5MHz, fOUT = 620kHz fCLK = 7.5MHz, fOUT = 620kHz 60 fCLK ND IM3 (Note 2) fOUT = 620kHz, fCLK = 5.12MHz, offset = 500kHz f1 = 620kHz, f2 = 640kHz -121.7 76 10 76.5 -74.8 57.1 -59 55 20 46.5 54.7 81 88 7.5 MHz dBc/Hz dBc pV*s dBc dB dB dB 1.1 1.27 0.28 50 2 1.5 0.5 100 MHz dBP-P ns % dBc N INL DNL VOS Guaranteed monotonic (Note 6) TA > +25C TA < +25C Include reference error (peak-to-peak error) -4 -6.5 -50 10 0.45 0.26 1 1 +4 mV +6.5 +50 mV Bits LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX19700
_______________________________________________________________________________________
5
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F. Typical values are at TA = +25C, unless otherwise noted. CL < 5pF on all aux-DAC outputs.) (Note 1)
PARAMETER I-to-Q Output Isolation Gain Mismatch Between DAC Outputs Phase Mismatch Between DAC Outputs Differential Output Impedance TRANSMIT-PATH ANALOG OUTPUT Full-Scale Output Voltage (Table 6) VFS Bit E7 = 0 (default) Bit E7 = 1 Bits CM1 = 0, CM0 = 0 (default) Output Common-Mode Voltage (Table 8) Bits CM1 = 0, CM0 = 1 Bits CM1 = 1, CM0 = 0 Bits CM1 = 1, CM0 = 1 RECEIVE TRANSMIT-PATH INTERCHANNEL CHARACTERISTICS Receive Transmit Isolation AUXILIARY DACs (DAC1, DAC2, DAC3) Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Zero-Code Error Output-Voltage Low Output-Voltage High DC Output Impedance Settling Time Glitch Impulse Rx ADC-Tx DAC TIMING CHARACTERISTICS CLK Rise to Channel-I Output Data Valid CLK Fall to Channel-Q Output Data Valid CLK Rise/Fall to DR Rise/Fall Time I-DAC DATA to CLK Fall Setup Time tDOI tDOQ tDR tDSI Figure 3 (Note 6) Figure 3 (Note 6) Figure 3 (Note 6) Figure 5 (Note 6) 10 6.9 9.3 8.5 10 13 12 ns ns ns ns VOL VOH RL > 200k RL > 200k DC output at midscale From 1/4 FS to 3/4 FS From 0 to FS transition 2.56 4 1 24 INL DNL GE Guaranteed monotonic over codes 100 to 4000 (Note 6) RL > 200k (Note 6) 12 1.25 0.65 0.7 0.6 0.1 Bits LSB LSB %FS %FS V V s nV*s ADC fINI = fINQ = 1.875MHz, DAC fOUTI = fOUTQ = 620kHz, fCLK = 7.5MHz 85 dB 1.32 410 500 1.4 1.25 1.1 0.9 1.48 V mV SYMBOL CONDITIONS fOUTx,Y = 500kHz, fOUTx,Y = 620kHz Measured at DC fOUT = 620kHz, fCLK = 7.5MHz -0.3 MIN TYP 85 0.05 0.16 800 +0.3 MAX UNITS dB dB Degrees
TRANSMIT-PATH INTERCHANNEL CHARACTERISTICS
6
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7.5Msps, Ultra-Low-Power Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F. Typical values are at TA = +25C, unless otherwise noted. CL < 5pF on all aux-DAC outputs.) (Note 1)
PARAMETER Q-DAC DATA to CLK Rise Setup Time CLK Fall to I-DAC Data Hold Time CLK Rise to Q-DAC Data Hold Time CLK Duty Cycle CLK Duty-Cycle Variation Digital Output Rise/Fall Time Falling Edge of CS to Rising Edge of First SCLK Time DIN to SCLK Setup Time DIN to SCLK Hold Time SCLK Pulse-Width High SCLK Pulse-Width Low SCLK Period SCLK to CS Setup Time CS High Pulse Width 20% to 80% SERIAL-INTERFACE TIMING CHARACTERISTICS (Figure 6, Note 6) tCSS tDS tDH tCH tCL tCP tCS tCSW From shutdown to Rx mode, ADC settles to within 1dB SINAD Shutdown Wake-Up Time tWAKE,SD From shutdown to Tx mode, DAC settles to within 10 LSB error From idle to Rx mode with CLK present during idle, ADC settles to within 1dB SINAD Idle Wake-Up Time (With CLK) tWAKE,ST0 From idle to Tx mode with CLK present during idle, DAC settles to 10 LSB error From standby to Rx mode, ADC settles to within 1dB SINAD Standby Wake-Up Time tWAKE,ST1 From standby to Tx mode, DAC settles to 10 LSB error 10 10 0 25 25 50 10 80 ns ns ns ns ns ns ns ns SYMBOL tDSQ tDHI tDHQ CONDITIONS Figure 5 (Note 6) Figure 5 (Note 6) Figure 5 (Note 6) MIN 10 0 0 50 15 2.3 TYP MAX UNITS ns ns ns % % ns
MAX19700
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 7) 75 s 25 7.3 s 5 7.3 s 25
Enable Time from Tx to Rx, (Ext2Tx to Ext2-Rx, Ext4-Tx to Ext4-Rx, and SPI4-Tx to SPI3-Rx Modes) Enable Time from Rx to Tx, (Ext1Rx to Ext1-Tx, Ext4-Rx to Ext4-Tx, and SPI3-Rx to SPI4-Tx Modes)
tENABLE, RX ADC settles to within 1dB SINAD
500
ns
tENABLE, TX DAC settles to within 10 LSB error
1
s
_______________________________________________________________________________________
7
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F. Typical values are at TA = +25C, unless otherwise noted. CL < 5pF on all aux-DAC outputs.) (Note 1)
PARAMETER Enable Time from Tx to Rx, (Ext1Tx to Ext1-Rx, Ext3-Tx to Ext3-Rx, and SPI2-Tx to SPI1-Rx Modes) Enable Time from Rx to Tx, (Ext2Rx to Ext2-Tx, Ext3-Rx to Ext3-Tx, and SPI1-Rx to SPI2-Tx Modes) SYMBOL CONDITIONS MIN TYP 7.3 MAX UNITS s
tENABLE, RX ADC settles to within 1dB SINAD
tENABLE,TX
DAC settles to within 10 LSB error
5
s
INTERNAL REFERENCE (REFIN = VDD; VREFP, VREFN, VCOM levels are generated internally) Positive Reference Negative Reference Common-Mode Output Voltage Maximum REFP/REFN/COM Source Current Maximum REFP/REFN/COM Sink Current Differential Reference Output Differential Reference Temperature Coefficient Reference Input Voltage Differential Reference Output Common-Mode Output Voltage Maximum REFP/REFN/COM Source Current Maximum REFP/REFN/COM Sink Current REFIN Input Current REFIN Input Resistance DIGITAL INPUTS (CLK, SCLK, DIN, CS, D0-D9, T/R, SHDN) Input High Threshold Input Low Threshold Input Leakage Input Capacitance VINH VINL DIIN DCIN D0-D9, CLK, SCLK, DIN, CS, T/R, SHDN D0-D9, CLK, SCLK, DIN, CS, T/R, SHDN D0-D9, CLK, SCLK, DIN, CS, T/R, SHDN = OGND or OVDD -1 5 0.7 x OVDD 0.3 x OVDD +1 V V A pF VCOM ISOURCE ISINK VREF REFTC VREFP - VREFN +0.490 VREFP - VCOM VREFN - VCOM 0.256 -0.256 VDD / 2 VDD / 2 VDD / 2 - 0.15 + 0.15 2 2 +0.512 10 +0.534 V V V mA mA V ppm/C
BUFFERED EXTERNAL REFERENCE (external REFIN = 1.024V applied; VREFP, VREFN, VCOM levels are generated internally) VREFIN VDIFF VCOM ISOURCE ISINK VREFP - VREFN 1.024 0.512 VDD / 2 2 2 -0.7 500 V V V mA mA A k
8
_______________________________________________________________________________________
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F. Typical values are at TA = +25C, unless otherwise noted. CL < 5pF on all aux-DAC outputs.) (Note 1)
PARAMETER DIGITAL OUTPUTS (D0-D9, DR) Output-Voltage Low Output-Voltage High Tri-State Leakage Current Tri-State Output Capacitance VOL VOH ILEAK COUT ISINK = 200A ISOURCE = 200A 0.8 x OVDD -1 5 +1 0.2 x OVDD V V A pF SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: Specifications from TA = +25C to +85C are guaranteed by production tests. Specifications from TA = +25C to -40C are guaranteed by design and characterization. Note 2: The minimum clock frequency for the MAX19700 is 2MHz. Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude of the digital outputs. SINAD and THD are calculated using HD2 through HD6. Note 4: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second channel FFT test tone. Note 5: Amplitude and phase matching is measured by applying the same signal to each channel, and comparing the two output signals using a sine-wave fit. Note 6: Guaranteed by design and characterization.
Typical Operating Characteristics
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 7.5MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F, TA = +25C, unless otherwise noted.)
Rx ADC CHANNEL-IA FFT PLOT
MAX19700 toc01
Rx ADC CHANNEL-QA FFT PLOT
MAX19700 toc02
Rx ADC CHANNEL-IA TWO-TONE FFT PLOT
-10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 fCLK = 7.5MHz f1 = 2.0MHz f2 = 2.1MHz AIA = -7dBFS PER TONE 8192-POINT DATA RECORD f1
MAX19700 toc03
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 0
AMPLITUDE (dBFS)
fCLK = 7.5MHz fIA = 2MHz AIA = -0.5dBFS 8192-POINT DATA RECORD
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
IA
fCLK = 7.5MHz fQA = 2MHz AQA = -0.5dBFS 8192-POINT DATA RECORD
0
QA
f2
HD3
HD2
HD3
HD2
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
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9
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 7.5MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F, TA = +25C, unless otherwise noted.)
Rx ADC CHANNEL-QA TWO-TONE FFT PLOT
MAX19700 toc04
Rx ADC SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
MAX19700 toc05
Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. ANALOG INPUT FREQUENCY
MAX19700 toc06
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 0
f2 f1
IA 51 49 47 45
SINAD (dB)
SNR (dB)
fCLK = 7.5MHz f1 = 2.0MHz f2 = 2.1MHz AQA = -7dBFS PER TONE 8192-POINT DATA RECORD
57 55 53 QA
57 55 53 IA 51 49 47 45 QA
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
10 20 30 40 50 60 70 80 90 100 ANALOG INPUT FREQUENCY (MHz)
0
10 20 30 40 50 60 70 80 90 100 ANALOG INPUT FREQUENCY (MHz)
FREQUENCY (MHz)
Rx ADC TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX19700 toc07
Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
MAX19700 toc08
Rx ADC SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT AMPLITUDE
fIN = 1.9980913MHz 50 IA 40 SNR (dB) 30 20 QA
MAX19700 toc09
-66 -68 -70 -72 -74 -76 -78 -80 0
60
79 IA 77 75 SFDR (dBc) 73 71 69 67 65 QA
THD (dB)
10 0 0 10 20 30 40 50 60 70 80 90 100 ANALOG INPUT FREQUENCY (MHz) -23 -18 -13 -8 -3 ANALOG INPUT AMPLITUDE (dBFS)
10 20 30 40 50 60 70 80 90 100 ANALOG INPUT FREQUENCY (MHz)
Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. ANALOG INPUT AMPLITUDE
MAX19700 toc10
Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT AMPLITUDE
MAX19700 toc11
Rx ADC SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE
IA 54.8 54.6 54.4 SNR (dB) 54.2 54.0 53.8 53.6 53.4 53.2 53.0 fIN = 1.9980913MHz 2 3 4 5 6 7 QA
MAX19700 toc12
60 fIN = 1.9980913MHz 50 IA 40 30 QA 20 10 0 -23 -18 -13 -8 -3 ANALOG INPUT AMPLITUDE (dBFS) SINAD (dB)
80 fIN = 1.9980913MHz 75 70 SFDR (dBc) 65 60 55 50 45 40 -23 -18 -13 -8 -3 ANALOG INPUT AMPLITUDE (dBFS) QA IA
55.0
SAMPLING RATE (MHz)
10
______________________________________________________________________________________
7.5Msps, Ultra-Low-Power Analog Front-End
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 7.5MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F, TA = +25C, unless otherwise noted.) Rx ADC SPURIOUS-FREE DYNAMIC RANGE Rx ADC SIGNAL-TO-NOISE AND DISTORTION Rx ADC SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE RATIO vs. SAMPLING RATE vs. CLOCK DUTY CYCLE
MAX19700 toc13 MAX19700 toc14
MAX19700
54.8 54.6 54.4 SINAD (dB) 54.2 54.0 53.8 53.6 53.4 53.2 53.0 2 IA
fIN = 1.9980913MHz 80 IA
QA
56.5 56.0 55.5
fIN = 1.9980913MHz
SFDR (dBc)
QA 70
SNR (dB)
75
55.0 54.5 54.0 53.5
IA
QA
65 fIN = 1.9980913MHz 3 4 5 6 7
53.0 52.5
60 2 3 4 5 6 7 SAMPLING RATE (MHz)
52.0 35 40 45 50 55 60 65 CLOCK DUTY CYCLE (%)
SAMPLING RATE (MHz)
Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. CLOCK DUTY CYCLE
MAX19700 toc16
Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK DUTY CYCLE
MAX19700 toc17
Rx ADC OFFSET ERROR vs. TEMPERATURE
MAX19700 toc18
57.0 56.5 56.0 55.5 55.0 54.5 54.0 53.5 53.0 52.5 52.0 35 40 45 50 55 60 QA fIN = 1.9980913MHz
80 79 78 77 SFDR (dBc) fIN = 1.9980913MHz QA
1.2 1.0 OFFSET ERROR (%FS) 0.8 0.6 0.4 0.2 0
SINAD (dB)
IA
76 75 74 73 72 71 70 IA
65
35
40
45
50
55
60
65
-40
-20
0
20
40
60
80
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
TEMPERATURE (C)
Rx ADC GAIN ERROR vs. TEMPERATURE
MAX19700 toc19
Tx PATH SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE
76 75 74 SFDR (dBc) 73 72 71 70 69 68 67 SFDR (dBc) fOUT = fCLK / 10
MAX19700 toc20
Tx PATH SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY
77 76 75 74 73 72 71 70
MAX19700 toc21
1.0 0.9 0.8 GAIN ERROR (%FS) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -40 -20 0 20 40 60 80 TEMPERATURE (C)
77
78
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 SAMPLING RATE (MHz)
200
300
400
500
600
700
800
OUTPUT FREQUENCY (kHz)
______________________________________________________________________________________
11
MAX19700 toc15
55.0
85
57.0
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 7.5MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F, TA = +25C, unless otherwise noted.)
Tx PATH SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT AMPLITUDE
MAX19700 toc22
Tx PATH CHANNEL-ID SPECTRAL PLOT
MAX19700 toc23
Tx PATH CHANNEL-ID SPECTRAL PLOT WITH IMAGE REJECTION
fID = 800kHz, fCLK = 5.12Msps -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 IMAGE REJECTION
MAX19700 toc24 MAX19700toc30 MAX19700 toc27
80 75 70 65 SFDR (dBc) 60 55 50 45 40 35 30
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90
fOUT = 620kHz
fID = 620kHz
0
-30
-25
-20
-15
-10
-5
0
0.2
1.2
2.2
3.2
0.5
1.5
2.5
3.5
4.5
OUTPUT AMPLITUDE (dBFS)
FREQUENCY (MHz)
FREQUENCY (MHz)
Tx PATH CHANNEL-QD SPECTRAL PLOT
MAX19700 toc25
Tx PATH CHANNEL-ID TWO-TONE SPECTRAL PLOT
-10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 f1 = 600kHz, f2 = 800kHz f1 f2
MAX19700 toc26
Tx PATH CHANNEL-QD TWO-TONE SPECTRAL PLOT
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 f1 f2 f1 = 600kHz, f2 = 800kHz
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 0.2 1.2 2.2
fQD = 620kHz
0
3.2
0.2
1.2
2.2
3.2
0.2
1.2
2.2
3.2
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
SUPPLY CURRENT vs. SAMPLING RATE
MAX19700 toc28
Rx ADC INTEGRAL NONLINEARITY
MAX19700 toc29
TRANSMIT FILTER FREQUENCY RESPONSE
0 -20 AMPLITUDE (dB)
12.6 Ext4-Rx MODE 12.4 SUPPLY CURRENT (mA) 12.2
1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
12.0 11.8 11.6 11.4 11.2 11.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 SAMPLING RATE (MHz) IVDD
-40
-60 -80 -100
0
128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE
0.1
1 FREQUENCY (MHz)
10
12
______________________________________________________________________________________
7.5Msps, Ultra-Low-Power Analog Front-End
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 7.5MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33F, TA = +25C, unless otherwise noted.)
Tx PATH INTEGRAL NONLINEARITY
MAX19700 toc31
MAX19700
Tx PATH DIFFERENTIAL NONLINEARITY
MAX19700 toc32
REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE
MAX19700 toc33
1.0 0.8 0.6 0.4
0.3 0.2 0.1 DNL (LSB) 0 -0.1 -0.2 -0.3
0.520
0.515 VREFP - VREFN (V) 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE
INL (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE
0.510
0.505
0.500 -40 -20 0 20 40 60 80 TEMPERATURE (C)
TRANSMIT FILTER PASSBAND RIPPLE
MAX19700 toc34
AUX-DAC INTEGRAL NONLINEARITY
MAX19700 toc35
AUX-DAC DIFFERENTIAL NONLINEARITY
0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8
MAX19700 toc36
0.04 0.02 0 AMPLITUDE (dB) -0.02 -0.04 -0.06 -0.08 -0.10 -0.12 -0.14 0 0.3 0.6 0.9 1.2 FREQUENCY (MHz)
2.0 1.5 1.0 INL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 0 1024 2048 3072
0.8
4096
0
1024
2048
3072
4096
DIGITAL INPUT CODE
DIGITAL INPUT CODE
______________________________________________________________________________________
13
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
Pin Description
PIN 1 2, 8, 11, 31, 33, 39 43 3 4 5, 7, 12, 32, 42 6 9 10 13-18, 21-24 19 20 25 26 27 28 29 30 34, 35 36 37 38 40, 41 44, 45 46 47 48 -- NAME REFP VDD IAP IAN GND CLK QAN QAP D0-D9 OGND OVDD SHDN DR T/R DIN SCLK CS N.C. DAC3 DAC2 DAC1 IDN, IDP QDN, QDP REFIN COM REFN EP FUNCTION Upper Reference Voltage. Bypass with a 0.33F capacitor to GND as close to REFP as possible. Analog Supply Voltage. Bypass VDD to GND with a combination of a 2.2F capacitor in parallel with a 0.1F capacitor. Channel IA Positive Analog Input. For single-ended operation, connect signal source to IAP. Channel IA Negative Analog Input. For single-ended operation, connect IAN to COM. Analog Ground. Connect all GND pins to ground plane. Conversion Clock Input. Clock signal for both receive ADCs and transmit DACs. Channel QA Negative Analog Input. For single-ended operation, connect QAN to COM. Channel QA Positive Analog Input. For single-ended operation, connect signal source to QAP. Digital I/O. Outputs for receive ADC in Rx mode. Inputs for transmit DAC in Tx mode. D9 is the most significant bit (MSB) and D0 is the least significant bit (LSB). Output-Driver Ground Output-Driver Power Supply. Supply range from +1.8V to VDD to accommodate most logic levels. Bypass OVDD to OGND with a combination of a 2.2F capacitor in parallel with a 0.1F capacitor. Active-Low Shutdown Input. Apply logic-low to place the MAX19700 in shutdown. Data-Ready Indicator. This digital output indicates channel I data (DR = 1) or channel Q data (DR = 0) is present on the output. Transmit- or Receive-Mode Select Input. T/R logic-low input sets the device in receive mode. A logic-high input sets the device in transmit mode. 3-Wire Serial-Interface Data Input. Data is latched on the rising edge of the SCLK. 3-Wire Serial-Interface Clock Input 3-Wire Serial-Interface Chip-Select Input. Logic-low enables the serial interface. No Connection Analog Output for Auxiliary DAC3 Analog Output for Auxiliary DAC2 Analog Output for Auxiliary DAC1 (AFC DAC, VOUT = 1.1V During Power-Up) DAC Channel-ID Differential Voltage Output DAC Channel-QD Differential Voltage Output Reference Input. Connect to VDD for internal reference. Common-Mode Voltage I/O. Bypass COM to GND with a 0.33F capacitor. Negative Reference I/O. Conversion range is (VREFP - VREFN). Bypass REFN to GND with a 0.33F capacitor. Exposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.
Detailed Description
The MAX19700 integrates a dual 10-bit Rx ADC and a dual 10-bit Tx DAC with TD-SCDMA baseband filters while providing ultra-low power and high dynamic performance at a 7.5Msps conversion rate. The Rx ADC analog input amplifiers are fully differential and accept 1VP-P full-scale signals. The Tx DAC analog outputs are fully differential with 410mV full-scale output, selectable common-mode range and offset adjust.
14
The MAX19700 includes a 3-wire serial interface to control operating modes and power management. The serial interface is SPITM and MICROWIRETM compatible. The MAX19700 serial interface selects shutdown, idle, standby, transmit (Tx), and receive (Rx) modes.
SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
______________________________________________________________________________________
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
INTERNAL BIAS S2a C1a S4a IAP C2a S4c S1 OUT S4b C2b C1b S3b S2b INTERNAL BIAS INTERNAL BIAS S2a C1a S4a QAP C2a S4c S1 OUT S4b C2b C1b S3b S2b INTERNAL BIAS S5b COM OUT S5b COM HOLD TRACK HOLD TRACK CLK INTERNAL NONOVERLAPPING CLOCK SIGNALS OUT COM S5a S3a
IAN
COM S5a S3a
MAX19700
QAN
Figure 1. MAX19700 Rx ADC Internal T/H Circuits
To operate the device in TDD applications, configure the MAX19700 for Tx or Rx mode with the 3-wire serial interface. The Rx ADC and Tx DAC share a common digital bus to reduce the digital I/O to a single 10-bit parallel multiplexed bus.
Dual 10-Bit Rx ADC
The ADC uses a seven-stage, fully differential, pipelined architecture that allows for high-speed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. Including the delay through the
output latch, the total clock-cycle latency is 5 clock cycles for channel IA and 5.5 clock cycles for channel QA. The ADC full-scale analog input range is VREF with a VDD / 2 0.2V common-mode input range. VREF is the difference between VREFP and VREFN. See the Reference Configurations section for details. Input Track-and-Hold (T/H) Circuits Figure 1 displays a simplified diagram of the Rx ADC input track-and-hold (T/H) circuitry. Both ADC inputs (IAP, QAP, IAN, and QAN) can be driven either differentially or single-ended. Match the impedance of IAP
______________________________________________________________________________________
15
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
Table 1. Output Codes vs. Input Voltage
DIFFERENTIAL INPUT VOLTAGE VREF x 512/512 VREF x 511/512 VREF x 1/512 VREF x 0/512 -VREF x 1/512 -VREF x 511/512 -VREF x 512/512 DIFFERENTIAL INPUT (LSB) 511 (+Full Scale - 1 LSB) 510 (+Full Scale - 2 LSB) +1 0 (Bipolar Zero) -1 -511 (-Full Scale +1 LSB) -512 (-Full Scale) OFFSET BINARY (D0-D9) 11 1111 1111 11 1111 1110 10 0000 0001 10 0000 0000 01 1111 1111 00 0000 0001 00 0000 0000 OUTPUT DECIMAL CODE 1023 1022 513 512 511 1 0
and IAN, as well as QAP and QAN, and set the input signal common-mode voltage within the ADC range of VDD / 2 (200mV) for optimum performance. ADC System Timing Requirements Figure 3 shows the relationship between the clock, analog inputs, DR indicator, and the resulting output data. Channel I (CHI) and channel Q (CHQ) are sampled on the rising edge of the clock signal (CLK) and the resulting data is multiplexed at the D0-D9 outputs. CHI data is updated on the rising edge and CHQ data is updated on the falling edge of the CLK. The DR indicator follows CLK with a typical delay time of 8.5ns and remains high when CHI data is updated and low when CHQ data is updated. Including the delay through the output
latch, the total clock-cycle latency is 5 clock cycles for CHI and 5.5 clock cycles for CHQ. Digital Input/Output Data (D0-D9) D0-D9 are the Rx ADC digital logic outputs when the MAX19700 is in receive mode. This bus is shared with the Tx DAC digital logic inputs and operates in halfduplex mode. D0-D9 are the Tx DAC digital logic inputs when the MAX19700 is in transmit mode. The logic level is set by OVDD from 1.8V to VDD. The digital output coding is offset binary (Table 1). Keep the capacitive load on the digital outputs D0-D9 as low as possible (<15pF) to avoid large digital currents feeding back into the analog portion of the MAX19700 and degrading its dynamic performance. Buffers on the digital outputs isolate the outputs from heavy capacitive loads. Adding 100 resistors in series with the digital outputs close to the MAX19700 will help improve ADC performance. See the MAX19700EVKIT schematic for an example of the digital outputs driving a digital buffer through 100 series resistors. During SHDN, IDLE, and STBY states, the pins D0-D9 are internally pulled up to prevent floating digital inputs. To ensure no current flows through D0-D9 I/O, the external bus needs to be either tri-stated or pulled up to OVDD and should not be pulled to ground.
1 LSB =
2 x VREF 1024 VREF
VREF = VREFP - VREFN VREF
OFFSET BINARY OUTPUT CODE (LSB)
10 0000 0001 10 0000 0000 01 1111 1111
VREF (COM)
11 1111 1111 11 1111 1110 11 1111 1101
Dual 10-Bit Tx DAC and Transmit Path
The dual 10-bit digital-to-analog converters (Tx DAC) operate with clock speeds up to 7.5MHz. The Tx DAC digital inputs, D0-D9, are multiplexed on a single 10-bit bus. The voltage reference determines the Tx path fullscale output voltage. See the Reference Configurations section for details on setting the reference voltage. Each Tx path channel integrates a lowpass filter tuned to meet the TD-SCDMA spectral mask requirements. The TD-SCDMA filters are tuned for 1.27MHz cutoff frequency and >55dB image rejection at fIMAGE = 4.32MHz, fOUT = 800kHz, and fCLK = 5.12MHz. See Figure 4 for an illustration of the filter frequency response.
00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000
-512 -511 -510 -509
-1 0+ 1 (COM) INPUT VOLTAGE (LSB)
+509 +510 +511 +512
Figure 2. ADC Transfer Function 16
______________________________________________________________________________________
VREF
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
5.5 CLOCK-CYCLE LATENCY (CHQ) 5 CLOCK-CYCLE LATENCY (CHI)
CHI
CHQ tCLK tCL CLK tDR DR tDOQ D0-D9 D0Q D1I CHQ CHI CHQ tDOI D1Q D2I D2Q D3I D3Q D4I D4Q D5I D5Q D6I D6Q CHI CHQ CHI CHQ CHI CHQ CHI CHQ CHI CHQ tCH
Figure 3. Rx ADC System Timing Diagram
OCCUPIED CHANNEL TD-SCDMA FILTER RESPONSE 0dB -3dB Tx PATH: SFDR = 76.5dBc THD = -74.8dBc SINAD = 57.1dB DAC sin(x)/x RESPONSE
AMPLITUDE
-15dB -49.3dB -55dB (min)
-57.1dB 4.32 IMAGE
FREQ (MHz) 0.8 CHANNEL EDGE 1.27 fC 5.12 fCLK
NOT TO SCALE
Figure 4. TD-SCDMA Filter Frequency Response
Buffer amplifiers follow the TD-SCDMA filters. The amplifier outputs are biased at an adjustable commonmode DC level and designed to drive a differential input stage with input impedance 70k. This simplifies the analog interface between RF quadrature upconverters and the MAX19700. Many RF upconverters require a 0.9V to 1.5V common-mode bias. The SPI-controlled DC common-mode bias eliminates discrete level-setting resistors and code-generated level shifting while preserving the full dynamic range of each Tx DAC. Table 2
shows the Tx path output voltage vs. input codes. Table 10 shows the selection of DC common-mode levels. The buffer amplifiers also feature a programmable fullscale output level of 410mV or 500mV and independent DC offset correction of each I/Q channel. Both features are configured through the SPI interface. The DC offset correction is used to optimize sideband and carrier suppression in the Tx signal path (see Tables 8 and 9).
17
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7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
Table 2. Tx Path Output Voltage vs. Input Codes
(Internal Reference Mode VREFDAC = 1.024V, External Reference Mode VREFDAC = VREFIN; VFS = 410mV for 820mVP-P Full Scale and VFS = 500mV for 1VP-P Full Scale)
DIFFERENTIAL OUTPUT VOLTAGE (V) OFFSET BINARY (D0-D9) 11 1111 1111 11 1111 1110 10 0000 0001 10 0000 0000 01 1111 1111 00 0000 0001 00 0000 0000 INPUT DECIMAL CODE 1023 1022 513 512 511 1 0
(VFS ) VREFDAC x 1023 1024 1023
1021 (VFS ) VREFDAC x 1023 1024 3 (VFS ) VREFDAC x 1023 1024 1 (VFS ) VREFDAC x 1023 1024 1 (VFS ) -VREFDAC x 1023 1024 1021 (VFS ) -VREFDAC x 1023 1024
(VFS ) -VREFDAC x 1023 1024 1023
CLK tDSQ D0-D9 Q: N - 2 I: N - 1 tDSI ID N-2 tDHQ Q: N - 1 I: N tDHI N-1 N Q: N I: N + 1
QD
N-2
N-1
N
Figure 5. Tx DAC System Timing Diagram
Tx DAC Timing Figure 5 shows the relationship between the clock, input data, and analog outputs. Data for the I-channel (ID) is latched on the falling edge of the clock signal, and Qchannel (QD) data is latched on the rising edge of the clock signal. Both I and Q outputs are simultaneously updated on the next rising edge of the clock signal.
3-Wire Serial Interface and Operation Modes
The 3-wire serial interface controls the MAX19700 operation modes as well as the three 12-bit aux-DACs. Upon power-up, program the MAX19700 to operate in the desired mode. Use the 3-wire serial interface to program the device for shutdown, idle, standby, Rx, Tx, or aux-DAC modes. A 16-bit data register sets the mode control. The 16-bit word is comprised of A3-A0 control bits and D11-D0 data bits. Tables 4, 5, and 6 show the MAX19700 operating modes and SPI commands. The serial interface remains active in all modes.
18
______________________________________________________________________________________
7.5Msps, Ultra-Low-Power Analog Front-End
SPI Register Description The operating modes can be selected by programming the control bits, A3-A0, in the register as shown in Table 3. Modifying A3-A0 bits will select from ENABLE-16, Aux-DAC1, Aux-DAC2, Aux-DAC3, IOFFSET, QOFFSET, and COMSEL modes. ENABLE-16 is the default operating mode. This mode allows for shutdown, idle, and standby states as well as switching between FAST, SLOW, Rx, and Tx modes. Table 4 shows the MAX19700 power-management modes. Table 5 shows the T/R pin-controlled external Tx-Rx switching modes. Table 6 shows the SPI-controlled Tx-Rx switching modes. In ENABLE-16 mode, the aux-DACs have independent control bits E6, E5, and E4, and the Tx-path full-scale output can be set with bit E7. Table 7 shows the auxiliary DAC enable codes and Table 8 shows the fullscale output selection. Bits E11 and E10 are reserved and need to be programmed to logic-low. Bits E9 and E8 are not used. Modes Aux-DAC1, Aux-DAC2, and Aux-DAC3 select the aux-DAC channels named DAC1, DAC2, and DAC3 and hold the data inputs for each DAC. Bits _D11-_D0 are the data inputs for each aux-DAC and can be programmed through SPI. The MAX19700 also includes two 6-bit registers that can be programmed to correct the offsets for the Tx-path I and Q channels independently (see Table 9). Use the COMSEL mode to select the output common-mode voltage with bits CM1 and CM0 (see Table 10). Shutdown mode offers the most dramatic power savings by shutting down all the analog sections of the MAX19700 and placing the Rx ADC digital outputs in tri-state mode. When the Rx ADC outputs transition from tri-state to active, the last converted word is placed on the digital outputs. The Tx DAC previously stored data is lost when coming out of shutdown mode. The wake-up time from shutdown mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode, the wake-up time is typically 75s to enter Rx mode and 25s to enter Tx mode. In idle mode, the reference and clock distribution circuits are powered, but all other functions are off. The Rx ADC outputs are forced to tri-state. The wake-up time is 7.3s to enter Rx mode and 5s to enter Tx mode. When the Rx ADC outputs transition from tristate to active, the last converted word is placed on the digital outputs. In standby mode, the reference is powered, but the rest of the device functions are off. The wake-up time from standby mode is 7.3s to enter Rx mode and 25s to enter Tx mode. When the Rx ADC outputs transition from tri-state to active, the last converted word is placed on the digital outputs. FAST and SLOW Rx and Tx Modes In addition to the external Tx-Rx control, the MAX19700 also features SLOW and FAST modes for switching between Rx and Tx operation. In FAST Tx mode, the Rx ADC core is powered on but the ADC core digital outputs are tri-stated on the D0-D9 bus; likewise, in FAST Rx mode the transmit path (DAC core and Tx filter) is powered on but the DAC core digital inputs are tri-stated on the D0-D9 bus. The switching time between Tx to Rx or Rx to Tx is FAST because the converters are on and do not have to recover from a power-down state. In FAST mode, the switching time between Rx to Tx and Tx to Rx is 1s. However, power consumption is higher in this mode because both the Tx and Rx cores are always on. To prevent bus contention in these states, the Rx ADC output buffers are tri-stated during Tx and the Tx DAC input bus is tri-stated during Rx. In SLOW mode, the Rx ADC core is off during Tx; likewise the Tx DAC and filters are turned off during Rx to yield lower power consumption in these modes. For example, the power in SLOW Tx mode is 31.2mW. The power consumption during Rx is 21mW compared to power consumption in FAST mode of 38.4mW. However, the recovery time between states is increased. The switching time in SLOW mode between Rx to Tx is 5s and Tx to Rx is 7.3s. R External T/R Switching Control vs. Serial-Interface Control Bit E3 in the ENABLE-16 register determines whether the device Tx-Rx mode is controlled externally through the T/R input (E3 = low) or through the SPI command (E3 = high). By default, the MAX19700 is in the external Tx-Rx control mode. In the external control mode, use the T/R input (pin 27) to switch between Rx and Tx modes. Using the T/R pin provides faster switching between Rx and Tx modes. To override the external TxRx control, program the MAX19700 through the serial interface. During SHDN, IDLE, or STBY modes, the T/R input is overridden. To restore external Tx-Rx control, program bit E3 low and exit the SHDN, IDLE, or STBY modes through the serial interface.
MAX19700
______________________________________________________________________________________
19
7.5Msps, Ultra-Low-Power Analog Front-End
SPI Timing The serial digital interface is a standard 3-wire connection compatible with SPI/QSPITM/MICROWIRE/DSP interfaces. Set CS low to enable the serial data loading at DIN. Following a CS high-to-low transition, data is shifted synchronously, most significant bit first, on the rising edge of the serial clock (SCLK). After 16 bits are loaded into the serial input register, data is transferred to the latch when CS transitions high. CS must transition high for a minimum of 80ns before the next write sequence. The SCLK can idle either high or low between transitions. Figure 6 shows the detailed timing diagram of the 3-wire serial interface.
QSPI is a trademark of Motorola, Inc.
MAX19700
Mode-Recovery Timing
Figure 7 shows the mode-recovery timing diagram. tWAKE is the wakeup time when exiting shutdown, idle, or standby mode and entering Rx or Tx mode. tENABLE is the recovery time when switching between either Rx or Tx mode. tWAKE or tENABLE is the time for the Rx ADC to settle within 1dB of specified SINAD performance and Tx DAC settling to 10 LSB error. tWAKE and tENABLE times are measured after either the 16-bit serial command is latched into the MAX19700 by a CS transition high (SPI controlled) or a T/R logic transition (external Tx-Rx control). In FAST mode, the recovery time is 1s to switch between Tx or Rx modes.
Table 3. MAX19700 Mode Control
REGISTER NAME ENABLE-16 Aux-DAC1 Aux-DAC2 Aux-DAC3 IOFFSET QOFFSET COMSEL D11 (MSB) E11 = 0 Reserved 1D11 2D11 3D11 -- -- -- D10 15 E10 = 0 Reserved 1D10 2D10 3D10 -- -- -- D9 14 -- 1D9 2D9 3D9 -- -- -- D8 13 -- 1D8 2D8 3D8 -- -- -- D7 12 E7 1D7 2D7 3D7 -- -- -- D6 11 E6 1D6 2D6 3D6 -- -- -- D5 10 E5 1D5 2D5 3D5 IO5 -- D4 9 E4 1D4 2D4 3D4 IO4 -- D3 8 E3 1D3 2D3 3D3 IO3 -- D2 7 E2 1D2 2D2 3D2 IO2 -- D1 6 E1 1D1 2D1 3D1 IO1 D0 5 E0 1D0 2D0 3D0 IO0 A3 4 0 0 0 0 0 0 0 A2 3 0 0 0 0 1 1 1 A1 2 0 0 1 1 0 0 1 A0 1 0 1 0 1 0 1 0
QO5 QO4 QO3 QO2 QO1 QO0 CM1 CM0
Table 4. Power-Management Modes
ADDRESS DATA BITS T/R PIN 27 MODE A3 A2 A1 A0 E3 E2 E1 E0 FUNCTION (POWER MANAGEMENT) DESCRIPTION Rx ADC = OFF Tx DAC = OFF Aux-DAC = OFF REF = OFF Rx ADC = OFF Tx DAC = OFF Aux-DAC = Last State CLK = ON REF = ON Rx ADC = OFF Tx DAC = OFF Aux-DAC = Last State CLK = OFF REF = ON COMMENT
X000
X
SHDN
SHUTDOWN
Device is in complete shutdown Overrides T/R pin
0000
X001
X
IDLE
IDLE
Fast turn-on time Moderate idle power Overrides T/R pin
X010
X
STBY
STANDBY
Slow turn-on time Low standby power Overrides T/R pin
X = Don't care. 20 ______________________________________________________________________________________
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
Table 5. External Tx-Rx Control Using T/R Pin (T/R = 0 = Rx Mode, T/R = 1 = Tx Mode)
ADDRESS DATA BITS T/R PIN 27 STATE FUNCTION Rx TO Tx-Tx TO Rx SWITCHING SPEED DESCRIPTION Rx Mode 0 0011 1 Ext1-Tx Ext1-Rx FAST-SLOW Rx ADC = ON Tx DAC = ON Rx Bus = Enable Tx Mode Rx ADC = OFF Tx DAC = ON Tx Bus = Enable Rx Mode Rx ADC = ON Tx DAC = OFF Rx Bus = Enable Tx Mode Rx ADC = ON Tx DAC = ON Tx Bus = Enable Rx Mode Rx ADC = ON Tx DAC = OFF Rx Bus = Enable Tx Mode Rx ADC = OFF Tx DAC = ON Tx Bus = Enable Rx Mode Rx ADC = ON Tx DAC = ON Rx Bus = Enable Tx Mode Rx ADC = ON Tx DAC = ON Tx Bus = Enable Moderate Power Fast Rx to Tx when T/R transitions 0 to 1 COMMENT
A3 A2 A1 A0 E3 E2 E1 E0
Low Power Slow Tx to Rx when T/R transitions 1 to 0
0 0100 1 0000 0 0101 1
Ext2-Rx (Default) SLOW-FAST Ext2-Tx
Low Power Slow Rx to Tx when T/R transitions 0 to 1
Moderate Power Fast Tx to Rx when T/R transitions 1 to 0
Ext3-Rx SLOW-SLOW Ext3-Tx
Low Power Slow Rx to Tx when T/R transitions 0 to 1
Low Power Slow Tx to Rx when T/R transitions 1 to 0
0 0110 1
Ext4-Rx FAST-FAST Ext4-Tx
Moderate Power Fast Rx to Tx when T/R transitions 0 to 1
Moderate Power Fast Tx to Rx when T/R transitions 1 to 0
System Clock Input (CLK)
Both the Rx ADC and Tx DAC share the CLK input. The CLK input accepts a CMOS-compatible signal level set by OVDD from 1.8V to VDD. Since the interstage conversion of the device depends on the repeatability of
the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). Specifically, sampling occurs on the rising edge of the clock signal, requiring this edge to provide the lowest
______________________________________________________________________________________
21
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
Table 6. Tx-Rx Control Using SPI Commands
ADDRESS DATA BITS T/R PIN 27 MODE FUNCTION (Tx-Rx SWITCHING SPEED) DESCRIPTION Rx Mode 1011 X SPI1-Rx SLOW Rx ADC = ON Tx DAC = OFF Rx Bus = Enable Tx Mode 1100 X SPI2-Tx SLOW Rx ADC = OFF Tx DAC = ON Tx Bus = Enable Rx Mode 1101 X SPI3-Rx FAST Rx ADC = ON Tx DAC = ON Rx Bus = Enabled Tx Mode 1110 X SPI4-Tx FAST Rx ADC = ON Tx DAC = ON Tx Bus = Enabled Moderate Power Fast Tx to Rx through SPI command Moderate Power Fast Rx to Tx through SPI command Low Power Slow Tx to Rx through SPI command Low Power Slow Rx to Tx through SPI command COMMENTS
A3 A2 A1 A0 E3 E2 E1 E0
0000
X = Don't care.
Table 7. Aux-DAC Enable Table (ENABLE-16 Mode)
E6 0 0 0 0 1 1 1 1 E5 0 0 1 1 0 0 1 1 E4 0 1 0 1 0 1 0 1 Aux-DAC3 ON ON ON ON OFF OFF OFF OFF Aux-DAC2 ON ON OFF OFF ON ON OFF OFF Aux-DAC1 ON OFF ON OFF ON OFF ON OFF
possible jitter. Any significant clock jitter limits the SNR performance of the on-chip Rx ADC as follows: 1 SNR = 20 x log 2 x x fIN x t AJ where fIN represents the analog input frequency and tAJ is the time of the clock jitter. Clock jitter is especially critical for undersampling applications. Consider the clock input as an analog input and route away from any analog input or other digital signal lines. The MAX19700 clock input operates with a OVDD / 2 voltage threshold and accepts a 50% 15% duty cycle.
12-Bit, Auxiliary Control DACs
Table 8. Tx-Path Full-Scale Select (ENABLE-16 Mode)
E7 0 (Default) 1 Tx-PATH OUTPUT FULL SCALE 820mVP-P 1VP-P
The MAX19700 includes three 12-bit aux-DACs (DAC1, DAC2, DAC3) with 1s settling time for controlling variable-gain amplifier (VGA), automatic gain-control (AGC), and automatic frequency-control (AFC) functions. The aux-DAC output range is 0.1V to 2.56V. During power-up, the VGA and AGC outputs (DAC2 and DAC3) are at zero. The AFC DAC (DAC1) is at 1.1V during power-up. The aux-DACs can be independently
22
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7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
Table 9. Offset Control Bits for I and Q Channels (IOFFSET or QOFFSET Mode)
BITS IO5-IO0 WHEN IN IOFFSET MODE, BITS QO5-QO0 WHEN IN QOFFSET MODE IO5/QO5 1 1 1
* * *
IO4/QO4 1 1 1
* * *
IO3/QO3 1 1 1
* * *
IO2/QO2 1 1 1
* * *
IO1/QO1 1 1 0
* * *
IO0/QO0 1 0 1
* * *
OFFSET 1 LSB = (VFSP-P/1023) -31 LSB -30 LSB -29 LSB
* * *
1 1 1 0 0 0
* * *
0 0 0 0 0 0
* * *
0 0 0 0 0 0
* * *
0 0 0 0 0 0
* * *
1 0 0 0 0 1
* * *
0 1 0 0 1 0
* * *
-2 LSB -1 LSB 0mV 0mV (Default) 1 LSB 2 LSB
* * *
0 0 0
1 1 1
1 1 1
1 1 1
0 1 1
1 0 1
29 LSB 30 LSB 31 LSB
Note: For transmit full-scale select of 820mVP-P: 1 LSB = (820mVP-P/1023) = 0.8016mV. For transmit full-scale select of 1VP-P: 1 LSB = (1VP-P/1023) = 0.9775mV.
Table 10. Common-Mode Select (COMSEL Mode)
CM1 0 0 1 1 CM0 0 1 0 1 Tx-PATH OUTPUT COMMON MODE (V) 1.4 (Default) 1.25 1.1 0.9
drive larger load capacitance (<15pF) at the expense of slower settling time.
Reference Configurations
The MAX19700 features an internal precision 1.024V bandgap reference that is stable over the entire powersupply and temperature ranges. The REFIN input provides two modes of reference operation. The voltage at REFIN (V REFIN ) sets the reference operation mode (Table 11). In internal reference mode, connect REFIN to VDD . V REF is an internally generated 0.512V 4%. COM, REFP, and REFN are low-impedance outputs with V COM = V DD / 2, V REFP = V DD / 2 + V REF / 2, and VREFN = VDD / 2 - VREF / 2. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Bypass REFIN to GND with a 0.1F capacitor. In buffered external reference mode, apply 1.024V 10% at REFIN. In this mode, COM, REFP, and REFN are low-impedance outputs with V COM = V DD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 VREFIN / 4. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Bypass REFIN to GND with a 0.1F
23
controlled through the SPI bus, except during SHDN mode where the aux-DACs are turned off completely and the output voltage is set to zero. In STBY and IDLE modes the aux-DACs maintain the last value. On wakeup from SHDN, the aux-DACs resume the last values. Loading on the aux-DAC outputs should be carefully observed to achieve specified settling time and stability. The capacitive load must be kept to a maximum of 5pF including package and trace capacitance. The resistive load must be greater than 200k. If capacitive loading exceeds 5pF, then add a 10k resistor in series with the output. Adding the series resistor helps
______________________________________________________________________________________
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
tCSW CS tCSS tCP tCH tCL tCS
SCLK tDS DIN MSB tDH LSB
Figure 6. 3-Wire Serial-Interface Timing Diagram
CS
SCLK 16-BIT SERIAL DATA INPUT
DIN
D0-D9
ADC DIGITAL OUTPUT. SINAD SETTLES WITHIN 1dB tWAKE, SD, ST_ TO Rx MODE OR tENABLE, RX DAC ANALOG OUTPUT OUTPUT SETTLES TO 10 LSB ERROR tWAKE, SD, ST_ TO Tx MODE OR tENABLE, TX tENABLE, TX EXTERNAL T/R CONTROL
ID/QD
T/R R X - > TX tENABLE, RX EXTERNAL T/R CONTROL T/R T X - > RX
Figure 7. MAX19700 Mode-Recovery Timing Diagram
capacitor. In this mode, the Tx-path full-scale output is proportional to the external reference. For example, if the VREFIN is increased by 10% (max), the Tx-path fullscale output is also increased by 10% or 451mV.
Power-On Reset
The MAX19700 features a power-on-reset (POR) function that sets the device in a known state upon powerup. The default state is Ext2-Rx. The POR circuit is designed to accommodate power supplies that ramp
24
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7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
Table 11. Reference Modes
VREFIN >0.8V x VDD REFERENCE MODE Internal Reference Mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Buffered External Reference Mode. An external 1.024V 10% reference voltage is applied to REFIN. VREF is internally generated to be VREFIN / 2. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Bypass REFIN to GND with a 0.1F capacitor.
1.024V 10%
from 0V to VDD in less than or equal to 1ms. For power supplies that ramp from 0V to VDD in greater than 1ms, program the MAX19700 to enter the desired state using the SPI interface.
TDD Mode
The MAX19700 is optimized to operate in TD-SCDMA applications. When FAST mode is selected, the MAX19700 can switch between Tx and Rx modes through the T/R pin in typically 1s. The Rx ADC and Tx DAC operate independently. The Rx ADC and Tx DAC digital bus are shared forming a single 10-bit parallel bus. Using the 3-wire serial interface or external T/R pin, select between Rx mode to enable the Rx ADC or Tx mode to enable the Tx DAC. When operating in Rx mode, the Tx DAC bus is not enabled and in Tx mode the Rx ADC bus is tri-stated eliminating any unwanted
Applications Information
Using Balun Transformer AC-Coupling
An RF transformer (Figure 8) provides an excellent solution to convert a single-ended signal source to a fully differential signal for optimum ADC performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. A 1:1 transformer can be used, or a step-up transformer can be selected to reduce the drive requirements. In general, the MAX19700 provides better SFDR and THD with fully differential input signals than single-ended signals, especially for high input frequencies. In differential mode, even-order harmonics are lower as both inputs (IAP, IAN, QAP, QAN) are balanced, and each of the Rx ADC inputs only requires half the signal swing compared to single-ended mode. Figure 9 shows an RF transformer converting the MAX19700 Tx DAC differential analog outputs to single-ended.
25 IAP 0.1F VIN COM 0.33F 0.1F 22pF
Using Op-Amp Coupling
Drive the MAX19700 Rx ADC with op amps when a balun transformer is not available. Figures 10 and 11 show the Rx ADC being driven by op amps for AC-coupled single-ended and DC-coupled differential applications. Amplifiers such as the MAX4454 and MAX4354 provide high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. The op-amp circuit shown in Figure 11 can also be used to interface with the Tx DAC differential analog outputs to provide gain or buffering. The Tx DAC differential analog outputs cannot be used in single-ended mode because of the internally generated common-mode level. Also, the Tx DAC analog outputs are designed to drive a differential input stage with input impedance 70k. If single-ended outputs are desired, use an amplifier to provide differential-to-single-ended conversion and select an amplifier with proper input commonmode voltage range.
25 22pF
IAN
MAX19700
25 QAP 0.1F VIN 22pF
0.33F
0.1F
QAN 25 22pF
Figure 8. Balun Transformer-Coupled Single-Ended-toDifferential Input Drive for Rx ADC 25
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7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
IDP VOUT
spurious emissions and preventing bus contention. In TDD mode, the MAX19700 uses 38.4mW power in Rx mode at fCLK = 7.5MHz, and 39.3mW in Tx mode.
TD-SCDMA Application
MAX19700
IDN
QDP
VOUT
Figure 12 illustrates a typical TD-SCDMA application circuit. The MAX19700 is designed to interface directly with the MAX2507 and MAX2392 radio front-ends to provide a complete "RF-to-Bits" front-end solution. The MAX19700 provides several features that allow direct interface to the MAX2392 and MAX2507: * Integrated Tx filters reduce component count, lower cost, and meet TD-SCDMA spectral mask requirements * Programmable DC common-mode Tx output levels eliminate discrete DC level-shifting components while preserving Tx DAC full dynamic range Optimized Tx full-scale output level eliminates discrete amplifiers for I/Q gain control Tx-I/Q offset correction eliminates discrete trim DACs for offset trim to improve sideband/carrier suppression One microsecond settling time aux-DACs for VGA and AGC control allow fast, accurate Tx power and Rx gain control
QDN
Figure 9. Balun Transformer-Coupled Differential-to-SingleEnded Output Drive for Tx DAC
* *
REFP
*
VIN 1k 0.1F RISO 50 IAP 100 1k CIN 22pF
Grounding, Bypassing, and Board Layout
The MAX19700 requires high-speed board layout design techniques. Refer to the MAX19700 EV kit data sheet for a board layout reference. Place all bypass capacitors as close to the device as possible, preferably on the same side of the board as the device, using surface-mount devices for minimum inductance. Bypass VDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F capacitor. Bypass OVDD to OGND with a 0.1F ceramic capacitor in parallel with a 2.2F capacitor. Bypass REFP, REFN, and COM each to GND with a 0.33F ceramic capacitor. Bypass REFIN to GND with a 0.1F capacitor. Multilayer boards with separated ground and power planes yield the highest level of signal integrity. Use a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the device package. Connect the MAX19700 exposed backside paddle to GND plane. Join the two ground planes at a single point so the noisy digital ground currents do not interfere with the analog ground plane. The ideal location for this connection can be determined experimentally at a point along the gap between the two ground planes.
COM REFN 0.1F RISO 50 100 IAN CIN 22pF REFP
MAX19700
RISO 50 QAP CIN 22pF
VIN
0.1F
1k
100
1k
REFN
0.1F RISO 50
100
QAN CIN 22pF
Figure 10. Single-Ended Drive for Rx ADC 26 ______________________________________________________________________________________
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
R4 600 R5 600
R1 600
RISO 22 IAN CIN 5pF
R2 600 R6 600 R3 600 R8 600 R9 600 R7 600 COM
MAX19700
RISO 22 CIN 5pF IAP
R10 600
R11 600
Figure 11. Rx ADC DC-Coupled Differential Drive
Make this connection with a low-value, surface-mount resistor (1 to 5), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy digital system's ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from sensitive analog traces. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90 turns.
earity parameters for the device are measured using the best straight line fit (DAC Figure 13a). Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes (ADC) and a monotonic transfer function (ADC and DAC) (DAC Figure 13b). ADC Offset Error Ideally, the midscale transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured transition point and the ideal transition point. DAC Offset Error Offset error (Figure 13a) is the difference between the ideal and actual offset point. The offset point is the output value when the digital input is midscale. This error affects all codes by the same amount and usually can be compensated by trimming.
Dynamic Parameter Definitions
ADC and DAC Static Parameter Definitions
Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static lin-
______________________________________________________________________________________
27
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
VCC RF IN
MAX2392 TD-SCDMA ZIF RECEIVER
Rx ADC 10-BIT
MAX19700
CLK
Rx ADC 10-BIT
ADC OUTPUT MUX
AGC AUX-DAC2
TCXO
AFC
AUX-DAC1 10-BIT
RF OUT VGA MAX2507 TD-SCDMA DIRECT MODULATOR FILTER
AUX-DAC3
Tx DAC 10-BIT
FILTER
Tx DAC 10-BIT
DAC INPUT MUX
SERIAL BUS
Figure 12. Typical Application Circuit for TD-SCDMA Radio
7 6 ANALOG OUTPUT VALUE 5 4 3 2 1 0 000 001 010 011 100 101 110 111 DIGITAL INPUT CODE AT STEP 001 (0.25 LSB) AT STEP 011 (0.5 LSB) ANALOG OUTPUT VALUE
6 5 4 3 1 LSB 2 1 0 000 001 010 011 100 101 DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR (+0.25 LSB) 1 LSB DIFFERENTIAL LINEARITY ERROR (-0.25 LSB)
Figure 13a. Integral Nonlinearity
Figure 13b. Differential Nonlinearity
28
______________________________________________________________________________________
DIGITAL BASEBAND PROCESSOR
7.5Msps, Ultra-Low-Power Analog Front-End
CLK
ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: ENOB = (SINAD - 1.76) / 6.02 Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as:
TRACK
MAX19700
T/H
TRACK
HOLD
Figure 14. T/H Aperture Timing
(V22 + V32 + V42 + V52 + V62 THD = 20log V1
)
ADC Gain Error Ideally, the ADC full-scale transition occurs at 1.5 LSB below full scale. The gain error is the amount of deviation between the measured transition point and the ideal transition point with the offset error removed.
where V1 is the fundamental amplitude and V2-V6 are the amplitudes of the 2nd- through 6th-order harmonics. Third Harmonic Distortion (HD3) HD3 is defined as the ratio of the RMS value of the third harmonic component to the fundamental input signal. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) IMD is the total power of the intermodulation products relative to the total input power when two tones, f1 and f2, are present at the inputs. The intermodulation products are (f1 f2), (2 f1), (2 f2), (2 f1 f2), (2 f2 f1). The individual input tone levels are at -7dBFS. 3rd-Order Intermodulation (IM3) IM3 is the power of the worst 3rd-order intermodulation product relative to the input power of either input tone when two tones, f1 and f2, are present at the inputs. The 3rd-order intermodulation products are (2 x f1 f2), (2 f2 f1). The individual input tone levels are at 7dBFS. Power-Supply Rejection Power-supply rejection is defined as the shift in offset and gain error when the power supply is changed 5%. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in such a way that the signal's slew rate does not limit the ADC's performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. Note that the T/H performance is usually the limiting factor for the small-signal input bandwidth.
29
ADC Dynamic Parameter Definitions
Aperture Jitter Figure 14 shows the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 14). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error) and results directly from the ADC's resolution (N bits): SNR(max) = 6.02dB x N + 1.76dB (in dB) In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset.
______________________________________________________________________________________
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. This point is defined as the fullpower bandwidth frequency. where V1 is the fundamental amplitude and V2 through Vn are the amplitudes of the 2nd through nth harmonic up to the Nyquist frequency. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component up to the Nyquist frequency excluding DC.
DAC Dynamic Parameter Definitions
Total Harmonic Distortion THD is the ratio of the RMS sum of the output harmonics up to the Nyquist frequency divided by the fundamental: (V22 + V32 + ...+ Vn2 ) THD = 20log V1
Functional Diagram
IAP IAN
10-BIT ADC
MAX19700
SHDN T/R
QAP QAN
10-BIT ADC HALFDUPLEX BUS FILTER 10-BIT DAC
D0-D9 DR
IDP IDN
QDP FILTER QDN
10-BIT DAC
SYSTEM CLOCK
CLK
OFFSET PROGRAM DAC1 12-BIT DAC
SERIAL INTERFACE AND SYSTEM CONTROL
DIN SCLK CS
DAC2
12-BIT DAC
1.024V REFERENCE BUFFER
REFIN REFP REFN COM
DAC3
12-BIT DAC
30
______________________________________________________________________________________
7.5Msps, Ultra-Low-Power Analog Front-End
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX19700
D2 D D/2 k
C L
b D2/2
E/2 E2/2 E (NE-1) X e
C L
E2
k L DETAIL A e (ND-1) X e DETAIL B
e L
C L
C L
L1
L
L
e
e
A1
A2
A
TITLE:
SEMICONDUCTOR
PROPRIETARY INFORMATION
DALLAS
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0144
D
1
2
______________________________________________________________________________________
32, 44, 48L QFN.EPS
31
7.5Msps, Ultra-Low-Power Analog Front-End MAX19700
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SEMICONDUCTOR
PROPRIETARY INFORMATION TITLE:
DALLAS
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0144
D
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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