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| (R) PGA204 PGA205 Programmable Gain INSTRUMENTATION AMPLIFIER FEATURES q DIGITALLY PROGRAMMABLE GAIN: PGA204: G=1, 10, 100, 1000V/V PGA205: G=1, 2, 4, 8V/V q LOW OFFSET VOLTAGE: 50V max q LOW OFFSET VOLTAGE DRIFT: 0.25V/C q LOW INPUT BIAS CURRENT: 2nA max q LOW QUIESCENT CURRENT: 5.2mA typ q NO LOGIC SUPPLY REQUIRED q 16-PIN PLASTIC DIP, SOL-16 PACKAGES DESCRIPTION The PGA204 and PGA205 are low cost, general purpose programmable-gain instrumentation amplifiers offering excellent accuracy. Gains are digitally selected: PGA204--1, 10, 100, 1000, and PGA205--1, 2, 4, 8V/V. The precision and versatility, and low cost of the PGA204 and PGA205 make them ideal for a wide range of applications. Gain is selected by two TTL or CMOS-compatible address lines, A0 and A1. Internal input protection can withstand up to 40V on the analog inputs without damage. The PGA204 and PGA205 are laser trimmed for very low offset voltage (50V), drift (0.25V/C) and high common-mode rejection (115dB at G=1000). They operate with power supplies as low as 4.5V, allowing use in battery operated systems. Quiescent current is 5mA. The PGA204 and PGA205 are available in 16-pin plastic DIP, and SOL-16 surface-mount packages, specified for the -40C to +85C temperature range. APPLICATIONS q DATA ACQUISITION SYSTEM q GENERAL PURPOSE ANALOG BOARDS q MEDICAL INSTRUMENTATION VO1 1 - VIN 4 Over-Voltage Protection V+ 13 PGA204 PGA205 Feedback 12 A1 25k 25k A1 A0 Digital Ground + VIN 16 15 14 Digitally Selected Feedback Network A3 11 VO 5 Over-Voltage Protection 6 A2 25k 7 9 VO2 8 V- 25k 10 Ref VOS Adj International Airport Industrial Park * Mailing Address: PO Box 11400 * Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd. * Tucson, AZ 85706 Tel: (520) 746-1111 * Twx: 910-952-1111 * Cable: BBRCORP * Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132 (R) (c) 1991 Burr-Brown Corporation PDS-1176A 1 Printed in U.S.A. PGA204/205 October, 1993 SPECIFICATIONS ELECTRICAL At TA = +25C, VS = 15V, and RL = 2k unless otherwise noted. PGA204BP, BU PARAMETER INPUT Offset Voltage, RTI vs Temperature vs Power Supply Long-Term Stability Impedance, Differential Common-Mode Input Common-Mode Range Safe Input Voltage Common-Mode Rejection CONDITIONS TA=+25C TA=TMIN to TMAX VS=4.5V to 18V MIN TYP MAX MIN PGA204AP, AU TYP 25+30/G 0.25+5/G * * * * * MAX 125+500/G 1+10/G * UNITS V V/C V/V V/mo || pF || pF V V dB dB dB dB 5 * nA pA/C nA pA/C nV/Hz nV/ Hz nV/Hz Vp-p pA/Hz pA/Hz pAp-p 0.05 0.05 0.05 0.1 * 0.002 0.004 0.004 0.02 % % % % ppm/C % of FSR % of FSR % of FSR % of FSR V V pF mA MHz kHz kHz kHz V/s s s s s s s s s s * * * V+ 15 +5.2/-4.2 18 6.5 +85 +125 80 * * * * * * 7.5 * * * V V A V V mA C C C/W PGA204 G=1, 10, 100, 1000V/V VO=0V (see text) VCM=10V, RS=1k G=1 G=10 G=100 G=1000 10.5 10+20/G 50+100/G 0.1+0.5/G 0.25+5/G 0.5+2/G 3+10/G 0.2+0.5/G 1010||6 1010||6 12.7 40 99 114 123 123 0.5 8 0.5 8 2 2 * * 75 90 106 106 90 106 110 110 * * * * * * * * * * * 80 96 110 115 BIAS CURRENT vs Temperature Offset Current vs Temperature NOISE, Voltage, RTI(1): f=10Hz f=100Hz f=1kHz fB=0.1Hz to 10Hz Noise Current f=10Hz f=1kHz fB=0.1Hz to 10Hz GAIN, Error G100, G100, G100, G100, RS=0 RS=0 RS=0 RS=0 16 13 13 0.4 0.4 0.2 18 Gain vs Temperature Nonlinearity G=1 G=10 G=100 G=1000 G=1 to 1000 G=1 G=10 G=100 G=1000 IO=5mA, TMIN to TMAX IO=-5mA, TMIN to TMAX (V+)-1.5 (V-)+1.5 0.005 0.01 0.01 0.02 2.5 0.0004 0.0004 0.0004 0.0008 (V+)-1.3 (V-)+1.3 1000 +23/-17 1 80 10 1 0.7 22 23 100 1000 23 28 140 1300 70 0.024 0.024 0.024 0.05 10 0.001 0.002 0.002 0.01 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * OUTPUT Voltage, Positive(2) Negative(2) Load Capacitance Stability Short Circuit Current FREQUENCY RESPONSE Bandwidth, -3dB Slew Rate Settling Time(3), 0.1% 0.01% Overload Recovery DIGITAL LOGIC Digital Ground Voltage, VDG Digital Low Voltage Digital Input Current Digital High Voltage POWER SUPPLY, Voltage Current TEMPERATURE RANGE Specification Operating JA G=1 G=10 G=100 G=1000 VO=10V, G=10 G=1 G=10 G=100 G=1000 G=1 G=10 G=100 G=1000 50% Overdrive 0.3 * V- V- 1 VDG +2 4.5 VIN=0V -40 -40 (V+)-4 VDG+0.8V * * * * * Specification same as PGA204BP. NOTES: (1) Input-referred noise voltage varies with gain. See typical curves. (2) Output voltage swing is tested for 10V min on 11.4V power supplies. (3) Includes time to switch to a new gain. (R) PGA204/205 2 SPECIFICATIONS ELECTRICAL At TA = +25C, VS = 15V, and RL = 2k unless otherwise noted. PGA205BP, BU PARAMETER INPUT Offset Voltage, RTI vs Temperature vs Power Supply Long-Term Stability Impedance, Differential Common-Mode Input Common-Mode Range Safe Input Voltage Common-Mode Rejection CONDITIONS TA=+25C TA=TMIN to TMAX VS=4.5V to 18V MIN TYP MAX MIN PGA205AP, AU TYP 25+30/G 0.25+5/G * * * * * MAX 125+500/G 1+10/G * UNITS V V/C V/V V/mo ||pF ||pF V V dB dB dB dB 5 * nA pA/C nA pA/C nV/Hz nV/Hz nV/Hz Vp-p pA/Hz pA/Hz pAp-p 0.05 0.05 0.05 0.05 * 0.002 0.004 0.004 0.004 % % % % ppm/C % of FSR % of FSR % of FSR % of FSR V V pF mA MHz kHz kHz kHz V/s s s s s s s s s s * * * V+ 15 +5.2/-4.2 18 6.5 +85 +125 80 * * * * * * 7.5 * * * V V A V V mA C C C/W PGA205 G=1, 2, 4, 8V/V VO=0V (see text) VCM=10V, RS=1k G=1 G=2 G=4 G=8 10.5 10+20/G 50+100/G 0.1+0.5/G 0.25+5/G 0.5+2/G 3+10/G 0.2+0.5/G 1010||6 1010||6 12.7 40 94 100 106 112 0.5 8 0.5 8 2 2 * * 75 80 85 89 88 94 100 106 * * * * * * * * * * * 80 85 90 95 BIAS CURRENT vs Temperature Offset Current vs Temperature Noise Voltage, RTI(1): f=10Hz f=100Hz f=1kHz fB=0.1Hz to 10Hz Noise Current f=10Hz f=1kHz fB=0.1Hz to 10Hz GAIN, Error G=8, G=8, G=8, G=8, RS=0 RS=0 RS=0 RS=0 19 15 15 0.5 0.4 0.2 18 Gain vs Temperature Nonlinearity G=1 G=2 G=4 G=8 G=1 to 8 G=1 G=2 G=4 G=8 IO=5mA, TMIN to TMAX IO=-5mA, TMIN to TMAX (V+)-1.5 (V-)+1.5 0.005 0.01 0.01 0.01 2.5 0.00024 0.00024 0.00024 0.00024 (V+)-1.3 (V-)+1.3 1000 +23/-17 1 400 200 100 0.7 22 22 23 23 23 23 25 28 70 0.024 0.024 0.024 0.024 10 0.001 0.002 0.002 0.002 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * OUTPUT Voltage, Positive(2) Negative(2) Load Capacitance Stability Short Circuit Current FREQUENCY RESPONSE Bandwidth, -3dB Slew Rate Settling Time(3), 0.1% 0.01% Overload Recovery DIGITAL LOGIC INPUTS Digital Ground Voltage, VDG Digital Low Voltage Digital Low Current Digital High Voltage POWER SUPPLY, Voltage Current TEMPERATURE RANGE Specification Operating JA G=1 G=2 G=4 G=8 VO=10V, G=8 G=1 G=2 G=4 G=8 G=1 G=2 G=4 G=8 50% overdrive 0.3 * V- V- 1 VDG+2 4.5 VIN=0V -40 -40 (V+)-4 VDG+0.8V * * * * * Specification same as PGA204BP. NOTES: (1) Input-referred noise voltage varies with gain. See typical curves. (2) Output voltage swing is tested for 10V min on 11.4V power supplies. (3) Includes time to switch to a new gain. (R) 3 PGA204/205 PACKAGE INFORMATION MODEL PGA204AP PGA204BP PGA204AU PGA204BU PGA205AP PGA205BP PGA205AU PGA205BU PACKAGE 16-Pin Plastic 16-Pin Plastic SOL-16 Surface SOL-16 Surface DIP DIP Mount Mount PACKAGE DRAWING NUMBER(1) 180 180 211 211 180 180 211 211 ABSOLUTE MAXIMUM RATINGS Supply Voltage .................................................................................. 18V Analog Input Voltage Range ............................................................. 40V Logic Input Voltage Range .................................................................. VS Output Short-Circuit (to ground) .............................................. Continuous Operating Temperature ................................................. -40C to +125C Storage Temperature ..................................................... -40C to +125C Junction Temperature .................................................................... +150C Lead Temperature (soldering -10s) .............................................. +300C 16-Pin Plaseic DIP 16-Pin Plastic DIP SOL-16 Surface Mount SOL-16 Surface Mount NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION MODEL PGA204AP PGA204BP PGA204AU PGA204BU PGA205AP PGA205BP PGA205AU PGA205BU GAINS 1, 10, 100, 1000V/V 1, 10, 100, 1000V/V 1, 10, 100, 1000V/V 1, 10, 100, 1000V/V 1, 2, 4, 8V/V 1, 2, 4, 8V/V 1, 2, 4, 8V/V 1, 2, 4, 8V/V PACKAGE 16-Pin Plastic DIP 16-Pin Plastic DIP SOL-16 Surface-Mount SOL-16 Surface-Mount 16-Pin Plastic DIP 16-Pin Plastic DIP SOL-16 Surface-Mount SOL-16 Surface-Mount TEMPERATURE RANGE -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C (R) PGA204/205 4 DICE INFORMATION PAD FUNCTION VO1 -- -- V-IN V+IN VOS Adj VOS Adj V- PAD 9 10 11 12 13 14 15 16 FUNCTION VO2 Ref VO Feedback V+ Dig. Ground A0 A1 FPO 1 2 3 4 5 6 7 8 Substrate Bias: Internally connected to V- power supply. MECHANICAL INFORMATION MILS (0.001") Die Size Die Thickness Min. Pad Size Backing 186 x 130 5 20 3 4x4 MILLIMETERS 4.72 x 3.30 0.13 0.51 0.08 0.1 x 0.1 Gold PGA204/205 DIE TOPOGRAPHY PIN CONFIGURATION Top View ELECTROSTATIC DISCHARGE SENSITIVITY 16 A1 15 A0 14 Dig. Ground 13 V+ 12 Feedback 11 VO 10 Ref 9 VO2 VO1 NC NC V-IN V+IN VOS Adjust VOS Adjust V- 1 2 3 4 5 6 7 8 This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NC: No Internal Connection. (R) 5 PGA204/205 TYPICAL PERFORMANCE CURVES At TA = +25C, and VS = 15V, unless otherwise noted. GAIN vs FREQUENCY COMMON-MODE REJECTION vs FREQUENCY 140 G = 1k,100 G=1k 1k Common-Mode Rejection (dB) 120 "B" Grade G=1 G = 10 Gain (V/V) G=100 100 G=10 100 G = 1k G = 100 G = 10 G=1 10 80 G=1 1 60 40 10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M Frequency (Hz) Frequency (Hz) INPUT COMMON-MODE VOLTAGE RANGE vs OUTPUT VOLTAGE 15 Common-Mode Voltage (V) POSITIVE POWER SUPPLY REJECTION vs FREQUENCY 140 Power Supply Rejection (dB) 10 5 0 -5 -10 y A1 ed b Limit ut Swing utp +O Limit + Ou ed by A tput Swin2 g - + - + (Any Gain) VO 120 100 80 60 40 20 0 G = 1k G = 100 VD/2 VD/2 VCM A3 - Output Swing Limit Lim it - O ed by utpu A t Sw 2 ing -10 -5 0 5 A3 + Output Swing Limit by A 1 g in ited Lim put Sw Out - G = 10 G=1 -15 -15 10 15 10 100 1k 10k 100k 1M Output Voltage (V) Frequency (Hz) NEGATIVE POWER SUPPLY REJECTION vs FREQUENCY INPUT- REFERRED NOISE VOLTAGE vs FREQUENCY Power Supply Rejection (dB) 120 100 80 G = 10 60 40 20 0 10 100 1k 10k 100k 1M Frequency (Hz) G=1 G = 1k G = 100 Input-Referred Noise Voltage (nV/ Hz) 140 1k 100 G=1 G = 10 10 G = 100, 1k G = 1k BW Limit 1 1 10 100 Frequency (Hz) 1k 10k (R) PGA204/205 6 TYPICAL PERFORMANCE CURVES At TA = +25C, and VS = 15V, unless otherwise noted. (CONT) INPUT-REFERRED OFFSET VOLTAGE WARM-UP vs TIME Input Bias and Input Offset Current (nA) INPUT BIAS AND INPUT OFFSET CURRENT vs TEMPERATURE 2 6 Offset Voltage Change (V) 4 G > 100 2 0 -2 -4 -6 0 15 30 45 60 75 90 105 120 Time from Power Supply Turn-on (s) 1 IB 0 IOS -1 -2 -75 -50 -25 0 25 50 75 100 125 Temperature (C) INPUT BIAS CURRENT vs DIFFERENTIAL INPUT VOLTAGE 3 2 3 INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE Both Inputs 2 Input Bias Current (mA) |Ib1| + |Ib2| One Input Input Current (mA) 1 0 -1 -2 -3 -45 G=1 G = 10 G = 100, 1k -30 -15 0 15 30 45 1 0 -1 -2 One Input Both Inputs -30 -15 0 15 Common-Mode Voltage (V) 30 45 Over-Voltage Protection Normal Operation Over-Voltage Protection -3 -45 Differential Overload Voltage (V) MAXIMUM OUTPUT VOLTAGE vs FREQUENCY 32 28 Output Voltage (Vp-p) SLEW RATE vs TEMPERATURE 1.0 24 20 16 12 8 4 0 10 100 G 10 Slew Rate (V/s) 0.8 G=8 or 10 0.6 0.4 0.2 1k 10k 100k 1M 0 -75 -50 -25 0 25 50 75 100 125 Frequency (Hz) Temperature (C) (R) 7 PGA204/205 TYPICAL PERFORMANCE CURVES At TA = +25C, and VS = 15V, unless otherwise noted. (CONT) OUTPUT CURRENT LIMIT vs TEMPERATURE 30 QUIESCENT CURRENT vs TEMPERATURE 6.0 Short Circuit Current (mA) Quiescent Current (mA) 25 +|ICL| 20 -|ICL| 5.5 5.0 15 4.5 10 -40 -15 10 35 60 85 4.0 -75 -50 -25 0 25 50 75 100 125 Temperature (C) Temperature (C) QUIESCENT CURRENT vs POWER SUPPLY VOLTAGE 5.2 V+ Quiescent Current (mA) Output Voltage (V) 16 14 12 10 8 6 4 2 POSITIVE OUTPUT SWING vs TEMPERATURE VS = 15V 5.0 VS = 11.4 4.5 4.0 V- VS = 4.5 3.5 0 5 10 Power Supply Voltage (V) 15 20 0 -75 -50 -25 0 25 50 75 100 125 Temperature (C) NEGATIVE OUTPUT SWING vs TEMPERATURE -16 -14 Output Voltage (V) VS = 15V -12 -10 -8 -6 -4 -2 0 -75 VS = 11.4 VS = 4.5 -50 -25 0 25 50 75 100 125 Temperature (C) (R) PGA204/205 8 TYPICAL PERFORMANCE CURVES At TA = +25C, and VS = 15V, unless otherwise noted. (CONT) SMALL-SIGNAL RESPONSE, G = 1 LARGE-SIGNAL RESPONSE, G = 1 +200mV +10V -200mV -10V SMALL-SIGNAL RESPONSE, G = 10 LARGE-SIGNAL RESPONSE, G = 10 +200mV +10V -200mV -10V SMALL-SIGNAL RESPONSE, G = 1000 LARGE-SIGNAL RESPONSE, G = 1000 +200mV +10V -200mV -10V (R) 9 PGA204/205 TYPICAL PERFORMANCE CURVES At TA = +25C, and VS = 15V, unless otherwise noted. INPUT-REFERRED NOISE, 0.1 TO 10Hz, G = 1000 (CONT) NOISE, 0.1 TO 10Hz, G = 1 0.2V/Div 0.5V/Div 1s/Div 1s/Div APPLICATION INFORMATION Figure 1 shows the basic connections required for operation of the PGA204/205. Applications with noisy or high impedance power supplies may require decoupling capacitors close to the device pins as shown. The output is referred to the output reference (Ref) terminal which is normally grounded. This must be a low-impedance connection to assure good common-mode rejection. A resistance of 5 in series with the Ref pin will cause a typical device to degrade to approximately 80dB CMR (G=1). The PGA204/205 has an output feedback connection (pin 12). Pin 12 must be connected to the output terminal (pin 11) for proper operation. The output Feedback connection can be used to sense the output voltage directly at the load for best accuracy. DIGITAL INPUTS The digital inputs A0 and A1 select the gain according to the logic table in Figure 1. Logic "1" is defined as a voltage greater than 2V above digital ground potential (pin 14). Digital ground can be connected to any potential from the V- power supply to 4V less than V+. Digital ground is normally connected to ground. The digital inputs interface directly CMOS and TTL logic components. Approximately 1A flows out of the digital input pins when a logic "0" is applied. Logic input current is nearly zero with a logic "1" input. A constant current of approximately +15V 1F VO1 1 PGA204 PGA205 - VIN 4 Over-Voltage Protection Feedback 12 A1 25k 25k 16 15 14 + - VO = G (VIN - VIN) Digitally Selected Feedback Network A3 11 VO + VIN 5 Over-Voltage Protection 6 A2 25k 7 VOS Adj 9 VO2 8 1F VIN +15V + VIN - 25k Ref 10 Sometimes shown in simplified form: GAIN PGA204 PGA205 1 10 100 1000 1 2 4 8 A 1 A0 0 0 1 1 0 1 0 1 PGA204 VO A1 A0 FIGURE 1. Basic Connections. (R) PGA204/205 10 V+ 4 - VIN 100k 100k 16 15 14 Digitally Selected Feedback Network Over-Voltage Protection A1 Some applications select gain of the PGA204/205 with switches or jumpers. Figure 2 shows pull-up resistors connected to assure a noise-free logic "1" when the switch, jumper or open-collector logic is open or off. Fixed-gain applications can connect the logic inputs directly to V+ or V- (or other valid logic level); no resistor is required. OFFSET VOLTAGE Voltage offset of the PGA204/205 consists of two components--input stage offset and output stage offset. Both components are specified in the specification table in equation form: 7 9 VO2 + VIN Switches, jumpers or open-collector logic output. 5 Over-Voltage Protection 6 A2 Digital ground can alternatively be connected to V- power supply. VOS Adj VOS = VOSI + VOSO / G (1) FIGURE 2. Switch or Jumper-Selected Digital Inputs. 1.3mA flows in the digital ground pin. It is good practice to return digital ground through a separate connection path so that analog ground is not affected by the digital ground current. The digital inputs, A0 and A1, are not latched; a change in logic inputs immediately selects a new gain. Switching time of the logic is approximately 1s. The time to respond to gain change is effectively the time it takes the amplifier to settle to a new output voltage in the newly selected gain (see settling time specifications). Many applications use an external logic latch to access gain control data from a high speed data bus (see Figure 7). Using an external latch isolates the high speed digital bus from sensitive analog circuitry. Locate the latch circuitry as far as practical from analog circuitry. where: VOS total is the combined offset, referred to the input. VOSI is the offset voltage of the input stage, A1 and A2. VOSO is the offset voltage of the output difference amplifier, A3. VOSI and VOSO do not change with gain. The composite offset voltage VOS changes with gain because of the gain term in equation 1. Input stage offset dominates in high gain (G100); both sources of offset may contribute at low gain (G=1 to 10). OFFSET TRIMMING Both the input and output stages are laser trimmed for very low offset voltage and drift. Many applications require no external offset adjustment. Figure 3 shows an optional input offset voltage trim circuit. This circuit should be used to adjust only the input stage offset voltage of the PGA204/205. Do this by programming VO1 1 - VIN 4 Over-Voltage Protection V+ 13 PGA204 PGA205 Feedback 12 Resistors can be substituted for REF200. Power supply rejection will be degraded. 11 + - VO = G (VIN - VIN) + VREF A1 25k 25k A1 A0 Digital Ground + VIN 16 15 14 VREF 25k 6 7 9 VO2 Input Offset Adjustment Trim Range 250V 200k to 1M V+ 8 V- 10mV Adjustment Range Output Offset Adjustment 25k 10 OPA177 Digitally Selected Feedback Network A3 V+ 5 Over-Voltage Protection A2 100A 1/2 REF200 100 10k 100 100A 1/2 REF200 V- FIGURE 3. Optional Offset Voltage Trim Circuit. (R) 11 PGA204/205 it to its highest gain and trimming the output voltage to zero with the inputs grounded. Drift performance usually improves slightly when the input offset is nulled with this procedure. Do not use the input offset adjustment to trim system offset or offset produced by a sensor. Nulling offset that is not produced by the input amplifiers will increase temperature drift by approximately 3.3V/C per 1mV of offset adjustment. Many applications that need input stage offset adjustment do not need output stage offset adjustment. Figure 3 also shows a circuit for adjusting output offset voltage. First, adjust the input offset voltage as discussed above. Then program the device for G=1 and adjust the output to zero. Because of the interaction of these two adjustments at G=8, the PGA205 may require iterative adjustment. The output offset adjustment can be used to trim sensor or system offsets without affecting drift. The voltage applied to the Ref terminal is summed with the output signal. Low impedance must be maintained at this node to assure good common-mode rejection. This is achieved by buffering the trim voltage with an op amp as shown. NOISE PERFORMANCE The PGA204/205 provides very low noise in most applications. Low frequency noise is approximately 0.4Vp-p measured from 0.1 to 10Hz. This is approximately one-tenth the noise of "low noise" chopper-stabilized amplifiers. INPUT BIAS CURRENT RETURN PATH The input impedance of the PGA204/205 is extremely high-- approximately 1010. However, a path must be provided for the input bias current of both inputs. This input bias current is typically less than 1nA (it can be either polarity due to cancellation circuitry). High input impedance means that this input bias current changes very little with varying input voltage. Input circuitry must provide a path for this input bias current if the PGA204/205 is to operate properly. Figure 4 shows provisions for an input bias current path. Without a bias current return path, the inputs will float to a potential which exceeds the common-mode range of the PGA204/205 and the input amplifiers will saturate. If the differential source resistance is low, bias current return path can be connected to one input (see thermocouple example in Figure 4). With higher source impedance, using two resistors provides a balanced input with possible advantages of lower input offset voltage due bias current and better common-mode rejection. Many sources or sensors inherently provide a path for input bias current (e.g. the bridge sensor shown in Figure 4). These applications do not require additional resistor(s) for proper operation. Microphone, Hydrophone etc. PGA204 47k 47k Thermocouple PGA204 10k PGA204 VR Center-tap provides bias current return. Bridge PGA204 Bias current return inherrently provided by source. FIGURE 4. Providing an Input Common-Mode Current Path. INPUT COMMON-MODE RANGE The linear common-mode range of the input op amps of the PGA204/205 is approximately 12.7V (or 2.3V from the power supplies). As the output voltage increases, however, the linear input range will be limited by the output voltage swing of the input amplifiers, A1 and A2. The commonmode range is related to the output voltage of the complete amplifier--see performance curve "Input Common-Mode Range vs Output Voltage". A combination of common-mode and differential input voltage can cause the output of A1 or A2 to saturate. Figure 5 shows the output voltage swing of A1 and A2 expressed in terms of a common-mode and differential input voltages. Output swing capability of these internal amplifiers is the same as the output amplifier, A3. For applications where input common-mode range must be maximized, limit the output voltage swing by selecting a lower gain of the PGA204/205 (see performance curve "Input Common-Mode Voltage Range vs Output Voltage"). If necessary, add gain after the PGA204/205 to increase the voltage swing. (R) PGA204/205 12 VCM - 4 Over-Voltage Protection G * VD 2 VO1 1 V+ 13 PGA204 PGA205 Feedback 12 A1 25k 25k VD 2 A1 A0 VD 2 VCM 16 15 14 Digitally Selected Feedback Network A3 11 VO Digital Ground 5 Over-Voltage Protection A2 25k 9 VCM + G * VD 2 VO2 8 V- 25k 10 Ref FIGURE 5. Voltage Swing of A1 and A2. Input-overload often produces an output voltage that appears normal. For example, consider an input voltage of +20V on one input and +40V on the other input will obviously exceed the linear common-mode range of both input amplifiers. Since both input amplifiers are saturated to the nearly the same output voltage limit, the difference voltage measured by the output amplifier will be near zero. The output of the PGA204/205 will be near 0V even though both inputs are overloaded. INPUT PROTECTION The inputs of the PGA204/205 are individually protected for voltages up to 40V. For example, a condition of -40V on one input and +40V on the other input will not cause damage. Internal circuitry on each input provides low series impedance under normal signal conditions. To provide equivalent protection, series input resistors would contribute excessive noise. If the input is overloaded, the protection circuitry limits the input current to a safe value (approximately 1.5mA). The typical performance curve "Input Bias Current vs Common-Mode Input Voltage" shows this input current limit behavior. The inputs are protected even if no power supply voltage is present. V+ 47k - VIN 47k A1 A0 + VIN B A C D X PGA204 PGA205 D1, D2: IN4148, IN914, etc. SWITCH POSITION A B C D GAIN PGA204 1 10 100 1000 PGA205 1 2 4 8 FIGURE 6. Switch-Selected PGIA. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. (R) 13 PGA204/205 +15V 14 4 5 - VIN 6 7 13 12 + VIN 11 10 A0 3 15 -15V 1 A1 16 5 Over-Voltage Protection 6 VOS Adj 9 A2 25k 7 9 VO2 8 V- 25k 10 Ref A1 A0 16 15 14 Digitally Selected Feedback Network A3 11 VO 8 2 HI-509 4 Over-Voltage Protection VO1 1 V+ 13 PGA204 PGA205 A1 25k 25k Feedback 12 Data Out 74HC574 Data In Data Bus CK To Address Decoding Logic FIGURE 7. Multiplexed-Input Programmable Gain IA. A0 A1 VO1 - VIN + VIN PGA204 PGA205 VO2 220 A1 A0 20k 20k VO Ref OPA177 FIGURE 8. Shield Drive Circuit. + VIN A1 - VIN AO PGA205 A1 AO PGA205 VO - VIN + PGA204 PGA205 Ref A1 A0 C1 0.1F VO R1 1M GAIN 1 2 4 8 16 32 64 A3 0 0 1 1 1 1 1 A2 0 1 0 1 1 1 1 A1 0 0 0 0 0 1 1 A0 0 0 0 0 1 0 1 OPA602 f-3dB = 1 2R1C1 = 1.59Hz FIGURE 9. Binary Gain Steps, G=1 to G=64. (R) FIGURE 10. AC-Coupled PGIA. PGA204/205 14 |
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