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STV9420 STV9421
MULTISYNC ON-SCREEN DISPLAY FOR MONITOR
. . . . . . . . . . . . . .
CMOS SINGLE CHIP OSD FOR MONITOR BUILT IN 1 KBYTE RAM HOLDING : - PAGES' DESCRIPTORS - CHARACTER CODES - USER DEFINABLE CHARACTERS 128 ALPHANUMERIC CHARACTERS OR GRAPHIC SYMBOLS IN INTERNAL ROM (12 x 18 DOT MATRIX) UP TO 26 USER DEFINABLE CHARACTERS INTERNAL HORIZONTAL PLL (15 TO 120kHz) PROGRAMMABLE VERTICAL HEIGHT OF CHARACTER WITH A SLICE INTERPOLATOR TO MEET MULTI-SYNCH REQUIREMENTS PROGRAMMABLE VERTICAL AND HORIZONTAL POSITIONING FLEXIBLE SCREEN DESCRIPTION CHARACTER BY CHARACTER COLOR SELECTION (UP TO 8 DIFFERENT COLORS) PROGRAMMABLE BACKGROUND (COLOR, TRANSPARENT OR WITH SHADOWING) CHARACTER BLINKING 2-WIRES ASYNCHRONOUS SERIAL MCU INTERFACE (I2C PROTOCOL) 4 x 8 BITS PWM DAC OUTPUTS ON THE STV9421 SINGLE POSITIVE 5V SUPPLY
DIP16 (Plastic Package) ORDER CODE : STV9420
DESCRIPTION The STV9420/21 is an ON SCREEN DISPLAY for monitor. It is built as a slave peripheral connected to a host MCU via a serial I2C bus. It includes a display memory, controls all the display attributes and generates pixels from the data read in its on chip memory. The line PLL and a special slice interpolator allow to have a display aspect which does not depend on the line and frame frequencies. I2C interface allows MCU to make transparent internal access to prepare the next pages during the display of the current page. Toggle from one page to another by programming only one register. 4 x 8 bits PWM DAC are available (STV9421) to provide DC voltage control to other peripherals. The STV9420/21 provides the user an easy to use and cost effective solution to display alphanumeric or graphic information on monitor screen.
October 1995
DIP20 (Plastic Package) ORDER CODE : STV9421
1/16
STV9420 - STV9421
PIN CONNECTIONS
DIP16
FBLK H-SYNC V-SYNC VDD PXCK CKOUT XTALOUT XTALIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 TEST B G R GND RESET SDA SCL
DIP20 PWM1 FBLK H-SYNC V-SYNC VDD PXCK CKOUT XTALOUT XTALIN PWM4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PWM3 TEST B G R GND RESET SDA SCL PWM2
9420-01.AI / 9421-01.AI 9420-01.TBL
PIN DESCRIPTION
Symbol PWM1 FBLK H-SYNC V-SYNC VDD PXCK CKOUT XTALOUT XTALIN PWM4 PWM2 SCL SDA RESET GND R G B TEST PWM3 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 Pin Number DIP16 DIP20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 I/O O O I I S O O O I O O I I/O I S O O O I O DAC1 Output Fast Blanking Output Horizontal Sync Input Vertical Sync Input +5V Supply Pixel Frequency Output Clock Output Crystal Output Crystal or Clock Input DAC4 Output DAC2 Output Serial Clock Serial Input/output Data Reset Input Ground Red Output Green Output Blue Output Reserved (grounded in Normal Operation) DAC3 Output Description
2/16
STV9420 - STV9421
BLOCK DIAGRAMS STV9420
XTAL IN
8
XTAL OUT
7
PXCK
5
VDD
4
TES T
16
CKOUT 6 HS YNC 2
HORIZONTAL DIGITAL P LL
4K ROM (128 cha ra cte rs )
1K RAM P age De s criptors + Us e r De fine d Cha r.
Addre ss /Da ta
VSYNC 3 RESE T 11
DISPLAY CONTROLLER
I C BUS INTERFACE
2
13
14
15
1
12
9
10
R
G
B
FBLK
GND
S CL
S DA
STV9421
XTAL XTAL IN OUT P XCK
9 8 6
VDD
5
TES T
19
CKOUT 7 HSYNC 3
HORIZONTAL DIGITAL P LL
4K ROM (128 cha racte rs )
1K RAM P a ge Des criptors + Use r Define d Cha r. PWM
10 P WM4 20 P WM3 11 P WM2 1 P WM1
Addres s /Data
VSYNC 4 RES ET 14
DISP LAY CONTROLLER
I C BUS INTERFACE
2
16
17
18
2
15
12
13
R
G
B
FBLK
GND
S CL
S DA
3/16
9421-02.EPS
STV9421
9420-02.EPS
S TV9420
STV9420 - STV9421
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VIN Toper Tstg Supply Voltage Input Voltage Operating Ambient Temperature Storage Temperature Parameter Value -0.3, +7.0 -0.3, +7.0 0, +70 -40, +125 Unit V C C
9420-02.TBL 9420-03.TBL
V
ELECTRICAL CHARACTERISTICS (VDD = 5V, VSS = 0V, TA = 0 to 70C, FXTAL = 8 to 15MHz, TEST = 0 V, unless otherwise specified)
Symbol SUPPLY VDD IDD INPUTS SCL, SDA, TEST, RESET, V-SYNC and H-SYNC VIL VIH IIL OUTPUTS R, G, B, FBLK, SDA, CKOUT, PXCK and PWMi (i = 1 to 4) VOL VOH Output Low Voltage (I OL = 1.6mA) Output High Voltage (IOL = -0.1mA) 0 0.8 VDD 0.4 VDD V V Input Low Voltage Input High Voltage Input Leakage Current 0.8 VDD -20 +20 0.8 V V A Supply Voltage Supply Current 4.75 5 5.25 50 V mA Parameter Min. Typ. Max. Unit
For R, G, B and FBLK outputs, see Figure 1.
Figure 1 : Typical R, G, B Outputs Characteristics
5 VOL , VOH (V)
VOH 2.5
VOL 0 10 -5 10 -4 10 -3 10 -2 10 -1
9420-17.EPS
I (A)
4/16
STV9420 - STV9421
TIMINGS
Symbol Parameter Min. Typ. Max. Unit OSCILATOR INPUT : XTI (see Figure 2) tWH tWL fXTAL fPXL RESET tRES Reset High Level Pulse 4 s Clock High Level Clock Low Level Clock Frequency Pixel Frequency 35 35 6 15 30 ns ns MHz MHz
R, G, B, FBLK (CLOAD = 30pF) tR tF tSKEW
2
Rise Time (Note 1) Fall Time (Note 1) Skew between R, G, B, FBLK (Note 1)
5 5 5
ns ns ns
I C INTERFACE : SDA AND SCL (see Figure 3) fSCL tBUF tHDS tSUP tLOW tHIGH tHDAT tSUDAT tF tR SCL Clock Frequency Time the bus must be free between 2 access Hold Time for Start Condition Set up Time for Stop Condition The Low Period of Clock The High Period of Clock Hold Time Data Set up Time Data Fall Time of SDA Rise Time of Both SCL and SDA 0 500 500 500 400 400 0 375 20 Depend on the pull-up resistor and the load capacitance 1 MHz ns ns ns ns ns ns ns
9420-04.TBL
ns
Note 1 : These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches comming from corners of our processes and also temperature characterization.
Figure 2
Figure 3
S T OP S TART DATA tHDAT S TOP tBUF S DA
tWL XTI
9420-03.EPS
S CL tHIGH tLOW
5/16
9420-04.EPS
tWH
tHDS
tS UDAT
tS UP
STV9420 - STV9421
FUNCTIONAL DESCRIPTION The STV9420/21 display processor operation is controlled by a host MCU via the I2C interface. It is fully programmable through 8 internal read/write registers (12 for STV9421) and performs all the display functions by generating pixels from data stored in its internal memory. After the page downloading from the MCU, the STV9420/21 refreshes screen by its built in processor, without any MCU control (access).In addition, the host MCU has a direct access to the on chip 1Kbytes RAM during the display of the current page to make any update of its contents. With the STV9420/21, a page displayed on the screen is made of several strips which can be of 2 types : spacing or character and which are described by a table of descriptors and character codes in RAM. Several pages can be downloaded at the same time in the RAM and the choice of the current display page is made by programming the CONTROL register. I - Serial Interface The 2-wires serial interface is an I2C interface. To be connected to the I2C bus, a device must own its slave ad dress ; the sla ve address of t he STV9420/21 is BA (in hexadecimal).
A6 1 A5 0 A4 1 A3 1 A2 1 A1 0 A0 1 R/W
I.1 - Data Transfer in Write Mode The host MCU can write data into the STV9420/21 registers or RAM. To write data into the STV9420/21, after a start, the MCU must send (Figure 3) : - First, the I2C address slave byte with a low level for the R/W bit, - The two bytes of the internal address where the MCU wants to write data(s), - The successive bytes of data(s). All bytes are sent MS bit first and the write data transfer is closed by a stop. I.2 - Data Transfer in Read Mode The host MCU can read data from the STV9420/21 registers, RAM or ROM. To read data from the STV9420/21 (Figure 4), the MCU must send 2 different I2C sequences. The first one is made of I2C slave address byte with R/W bit at low level and the 2 internal address bytes. The second one is made of I2C slave address byte with R/W bit at high level and all the successive data bytes read at successive addresses starting from the initial address given by the first sequence.
Figure 3 : STV9420/I2C Write Operation
SCL R/W SDA Start I2C Slave Address ACK
A7
A6
A5
A4
A3
A2
A1
A0 ACK
-
-
A13 A12
A11 A10
A9
A8 ACK
LSB Address
MSB Address
SCL
SDA
D7
D6
D5
D4
D3
D2
D1
D0 ACK
D7
D6
D5
D4
D3
D2
D1
D0 ACK
D7
D6
D5
D4
D3
D2
D1
D0 ACK Stop
9420-05.AI 9420-06.EPS
Data Byte 1
Data Byte 2
Data Byte n
Figure 4 : STV9420/I2C Read Operation
SCL
R/W
SDA
A7
ACK
A6
A5
A4
A3
A2
A1
A0
ACK
-
-
A13 A12 A10 A10 A9
MSB Address
A8
ACK Stop
Start
I1C
Slave Address
LSB Address
SCL
SDA
R/W Start I1C Slave Address ACK
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte 1
ACK
Data Byte n
ACK
Stop
6/16
STV9420 - STV9421
FUNCTIONAL DESCRIPTION (continued) I.3 - Addressing Space STV9420/21registers, RAM and ROM are mapped in a 16Kbytes addressing space. The mapping is the following : 0000 Descriptors character 1024 bytes codes user definable RAM characters 03FF 0400 Empty Space 1FFF 2000 Character Generator ROM 32FF 3300 Empty Space 3FFF 3FF0 Internal Registers 3FFF I.4 - Register Set LINE DURATION
3FF0 * LD5 LD4 LD3 LD2 LD1 LD0 1 1 1 1 1 1
DISPLAY CONTROL
3FF3 * OSD FBK FL1 0 0 0 FL0 0 P8 0 P7 0 P6 0
: ON/OFF (if 0, R, G, B and FBLK are 0). : Fast blanking control : = 1 : FBLK = 1, forcing black where these is no display, = 0 : FBLK is active only during character display. FL[1:0] : Flashing mode : - 00 : No flashing. The character attribute is ignored, - 01 : 1/1 flashing (a duty cycle = 50%), - 10 : 1/3 flashing, - 11 : 3/1 flashing. P[8:6] : Address of the 1st descriptor of the current displayed pages. P[13:9] and P[5:0] = 0 ; up to 8 different pages can be stored in the RAM. LOCKING CONDITION TIME CONSTANT
3FF4 * FR 0 AS2 AS1 AS0 0 1 0 BS2 BS1 BS0 0 1 0
OSD FBK
FR
: Free Running ; if = 1 PLL is disabled and the pixel frequency keeps its last value. AS[2:0] : Ph a s e co n st a n t d urin g lo c kin g conditions. BS[2:0] : Frequency constant during locking conditions. CAPTURE PROCESS TIME CONSTANT
3FF5 * AF2 AF1 AF0 0 1 1 BF2 BF1 BF0 0 1 1
LD[5:0] : LINE DURATION (number of character period, 1LSB = 12 pixel periods). HORIZONTAL DELAY
3FF1 * DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 0 0 0 0 1 0 0 0
DD[7:0] : HORIZONTAL DISPLAY DELAY from the H-SYNC reference falling edge to the 1st pixel position of the character strips. Unit = 3 pixel periods. CHARACTERS HEIGHT
3FF2 * CH5 CH4 CH3 CH2 CH1 CH0 0 1 0 0 1 0
AF[2:0] : Phase constant during the capture process. BF[2:0] : Frequency constant during the capture process. INITIAL PIXEL PERIOD
3FF6 * PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 0 0 1 0 1 0 0 0
PP[7:0] : Value to initialize the pixel period of the PLL. FREQUENCY MULTIPLIER
3FF7 * FM3 FM2 FM1 FM0 1 0 1 0
CH[5:0] : HEIGHT of the character strips in scan lines. For each scan line, the number of the slice which is displayed is given by :
S LI CE -NU MBER = SCANLINENUMBER x 18 round CH[5:0] SCAN-LINE-NUMBER = Number of the current scan line of the strip.
FM[3:0] : Frequency multiplier of the crystal frequency to reach the high frequency used by the PLL to derive the pixel frequency.
7/16
STV9420 - STV9421
FUNCTIONAL DESCRIPTION (continued) The last fourth registers described below are only available with the STV9421 : PULSE WIDTH MODULATOR 1
3FF8 * V17 0 V16 0 V15 V14 0 0 V13 V12 0 0 V11 0 V10 0
SET
V1[7:0] : Digital value of the 1st PWM D to A converter (Pin1). PULSE WIDTH MODULATOR 2
3FF9 * V27 0 V26 0 V25 V24 0 0 V23 V22 0 0 V21 0 V20 0
V2[7:0] : Digital value of the 2d PWM DAC (Pin11). PULSE WIDTH MODULATOR 3
3FFA * V37 0 V36 0 V35 V34 0 0 V33 V32 0 0 V31 0 V30 0
: The set CHARACTER NUMBER - If SET = 0 : ROM character, - If SET = 1 : * If CHARACTER NUMBER is 0 to 25, a user redefinable character (UDC) located in RAM at the a d dr es s eq u a l t o : 3 8 x CHARACTER NUMBER, * If CHARACTER NUMBER is 26 to 63, space character, * If CHARACTER NUMBER >63, end of line.
V3[7:0] : Digital value of the 3rd PWM DAC (Pin20). PULSE WIDTH MODULATOR 4
3FFB * V47 0 V46 0 V45 V44 0 0 V43 V42 0 0 V41 0 V40 0
RF, GF, BF : Foreground color. BK[3:0] : Background : - If BK3 = 0, BK[2:0] = background color R, G and B, - If BK3 = 1, shadowing : * BK2 : vertival shadowing, * BK1 : horizontal shadowing. (if BK2 = BK1 = 0, the background is transparent). IV - Clock and Timing The whole timing is derived from the XTALIN and the SYNCHRO (horizontal and vertival) input frequencies. The XTALIN input frequency can be an external clock or a crystal signal thanks to XTALIN/XTALOUT pins. The value of this frequency can be chosen between 8 and 15MHz, it is available on the CKOUT pin and is used by the PLL to generate a pixel clock locked on the horizontal synchro input signal. IV.1 - Horizontal Timing The number of pixel periods is given by the LINE DURATION register and is equal to : [LD[5:0] + 1 ] x 12 (LD[5:0] : value of the LINE DURATION register). This value allows to choose the horizontal size of the characters. The horizontal left margin is given by the HORIZONTAL DELAY register and is equal to : [DD[7:0] + 8] x 3 x tPXCK (DD[7:0] : value of the DISPLAY DELAY register and TPXCK : pixel period). This value allows to choose the horizontal position of the characters on the screen. The value of DD[7:0] must be equal or greater than 4 (the minimum value of the horizontal delay is 36 x tPXCK = 3 character periods). The length of the active area, where R, G, B are different from 0, depends on the number of characters of the strips.
V4[7:0] : Digital value of the 4th PWM DAC (Pin10).
Note : * is power on reset value.
II - Descriptors SPACING
MSB LSB 0 SL7 SL6 SL1 SL0 SL5 SL4 SL3 SL2
SL[7:0] : The number of the scan lines of the spacing strip (1 to 255). CHARACTER
MSB LSB 1 C7 DE C6 C5 ZY C4 C3 C2 C9 C1 C8 0
C[9:0] : The address of the first character code of the strip (even). DE : Display enable : - DE = 0, R = G = B = 0 and FBLK = FBK (display control register) on whole strip, - DE = 1, display of the characters. ZY : Zoom, ZY = 1 all the scan lines are repeated once. III - Code Format
MSB LSB SET CHARACTER NUMBER FL RF GF BF BK3 BK2 BK1 BK0
FL : Flashing attribute (the flashing mode is defined in the DISPLAY CONTROL register).
8/16
STV9420 - STV9421
FUNCTIONAL DESCRIPTION (continued) Figure 5 : Horizontal Timing
H-SYNC
R, G, B 0 1 2 3 n +1 n+2 n+3 n +4 LD - 1 LD 0 1
Character Period LD[5:0] Fixed DD[7:0] Given by number of characters of the strips
= 4 (min)
= 4n + 2
9420-07.AI
IV.2 - D to A Timing (STV9421) The D to A converters of the STV9421 are pulse width modulater converter. FXTAL The frequency of the output signal is : 256 V1[7:0] and the duty cycle is : per cent. 256 After a low pass filter, the average value of the V1 [7:0] output is : VDD 256 Figure 6 : PWM Timing
P WM1 S ignal V1[7:0] 0 tXTAL 1 256 . tXTAL
255
V - Display Control A screen is composedof successive scanlines gathered in several strips. Each strip is defined by a descriptor stored in memory. A table of descriptors
9420-08.EPS
128
allows screen composition and different tables can be stored in memory at the page addresses (8 possible addresses). Two types of strips are available : - Spacing strip : its descriptor (see II) gives the number of black (FBK = 1 in DISPLAY CONTROL register) or transparent (FBK = 0) lines. - Character strip : its descriptor gives the memory address of the character codes corresponding to the 1st displayed character. The characters and attributes (see code format III) are defined by a succession of codes stored in the RAM at addresses starting from the 1st one given by the descriptor. A character strip can be displayed or not by using the DE bit of its descriptor. A zoom can be made on it by using the ZY bit. After the falling edge on V-SYNC, the first strip descriptor is read at the top of the current table of descriptors at the address given by P[8:6] (see DISPLAY CONTROL register) ; if it is a spacing strip, SL[7:0] black or transparent scan lines are displayed ; if it is a character strip, during CH[5:0] x (I + ZY) scan lines (CH[5:0] given by the CHARACTER HEIGHT register), the character codes are read at the addresses starting from the 1st one given by the descriptor until a end of line character or the end of the scan line ; the next descriptor is then read and the same process is repeated until the next falling edge on V-SYNC.
9/16
STV9420 - STV9421
FUNCTIONAL DESCRIPTION (continued) Figure 7 : Relation between Screen/Address Page/Character Code in RAM
DISPLAY CONTROL Register CSD FBK FL[1:0] P8 P7 P8 V-SYNC
TOP SPACING STRIP 2nd CHARACTER STRIP CODES OTHER TABLE OF DESCRIPTORS OTHER (UDC for example) 1st CHARACTER STRIP CODES 3rd CHARACTER SRTIP CODES OTHER (CODES OR DESCRIPTORS) RAM CODE AND DESCRIPTORS SPACING 1st CHARACTER STRIP ROW1 2nd CHARACTER STRIP ROW2 SPACING STRIP SPACING 3rd CHARACTER STRIP ROW3 | BOTTOM SPACING STRIP SPACING TABLE OF THE DESCRIPTORS SCREEN
Figure 8 : User Definable Character
ON THE SCREEN 36 Pixels (= 3 Characters) 1 2 3 Character Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
IN THE RAM (example for Character n5)
Slice 0 Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
: 0x01 : : : : : : : : : : : : : : : : : : 0x00 0x08 0x0c 0x0e 0x0f 0x0f 0x0f 0x0f 0x0e 0x0c 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Odd Address
0xff = Slice 18 of the character n2 only for vertical shadowing (not displayed). 0xff 0x7f 0x3f 0x1f 0x1f 0x1f 0x1e 0x1e 0x3c 0x3c 0x78 0x78 0xf1 0x00 0x00 0x00 0x00 0x00 Even Address
36 Slices (= 2 Characters)
4
5
6
Character Number
10/16
9420-10.AI
9420-09.EPS
STV9420 - STV9421
FUNCTIONAL DESCRIPTION (continued) Table 1 : ROM Character Generator
CHARACTERNUMBER C(6:0) C(6:4) C(3:0) 0 1 2 3 4 5 6 7
0
1
2
3
4
5
6
7
8
9
a
b
c
d
e
f
11/16
9420-11.EPS
STV9420 - STV9421
FUNCTIONAL DESCRIPTION (continued) VI - User Definable Character The STV9420/21 allows the user to dynamically define character(s) for his own needs (for a special LOGO for example). Like the ROM characters, a UDC is made of a 12 pixels x 18 slices dot matrix, but one more slice is added for the vertical shadowing when several UDCs are gathered to make a special great character (see Figure 8). In a UDC, each pixel is defined with a bit, 1 refers to foreground, and 0 to background color. Each slice of a UDC uses 2 bytes :
add + 1 add (even) PX11 PX10 PX9 PX8
D(n) ALGO err(n)
9420-13.AI
The second PLL, full digital (see Figure 10), provides a pixel frequency locked on the horizontal synchro signal. The ratio between the frequencies of these 2 signals is :M = 12 x (LD[5:0] + 1) Where LD[5:0] is the value of the LINE DURATION register. Figure 10 : Digital PLL
M . FH-SYNC N . FXTAL %D %M FH-SYNC
PX7 PX6 PX5 PX4 PX3 PX2 PX1 PX0
PX11 is the left most pixel. Character slice address : SLICE ADDRESS = 38 x (CHARACTER NUMBER) + (SLICE NUMBER). Where : - CHARACTER NUMBER is the number given by the character code, - SLICE NUMBER is the number given by the slice interpolator (n of the current slice of the strip : 1 < <18) VII - ROM Character Generator The STV9420/21 includes a ROM character generator which is made of 128 alphanumeric or graphic characters (see Table 1) VIII - PLL The PLL function of the STV9420/21 provides the internal pixel clock locked on the horizontal synchro signal and used by the display processor to generate the R, G, B and fast blanckingsignals.It ismade of 2 PLLs. The first one analogic (see Figure 9), provides a high frequency signal locked on the crystal frequency. The frequency multiplier is given by : N = 2 (FM[3:0] + 3) Where FM[3:0] is the value of the FREQUENCY MULTIPLIER register. Figure 9 : Analogic PLL
N . FXTAL VCO %N FXTAL
VIII.1 - Programming of the PLL Registers Frequency Multiplier (@3FF7) This register gives the ratio between the crystal frequency and the high frequency of the signal used by the 2nd PLL to provide,by division, the pixel clock. The value of this high frequency must be near to 200MHz (for example if the crystal is a 8MHz, the value of FM must be equal to 10) and greater than 6 x (pixel frequency). Initial Pixel Period (@3FF6) This register allows to increase the speed of the convergence of the PLL when the horizontal frequency changes (new graphic standart). The relationshipbetween FM[3:0], PP[7:0], LD[5:0], FHSYNC and FXTAL is :
2 (FM[3:0] + 3) FXTAL PP[7:0] = round 8 24 12 LD[5:0] FHSYNC
FILTRE
Locking Condition Time Constant (@ 3FF4) This register gives the constants AS[2:0] and BS[2:0] used by the algo part of the PLL (see Figure 10) to calculate, from the phase error, err(n), the new value, D(n), of the division of the high frequency signal to provide the pixel clock. These two constants are used only in locking condition, which is true, if the phase error is less than a fixed value during at least, 4 scan lines. If The phase error becomes greater than the fixed value, the PLL is not in locking condition but in capture process. In this case, the algo part of the PLL used the other constants, AF[2:0] and BF[2:0], given by the next register. Capture Process Time Constant (@ 3FF5) The choice between these two time constants (locking condition or capture process) allows to decrease the capture process time by changing the time response of the PLL.
12/16
9420-12.AI
STV9420 - STV9421
FUNCTIONAL DESCRIPTION (continued) VIII.2 - How to choose the value of the time constant ? The time response of the PLL is given by its characteristic equation which is : (x 1)2 + ( + ) (x 1) + = 0. Where : = 3 LD[5:0] 2A 11 and = 3 LD[5:0] 2B 19. (LD[5:0] = value of the LINE DURATION register, A = value of the 1st time constant, AF or AS and B = value of the 2d time constant, BF or BS). As you can see, the solution depend only on the LINE DURATION and the TIME CONSTANTS given by the I2C registers. If ( + )2 4 0 and 2 < 4, the PLL is stable and its response is like this presented on Figure 11. Figure 11 : Time Response of the PLL/Characteristic Equation Solutions (with Real Solutions)
PLL Frequency f1 f0 Input Frequency
9420-14.AI
In this case the PLL is stable if > 0.7 (damping coefficient). Figure 12 : Time Response of the PLL/Characteristic Equation Solutions (with Complex Solutions)
PLL Frequency f1 f0 Input Frequency
9420-115.AI
t
f1 f0 t
The Table 2 gives some good values for A and B constants for different values of the LINE DURATION. Summary For a good working of the PLL : - A and B time constants must be chosen among values for which the PLL is stable, - B must be equal or greater than A and the difference between them must be less than 3, - The greater (A, B) are, the faster the capture is. An optimalchoice for the most of applications might be : - For locking condition : AS = 0 and BS = 1, - For capture process : AS = 2 and BS = 4. But for each application the time constants can be calculated by solving the characteristic equation and choosing the best response.
t
f1 f0
2
t
If ( + ) 4 0, the response of the PLL is like this presented on Figure 12. Table 2 : Valid Time Constants Examples
B\A 0 1 2 3 4 5 6 7
LD Valid Time Constants
Note : 1. Case of A[2:0] = 1 (001) and B[2:0] = 4 (100) : 16 N 32 Y 48 Y 63 Y Value of LINE DURATION Register (@ 3FF0) : LD = 16 : LD[5:0] = 010000 LD = 32 : LD[5:0] = 100000 LD = 48 : LD[5:0] = 110000 LD = 63 : LD[5:0] = 111111 Table meaning : N = No possible capture Y = PLL can lock
13/16
9420-05.TBL
0 YYYY YYYY NYYY NNNY NNNN NNNN NNNN NNNN
1 YYYY YYYY YYYY YYYY (1) NYYY NNNY NNNN NNNN
2 YYYY YYYY YYYY YYYY YYYY YYYY NYYY NNNY
3 YYYN YYYN YYYN YYYN YYYN YYYN YYYN YYYN
4 YNNN YNNN YNNN YNNN YNNN YNNN YNNN YNNN
5 NNNN NNNN NNNN NNNN NNNN NNNN NNNN NNNN
6 NNNN NNNN NNNN NNNN NNNN NNNN NNNN NNNN
STV9420 - STV9421
DEMO KIT
5V POWER SUPPLY VCC J5 C6 100nF J6 R10 3.3k J2 1 6 11 2 7 12 3 8 13 4 9 14 5 10 15 to PC J3 1 6 11 2 7 12 3 8 13 4 9 14 5 10 15 PC mon J4 1 6 11 2 7 12 3 8 13 4 9 14 5 10 15 APPL mon VCC C3 100nF OSD PWM1 OSD FBLK
2 19 1
S2 VCC R9 75 R17 10 BC547B T1 R8 82 R22 1.8k S3 R12 75 1N4148 VGA1 G R18 10 R13 3.3k D2 OSD G 1N4148 R19 10 R16 3.3k OSD B D3 1N4148 BC547B T3 R14 82 R20 1.8k R15 75 BC547B T2 R11 82 R21 1.8k S4
VGA2 R VGA1 R VGA3 R
C7 470F
D1 VGA1 R OSD R
VGA2 G VGA1 G VGA3 G
VGA1 B
VGA2 B VGA1 B VGA3 B
VGA2 R
VGA2 G
VGA2 B U2A H-SYNC R2 1k 1 3 2 10 74HC86 C2 10F 74HC86 9 8 OSD HS U2C OSD PWM1 OSD PWM2 OSD PWM3 OSD PWM4 OSD HS OSD VS OSD R VCC VGA3 R OSD G OSD B OSD FBLK VGA3 G OSD PXCK OSD CKOUT VGA3 B U2B V-SYNC R1 1k R5 1k R6 1k 4 6 5 74HC86 74HC86 C1 10F 13 12 11 OSD VS TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 U2D TP14 TP15
VCC Reset Button
20
VCC
S1 OSD PWM3 R4 2.2k R3 2.2k
OSD HS
3
OSD VS
4 5
OSD PXCK OSD CKOUT
6 7 8 9
S T V 9 4 2 1
18 17 16 15 14 13 12 11
OSD B OSD G OSD R
VCC OSD SDA OSD SCL OSD PWM2 R7 2.2k
J1 4 3 2 1 I2 C
OSD PWM4 Q1 12MHz
10
C4 47pF
C5 47pF
14/16
9420-16.EPS
A demonstration board is available through your usual SGS-THOMSON Sales Office. This demonstration board alllows to test very easily the STV9420/21 performances on any personnal computer. The board is delivered together with a "page maker" software which allows to easily generate pages of text or graphics on the PC monitor, or on a second monitor. The I2C sequences are generated by the PC parallel port and send to the demobaord through an I2C interface which is also delivered together with demoboard. Of course, a small manual is also inside the kit.
STV9420 - STV9421
PACKAGE MECHANICAL DATA (STV9420) 16 PINS - PLASTIC DIP
Dimensions a1 B b b1 D E e e3 F I L Z
Min. 0.51 0.77
Millimeters Typ.
Max. 1.65
Min. 0.020 0.030
Inches Typ.
Max. 0.065
0.5 0.25 20 8.5 2.54 17.78 7.1 5.1 3.3 1.27
0.020 0.010 0.787 0.335 0.100 0.700 0.280 0.201 0.130 0.050
DIP16.TBL
15/16
PM-DIP16.WMF
STV9420 - STV9421
PACKAGE MECHANICAL DATA (STV9421) 20 PINS - PLASTIC DIP
Dimensions a1 B b b1 D E e e3 F I L Z
Min. 0.254 1.39
Millimeters Typ.
Max. 1.65
Min. 0.010 0.055
Inches Typ.
Max. 0.065
0.45 0.25 25.4 8.5 2.54 22.86 7.1 3.93 3.3 1.34
0.018 0.010 1.000 0.335 0.100 0.900 0.280 0.155 0.130 0.053
DIP20.TBL
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without noti ce. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1995 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system confo rms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
16/16
PM-DIP20.EPS

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