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(R) DAC 764 (R) DAC7641 1 For most current data sheet and other product information, visit www.burr-brown.com 16-Bit, Voltage Output DIGITAL-TO-ANALOG CONVERTER FEATURES q LOW POWER: 2.5mW q UNIPOLAR OR BIPOLAR OPERATION q SETTLING TIME: 10s to 0.003% q 15-BIT LINEARITY AND MONOTONICITY: -40C to +85C q PROGRAMMABLE RESET TO MID-SCALE OR ZERO-SCALE q DATA READBACK q DOUBLE-BUFFERED DATA INPUTS DESCRIPTION The DAC7641 is a 16-bit, voltage output digital-toanalog converter (DAC) with guaranteed 15-bit monotonic performance over the specified temperature range. It accepts 16-bit parallel input data, has double-buffered DAC input logic (allowing asynchronous update), and provides a readback mode of the internal input registers. Programmable asynchronous reset clears all registers to a mid-scale code of 8000H or to a zero-scale of 0000H. The DAC7641 can operate from a single +5V supply or from +5V and -5V supplies. Low power and small size per DAC make the DAC7641 ideal for automatic test equipment, DAC-per-pin programmers, data acquisition systems, and closedloop servo-control. The DAC7641 is available in a TQFP-32 package, and offers guaranteed specifications over the -40C to +85C temperature range. APPLICATIONS q PROCESS CONTROL q ATE PIN ELECTRONICS q CLOSED-LOOP SERVO-CONTROL q MOTOR CONTROL q DATA ACQUISITION SYSTEMS q DAC-PER-PIN PROGRAMMERS VDD VSS VCC VREFL Sense VREFL VREFH VREFH Sense 16 DATA I/O I/O Buffer Input Register DAC Register DAC VOUT VOUT Sense CS R/W Control Logic DAC7641 AGND DGND RST RSTSEL LDAC International Airport Industrial Park * Mailing Address: PO Box 11400, Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 * Tel: (520) 746-1111 Twx: 910-952-1111 * Internet: http://www.burr-brown.com/ * Cable: BBRCORP * Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132 (R) (c) 2000 Burr-Brown Corporation PDS-1532A 1 Printed in U.S.A. DAC7641 June, 2000 SBAS118 SPECIFICATIONS (Dual Supply) At TA = TMIN to TMAX, VDD = VCC = +5V, VSS = -5V, VREFH = +2.5V, and VREFL = -2.5V, unless otherwise noted. DAC7641Y PARAMETER ACCURACY Linearity Error Differential Linearity Error Monotonicity, TMIN to TMAX Bipolar Zero Error Bipolar Zero Error Drift Full-Scale Error Full-Scale Error Drift Power Supply Rejection Ratio (PSRR) ANALOG OUTPUT Voltage Output Output Current Maximum Load Capacitance Short-Circuit Current Short-Circuit Duration REFERENCE INPUT Ref High Input Voltage Range Ref Low Input Voltage Range Ref High Input Current Ref Low Input Current DYNAMIC PERFORMANCE Settling Time Digital Feedthrough Output Noise Voltage DAC Glitch DIGITAL INPUT VIH VIL IIH IIL DIGITAL OUTPUT VOH VOL POWER SUPPLY VDD VCC VSS ICC IDD ISS Power TEMPERATURE RANGE Specified Performance T Specifications same as DAC7641Y. IOH = -0.8mA IOL = 1.2mA To 0.003%, 5V Output Step f = 10kHz 7FFFH to 8000H or 8000H to 7FFFH 0.7 * VDD 0.3 * VDD 10 10 3.6 4.5 0.3 +5.0 +5.0 -5.0 0.4 15 -0.5 4 T 0.4 +5.25 +5.25 -4.75 0.5 -0.4 5.5 +85 T T T T T T T T T T T T CONDITIONS MIN TYP 3 2 14 1 5 1 5 10 VREFL -1.25 500 -10, +30 Indefinite VREFL + 1.25 -2.5 500 -500 8 2 60 40 10 +2.5 VREFH - 1.25 T T T T T T T T T T T T T 3 10 3 10 100 VREFH +1.25 T T T T T T T MAX 4 3 15 T T T T T T T T T T T T MIN DAC7641YB TYP 2 1 MAX 3 2 UNITS At Full Scale VREF = -2.5V, RL = 10k, VSS = -5V No Oscillation GND or VCC or VSS LSB LSB Bits mV ppm/C mV ppm/C ppm/V V mA pF mA V V A A s nV-s nV/Hz nV-s V V A A V V V V V mA A mA mW C T T T T T +4.75 +4.75 -5.25 -0.6 T T T -40 T The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. (R) DAC7641 2 SPECIFICATIONS (Single Supply) At TA = TMIN to TMAX, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, and VREFL = 0V, unless otherwise noted. DAC7641Y PARAMETER ACCURACY Linearity Error(1) Differential Linearity Error Monotonicity, TMIN to TMAX Zero Scale Error Zero Scale Error Drift Full-Scale Error Full-Scale Error Drift Power Supply Rejection Ratio (PSRR) ANALOG OUTPUT Voltage Output Output Current Maximum Load Capacitance Short-Circuit Current Short-Circuit Duration REFERENCE INPUT Ref High Input Voltage Range Ref Low Input Voltage Range Ref High Input Current Ref Low Input Current DYNAMIC PERFORMANCE Settling Time Digital Feedthrough Output Noise Voltage, f = 10kHz DAC Glitch DIGITAL INPUT VIH VIL IIH IIL DIGITAL OUTPUT VOH VOL POWER SUPPLY VDD VCC VSS ICC IDD Power TEMPERATURE RANGE Specified Performance T Specifications same as DAC7641Y. NOTE: (1) If VSS = 0V specification applies at Code 0040H and above due to possible negative zero-scale error. IOH = -0.8mA IOL = 1.2mA To 0.003%, 2.5V Output Step CONDITIONS MIN TYP 3 2 14 1 5 1 5 10 0 -1.25 500 30 Indefinite VREFL + 1.25 0 250 -250 8 2 60 40 0.7 * VDD 0.3 * VDD 10 10 3.6 4.5 0.3 +5.0 +5.0 0 0.4 15 1.8 T 0.4 +5.25 +5.25 0 0.5 2.5 +85 T T T T T T T T T T T T 10 +2.5 VREFH - 1.25 T T T T T T T T T T T T T 3 10 3 10 100 VREFH +1.25 T T T T T T T MAX 4 3 15 T T T T T T T T T T T T MIN DAC7641YB TYP 2 1 MAX 3 2 UNITS At Full Scale VREFL = 0V, VSS = 0V, RL = 10k No Oscillation GND or VCC LSB LSB Bits mV ppm/C mV ppm/C ppm/V V mA pF mA V V A A s nV-s nV/Hz nV-s V V A A V V V V V mA A mW C 7FFFH to 8000H or 8000H to 7FFFH T T T T T T T +4.75 +4.75 0 -40 (R) 3 DAC7641 ABSOLUTE MAXIMUM RATINGS(1) VSS to VSS ............................................................................. -0.3V to 11V VDD to GND .......................................................................... -0.3V to 5.5V VREFL to GND ............................................................ -0.3V to (VSS - VCC) VREFH to GND ........................................................... -0.3V to (VSS - VCC) VREFH to VREFL .................................................................... -0.3V to +11V Digital Input Voltage to GND ................................... -0.3V to VDD + 0.3V Digital Output Voltage to GND ................................. -0.3V to VDD + 0.3V Maximum Junction Temperature ................................................... +150C Operating Temperature Range ........................................ -40C to +85C Storage Temperature Range ......................................... -65C to +150C Lead Temperature (soldering, 10s) ............................................... +300C NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION MINIMUM RELATIVE ACCURACY (LSB) 4 " 3 " DIFFERENTIAL NONLINEARITY (LSB) 3 " 2 " PACKAGE DRAWING NUMBER 351 " 351 " SPECIFICATION TEMPERATURE RANGE -40C to +85C " -40C to +85C " PRODUCT DAC7641Y " DAC7641YB " PACKAGE TQFP-32 " TQFP-32 " ORDERING NUMBER(1) DAC7641Y/250 DAC7641Y/2K DAC7641YB/250 DAC7641YB/2K TRANSPORT MEDIA Tape Tape Tape Tape and and and and Reel Reel Reel Reel NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of "DAC7641Y/2K" will get a single 2000-piece Tape and Reel. (R) DAC7641 4 PIN CONFIGURATION 27 VREFH Sense 29 VREFL Sense 31 DGND DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 1 2 3 4 DAC7641 5 6 7 8 10 11 12 13 14 15 16 9 25 AGND 24 23 22 21 20 19 18 17 28 VREFH 30 VREFL 32 VDD 26 VCC VSS VOUT Sense VOUT RSTSEL RST LDAC R/W CS DB7 DB6 DB5 DB4 DB3 DB2 DB1 PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 NAME DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CS R/W DESCRIPTION Data Bit 15, MSB Data Bit 14 Data Bit 13 Data Bit 12 Data Bit 11 Data Bit 10 Data Bit 9 Data Bit 8 Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 Data Bit 0, LSB Chip Select, active low. Enabled by CS, controls data read and write from the input register. 24 25 26 27 28 29 30 31 32 VSS AGND VCC VREFH Sense VREFH VREFL Sense VREFL DGND VDD 22 23 VOUT VOUT Sense 21 RSTSEL PIN 19 20 NAME LDAC RST DESCRIPTION DAC Load Strobe, rising-edge triggered. Reset, rising-edge triggered. Depending on the state of RSTSEL, the DAC registers are set to either midscale or zero. Reset Select. Determines the action of RST. If HIGH, a RST command will set the DAC registers to mid-scale. If LOW, a RST command will set the DAC registers to zero. DAC Voltage Output DAC Output Amplifier Inverting Input. Used to close the feedback loop at the load. Negative Power Supply Analog Ground Positive Power Supply DAC Reference High Sense Input DAC Reference High Input DAC Reference Low Sense Input DAC Reference Low Input Digital Ground Positive Power Supply DB0 (R) 5 DAC7641 TYPICAL PERFORMANCE CURVES: VSS = 0V At TA = +25C, VDD = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25C) 3.0 2.0 1.0 0 -1.0 -2.0 -3.0 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code 3.0 2.0 1.0 0 -1.0 -2.0 -3.0 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+85C) LE (LSB) DLE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (-40C) 3.0 2.0 1.0 0 -1.0 -2.0 -3.0 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code 2 DLE (LSB) LE (LSB) ZERO-SCALE ERROR vs TEMPERATURE Code (0040H) 1.5 1 LE (LSB) UPO (mV) 0.5 0 -0.5 -1 -1.5 -2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (C) 90 DLE (LSB) POSITIVE FULL-SCALE ERROR vs TEMPERATURE 2 Code (FFFFH) 0.14 0.12 VREFH CURRENT vs CODE Positive Full-Scale Error (mV) 1.5 VREF Current (mA) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (C) 90 1 0.5 0 -0.5 -1 -1.5 -2 0.10 0.08 0.06 0.04 0.02 0.00 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code (R) DAC7641 6 TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25C, VDD = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. VREFL CURRENT vs CODE 0.00 -0.02 Quiescent Current (mA) VREF Current (mA) 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 POWER SUPPLY CURRENT vs TEMPERATURE Data = FFFFH No Load ICC -0.04 -0.06 -0.08 -0.10 -0.12 -0.14 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C) POSITIVE SUPPLY CURRENT vs DIGITAL INPUT CODE 0.50 0.45 0.40 Output Voltage OUTPUT VOLTAGE vs SETTLING TIME (0V to +2.5V) +5V LDAC 0 Large-Signal Settling Time: 0.5V/div 0.35 ICC (mA) 0.30 0.25 0.20 0.15 0.10 0.05 0.00 ICC Small-Signal Settling Time: 4LSB/div 0000H 0200H 0400H 0800H 1000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Time (2s/div) Digital Input Code OUTPUT VOLTAGE vs SETTLING TIME (+2.5V to 2mV) +5V LDAC 0 Output Voltage (50mV/div) OUTPUT VOLTAGE vs MIDSCALE GLITCH PERFORMANCE +5V LDAC 0 Output Voltage Small-Signal Settling Time: 4LSB/div 7FFFH to 8000H Large-Signal Settling Time: 0.5V/div Time (2s/div) Time (1s/div) (R) 7 DAC7641 TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25C, VDD = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. OUTPUT VOLTAGE vs MIDSCALE GLITCH PERFORMANCE +5V LDAC 0 Output Voltage (50mV/div) Noise Voltage (50V/div) BROADBAND NOISE 8000H to 7FFFH BW = 10kHz Code = 8000H Time (1s/div) Time (10ms/div) OUTPUT NOISE VOLTAGE vs FREQUENCY 1000 Logic Supply Current (mA) 12 10 8 6 4 2 0 LOGIC SUPPLY CURRENT vs LOGIC INPUT LEVEL FOR DATA BITS Noise (nV/Hz) 100 10 10 100 1000 10000 100000 1000000 Frequency (Hz) 0 1 2 3 4 5 Logic Input Level for Data Bits (V) OUTPUT VOLTAGE vs RLOAD 5 4 VOUT (V) 3 Source 2 1 Sink 0.1 1 RLOAD (k) 10 100 0 0.01 (R) DAC7641 8 TYPICAL PERFORMANCE CURVES: VSS = -5V At TA = +25C, VDD = +5V, VSS = -5V, VREFH = +2.5V, VREFL = -2.5V, representative unit, unless otherwise specified. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25C) 3.0 2.0 1.0 0 -1.0 -2.0 -3.0 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code 3.0 2.0 1.0 0 -1.0 -2.0 -3.0 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+85C) LE (LSB) LE (LSB) DLE (LSB) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code DLE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (-40C) 3.0 2.0 1.0 0 -1.0 -2.0 -3.0 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code 0.30 0.25 VREFH CURRENT vs CODE LE (LSB) VREF Current (mA) 0.20 0.15 0.10 0.05 0.00 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code DLE (LSB) VREFL CURRENT vs CODE 0.00 -0.05 Zero-Scale Error (mV) 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 ZERO-SCALE ERROR vs TEMPERATURE (Code 8000H) VREF Current (mA) -0.10 -0.15 -0.20 -0.25 -0.30 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (C) 90 (R) 9 DAC7641 TYPICAL PERFORMANCE CURVES: VSS = -5V POSITIVE FULL-SCALE ERROR vs TEMPERATURE (Code FFFFH) 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (C) 90 (Cont.) At TA = +25C, VDD = +5V, VSS = -5V, VREFH = +2.5V, VREFL = -2.5V, representative unit, unless otherwise specified. NEGATIVE FULL-SCALE ERROR vs TEMPERATURE (Code 0000H) 2 Negative Full-Scale Error (mV) Positive Full-Scale Error (mV) 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (C) 90 POWER SUPPLY CURRENT vs TEMPERATURE 1.0 0.8 Quiescent Current (mA) OUTPUT VOLTAGE vs RLOAD 5 4 Data = FFFFH No Load ICC VOUT (V) 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 -30 -20 -10 0 ISS 3 2 1 0 -1 -2 -3 -4 Source Sink 10 20 30 40 50 60 70 80 90 Temperature (C) -5 0.01 0.1 1 RLOAD (k) 10 100 POSITIVE SUPPLY CURRENT vs DIGITAL INPUT CODE 0.50 0.45 0.40 0.35 ICC OUTPUT VOLTAGE vs SETTLING TIME (-2.5V to +2.5V) Large-Signal Settling Time: 1V/div +5V LDAC 0 Output Voltage ICC (mA) 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0000H 0200H 0400H 0800H 1000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Small-Signal Settling Time: 2LSB/div Time (2s/div) Digital Input Code (R) DAC7641 10 TYPICAL PERFORMANCE CURVES: VSS = -5V (Cont.) At TA = +25C, VDD = +5V, VSS = -5V, VREFH = +2.5V, VREFL = -2.5V, representative unit, unless otherwise specified. OUTPUT VOLTAGE vs SETTLING TIME (+2.5V to -2.5V) +5V LDAC 0 Output Voltage Small-Signal Settling Time: 2LSB/div Large-Signal Settling Time: 1V/div Time (2s/div) THEORY OF OPERATION The DAC7641 is a voltage output, 16-bit digital-to-analog converter (DAC). The architecture is an R-2R ladder configuration with the three MSBs segmented, followed by an operational amplifier that serves as a buffer (see Figure 1). The minimum voltage output (zero-scale) and maximum voltage output (full-scale) are set by the external voltage references VREFL and VREFH, respectively. The digital input is a 16-bit parallel word and the DAC input register offers a readback capability. The converters can be powered from either a single +5V supply or a dual 5V supply. The device offers a reset function which immediately sets all DAC output voltages and DAC registers to mid-scale code 8000H or to zero-scale code 0000H. See Figures 2 and 3 for the basic operation of the DAC7641. RF VOUT Sense R VOUT 2R 2R 2R 2R 2R 2R 2R 2R 2R VREFH VREFH Sense VREFL VREFL Sense FIGURE 1. DAC7641 Architecture. (R) 11 DAC7641 +5V 1F + 0.1F 0V +2.5000V AGND DGND 32 VDD 31 30 29 28 27 26 VCC 25 VREFL DGND VREFL Sense VREFH VREFH Sense AGND VSS VOUT Sense VOUT 24 23 22 21 20 19 18 17 0V to +2.5V DAC RESET MODE SELECT DAC RESET DAC LOAD STROBE READ/WRITE STROBE CHIP SELECT 1 2 3 4 5 6 7 8 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DAC7641 RSTSEL RST LDAC R/W CS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 9 10 11 12 13 14 15 16 FIGURE 2. Single-Supply Operation. +5V 1F + 0.1F -2.500V +2.500V -5V DGND 32 VDD DGND 1 2 3 4 5 6 7 8 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DAC7641 31 30 29 28 27 26 VCC VREFH Sense AGND VSS VOUT Sense VOUT RSTSEL RST LDAC R/W CS 24 23 22 21 20 19 18 17 -2.5V to +2.5V DAC RESET MODE SELECT DAC RESET DAC LOAD STROBE READ/WRITE STROBE CHIP SELECT 25 AGND 1F + 0.1F VREFL VREFL Sense VREFH DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 9 10 11 12 13 14 15 16 FIGURE 3. Dual-Supply Operation. (R) DAC7641 12 VREFH Sense 27 ANALOG OUTPUTS When VSS = -5V (dual supply operation), the output amplifier can swing to within 2.25V of the supply rails, guaranteed over the -40C to +85C temperature range. With VSS = 0V (single-supply operation), and with RLOAD also connected to ground, the output can swing to ground. Care must be taken when measuring the zero-scale error with VSS = 0V. Since the output voltage cannot swing below ground, the output voltage may not change for the first few digital input codes (0000H, 0001H, 0002H, etc.) if the output amplifier has a negative offset. At the negative limit of -2mV, the first specified output starts at code 0040H. Due to the high accuracy of these D/A converters, system design problems such as grounding and contact resistance become very important. A 16-bit converter with a 2.5V fullscale range has a 1LSB value of 38V. With a load current of 1mA, series wiring and connector resistance (see Figure 4) of only 40m (RW2) will cause a voltage drop of 40V. To understand what this means in terms of a system layout, the resistivity of a typical 1 ounce copper-clad printed circuit board is 1/2 m per square. For a 1mA load, a 10 milli-inch wide printed circuit conductor 600 milli-inches long will result in a voltage drop of 30V. The DAC7641 offers a force and sense output configuration for the high open-loop gain output amplifier. This feature allows the loop around the output amplifier to be closed at the load (see Figure 4), thus ensuring an accurate output voltage. REFERENCE INPUTS The reference inputs, VREFL and VREFH, can be any voltage between VSS + 2.5V and VCC - 2.5V provided that VREFH is at least 1.25V greater than VREFL. The minimum output of each DAC is equal to VREFL plus a small offset voltage (essentially, the offset of the output op amp). The maximum output is equal to VREFH plus a similar offset voltage. Note that VSS (the negative power supply) must either be +V +2.5V VREFL 30 VREFL Sense 29 VREFH 28 26 VCC 25 24 VSS AGND RW1 VOUT Sense 23 VOUT 22 RW2 VOUT DAC7641 FIGURE 4. Analog Output Closed-Loop Configuration. RW represents wiring resistances. connected to ground or must be in the range of -4.75V to -5.25V. The voltage on VSS sets several bias points within the converter. If VSS is not in one of these two configurations, the bias values may be in error and proper operation of the device is not guaranteed. The current into the VREFH input and out of VREFL depends on the DAC output voltages and can vary from a few microamps to approximately 0.5mA. The reference input appears as a varying load to the reference. If the reference can sink or source the required current, a reference buffer is not required. The DAC7641 features a reference drive and sense connection such that the internal errors caused by the changing reference current and the circuit impedances can be minimized. Figures 5 through 13 show different reference configurations and the effect on the linearity and differential linearity. OPA2234 -2.5V 500pF 500pF VCC -V AGND +V VREFL 30 VREFL Sense 29 VREFH 28 VREFH Sense 27 26 25 +2.5V 24 VSS VOUT Sense 23 VOUT 22 VOUT DAC7641 FIGURE 5. Dual Supply Configuration-Buffered References, used for Dual Supply Performance Curves. (R) 13 DAC7641 OPA2350 2200pF 0.05V 1000pF 100 98k 2200pF 1000pF +2.5V 2k +V 100 VREFL 30 VREFL Sense 29 VREFH 28 VREFH Sense 27 26 25 24 VSS VOUT Sense 23 VOUT 22 VOUT DAC7641 NOTE: VREFL has been chosen to be 50mV to allow for current sinking voltage drops across the 100 resistor and the output stage of the buffer op amp. FIGURE 6. Single-Supply Buffered Reference with a Reference Low of 50mV. AGND VCC LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25C) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25C) LE (LSB) LE (LSB) DLE (LSB) 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code DLE (LSB) FIGURE 7. Integral Linearity and Differential Linearity Error Curves for Figure 6. FIGURE 8. Integral Linearity and Differential Linearity Error Curves for Figure 9. (R) DAC7641 14 OPA2350 2200pF +V 100 +1.25V 100 1000pF 2200pF +2.5V 1000pF VCC AGND +V VREFL 30 VREFL Sense 29 VREFH 28 VREFH Sense 27 26 25 24 VSS VOUT Sense 23 VOUT 22 VOUT DAC7641 FIGURE 9. Single-Supply Buffered Reference with VREFL = +1.25V and VREFH = +2.5V. +V LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25C) 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code 100 OPA350 1000pF 2200pF +2.5V VREFL 30 VREFL Sense 29 VREFH 28 VREFH Sense 27 26 25 AGND VCC VOUT Sense 23 VOUT 22 VOUT DAC7641 FIGURE 10. Single-Supply Buffered VREFH. FIGURE 11. Linearity and Differential Linearity Error Curves for Figure 10. DLE (LSB) 24 VSS LE (LSB) (R) 15 DAC7641 +V LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25C) +2.5V VREFL 30 VREFL Sense 29 VREFH 28 VREFH Sense 27 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code 26 25 24 VSS VOUT Sense 23 VOUT 22 VOUT DAC7641 FIGURE 12. Low Cost Single-Supply Configuration. FIGURE 13. Linearity and Differential Linearity Error Curves for Figure 12. DIGITAL TIMING Figure 14 and Table II provide detailed timing for the digital interface of the DAC7641. DIGITAL INPUT CODING The DAC7641 input data is in Straight Binary format. The output voltage is given by Equation 1. VOUT = VREF L + DIGITAL INTERFACE Table I shows the basic control logic for the DAC7641. Note that the internal register is edge triggered and not level triggered. When the LDAC signal is transitioned to HIGH, the digital word currently in the register is latched. The double-buffered architecture is designed so that the DAC input register can be written to at any time. DLE (LSB) LE (LSB) AGND VCC (VREF H - VREF L) * N 65, 536 (1) R/W L H X X X X CS L L H H X X RST RSTSEL LDAC REGISTER H H H H X X X X L H X X H X X Write Read Hold Hold REGISTER INPUT MODE Hold Write Input Hold Read Input Write Update Hold Hold Reset to Zero Reset to Zero Reset to Midscale Reset to Midscale where N is the digital input code. This equation does not include the effects of offset (zero-scale) or gain (full-scale) errors. TABLE I. DAC7641 Logic Truth Table. (R) DAC7641 16 tWCS tRCS CS tRDS R/W tDZ Data Out Data Valid tCSD Data In tS VOUT LDAC tDS tDH tRDH R/W tLS tLWD tLX tLH 0.003% of FSR Error Band CS tWS tWH Data Read Timing Data Write Timing tSS RSTSEL tRSH tRSS RST tSH 0.003% of FSR Error Band +FS VOUT, RSTSEL LOW -FS +FS VOUT, RSTSEL HIGH -FS MS DAC7641 Reset Timing FIGURE 14. Digital Input and Output Timing. SYMBOL tRCS tRDS tRDH tDZ tCSD tWCS tWS tWH tLS tLH tLX tDS tDH tLWD tSS tSH tRSS tRSH tS DESCRIPTION CS LOW for Read R/W HIGH to CS LOW R/W HIGH after CS HIGH CS HIGH to Data Bus in High Impedance CS LOW to Data Bus Valid CS LOW for Write R/W LOW to CS LOW R/W LOW after CS HIGH CS LOW to LDAC HIGH CS LOW after LDAC HIGH LDAC HIGH Data Valid to CS LOW Data Valid after CS HIGH LDAC LOW RSTSEL Valid Before RESET HIGH RSTSEL Valid After RESET HIGH RESET LOW Before RESET HIGH RESET LOW After RESET HIGH Settling Time MIN 150 10 10 10 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s 100 40 0 10 30 100 100 0 10 100 0 200 10 10 100 150 10 TABLE II. Timing Specifications (TA = -40C to +85C). (R) 17 DAC7641 DIGITALLY-PROGRAMMABLE CURRENT SOURCE The DAC7641 offers a unique set of features that allows a wide range of flexibility in designing applications circuits such as programmable current sources. The DAC7641 offers both a differential reference input as well as an open-loop configuration around the output amplifier. The open-loop configuration around the output amplifier allows transistor to be placed within the loop to implement a digitallyprogrammable, uni-directional current source. The availability of a differential reference also allows programmability for both the full-scale and zero-scale currents. The output current is calculated as: V H - VREF L N Value I OUT = REF * R SENSE 65, 536 + (VREF L / R SENSE ) Figure 15 shows a DAC7641 in a 4mA to 20mA current output configuration. The output current can be determined by Equation 3: (3) 2.5V - 0.5V N Value 0.5V * I OUT = + 125 65, 536 125 At full-scale, the output current is 16mA plus the 4mA for the zero current. At zero scale the output current is the offset current of 4mA (0.5V/125). (2) OPA2350 2200pF +0.50v 1000pF 80k 100 2200pF +2.5V 1000pF AGND +V 20k 100 VREFL 30 VREFL Sense 29 VREFH 28 VREFH Sense 27 26 VCC 25 24 VSS VOUT Sense 23 VOUT 22 IOUT DAC7641 VPROGRAMMED RSENSE 125 FIGURE 15. 4-to-20mA Digitally Controlled Current Source. (R) DAC7641 18 PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2003 PACKAGING INFORMATION ORDERABLE DEVICE DAC7641Y/250 DAC7641Y/2K DAC7641YB/250 DAC7641YB/2K STATUS(1) ACTIVE ACTIVE ACTIVE ACTIVE PACKAGE TYPE TQFP TQFP TQFP TQFP PACKAGE DRAWING PBS PBS PBS PBS PINS 32 32 32 32 PACKAGE QTY 250 2000 250 2000 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. 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