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ADS7833
10-Channel, 12-Bit DATA ACQUISITION SYSTEM
FEATURES
q 3 SIMULTANEOUS SAMPLED CHANNELS q 3 SYNCHRONIZED 12-BIT ADCs q 6.6s THROUGHPUT RATE q FULLY DIFFERENTIAL MUX INPUTS q DIGITALLY SELECTABLE INPUT RANGES q 5V POWER SUPPLIES q SERIAL DIGITAL INPUT/OUTPUTS q 2 SIMULTANEOUS SAMPLED AUXILIARY CHANNELS q DIRECT INTERFACE TO MOTOROLA'S DSP56004/7
APPLICATIONS
q AC MOTOR SPEED CONTROLS q THREE PHASE POWER CONTROL q UNINTERRUPTABLE POWER SUPPLIES q VIBRATION ANALYSIS q PC DATA ACQUISITION q MEDICAL INSTRUMENTATION
2 V1-1 2 V1-2 2 V1-3 2 V2-1 2 V2-2 2 V2-3 2 V3-1 V3-2 V3-3 V3-4 2 2 2 MUX3 Input Select Gain Select Serial IN SH3 PGA3 ADC3 12-Bit Serial Out3 MUX2 SH2 PGA2 ADC2 12-Bit Serial Out2 MUX1 SH1 PGA1 ADC1 12-Bit Serial Out1
DESCRIPTION
The ADS7833 consists of three 12-bit analog-to-digital converters preceded by three simultaneously operating sample-hold amplifiers, and multiplexers for 10 differential inputs. The ADCs have simultaneous serial outputs for high speed data transfer and data processing. The ADS7833 also offers a programmable gain amplifier with programmable gains of 1.0V/V, 1.25V/V, 2.5V/V, and 5.0V/V. Channel selection and gain selection are selectable through the serial input control word. The high through put rate is maintained by simultaneously clocking in the 13-bit input control word for the next conversion while the present conversions are clocked out. The part also contains an 8-bit digital-to-analog converter whose digital input is supplied as part of the input control word.
2.5V Ref
Control Logic
Input Setup Register
DAC CAP
DAC 8-Bit
Voltage Out Clock Convert Busy
International Airport Industrial Park * Mailing Address: PO Box 11400, Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 * Tel: (520) 746-1111 * Twx: 910-952-1111 Internet: http://www.burr-brown.com/ * FAXLine: (800) 548-6133 (US/Canada Only) * Cable: BBRCORP * Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132
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1994 Burr-Brown Corporation
PDS-1235C
1
ADS7833
Printed in U.S.A. May, 1997
SPECIFICATIONS
At VANA+ = +5V, VANA- = -5V, VDIG+ = +5V, VDIG- = -5V, and TA = -40C to +85C, using internal reference, fCLOCK = 2.1MHz.
ANALOG-TO-DIGITAL CONVERTER CHANNELS
ADS7833N PARAMETER RESOLUTION ANALOG INPUT Full Scale Voltage, Differential CONDITIONS MIN 12 2.5 2.0 1.0 0.5 See Table VII 1012 20 6.1 6.6 150 200 0.1 0.5 50 50 3 0.5 0.5 12 0.5 0.5 G = 1.0V/V G G G G G = = = = = 1.0V/V 2.5V/V 1.0V/V 1.0V/V 1.0V/V 10 10 0.5 0.5 0.5 3 3 2 4 100 100 15 20 2 TYP MAX UNITS Bit
G = 1.0V/V G = 1.25V/V G = 2.5V/V G = 5.0V/V 0.5
Common-Mode Voltage Impedance Capacitance THROUGHPUT SPEED Conversion Time Complete Cycle Throughput Rate SAMPLING DYNAMICS S/H Droop Rate S/H Acquisition Time S/H Aperture Delay S/H Aperture Jitter Sampling Skew, Channel-to-Channel DC ACCURACY Integral Linearity - ADC Differential Linearity - ADC No Missing Codes Integral Linearity - Asynchronous, Synchronous Differential Linearity - Asynchronous, Synchronous Full Scale Error Full Scale Error Other Gains Full Scale Error Drift Zero Error - ADC Zero Error - Asynchronous, Synchronous Zero Error Drift AC ACCURACY Total Harmonic Distortion fIN = 1kHz fIN = 1MHz CMR REFERENCE Internal Reference Voltage Internal Reference Accuracy Internal Reference Drift Internal Reference Source Current External Reference Voltage Range for Specified Linearity External Reference Current Drain DIGITAL INPUTS Logic Levels VIL VIH IIL IIH Input Capacitance DIGITAL OUTPUTS Data Format Data Coding VOL VOH Leakage Current Output Capacitance CLK = 2.1MHz Acquire and Convert
V V V V V pF s s kHz V/s s ns ps ns LSB LSB Bits LSB LSB % of FSR % of FSR ppm/C ppm/C LSB LSB ppm/C
VCM = 1V, fCM = 1MHz
92 72 40 2.5 0.25 10 10 2.5 10
dB dB dB V % ppm/C A V A
2.25
2.75
0 +3.5
At All Digital Input Pins 12-Bit Serial BTC ISINK = 1.6mA ISOURCE = 500A At All Digital Output Pins 0 4.2
1.5 +5 10 10 15
V V A A pF
0.4 5 5 15
V V A pF
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
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ADS7833
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SPECIFICATIONS
(CONT)
At VANA+ = +5V, VANA- = -5V, VDIG+ = +5V, VDIG- = -5V, and TA = -40C to +85C, using internal reference, fCLOCK = 2.1MHz.
ANALOG-TO-DIGITAL CONVERTER CHANNELS
ADS7833N PARAMETER POWER SUPPLIES VANA+ VANA- VDIG+ VDIG- IANA+ IANA- IDIG+ IDIG- Power Dissipation TEMPERATURE RANGE Specified Performance Derated Performance Storage CONDITIONS Specified Performance +4.75 -4.75 +4.75 -4.75 +5.0 -5.0 +5.0 -5.0 15 8 3 1 125 +5.25 -5.25 +5.25 -5.25 25 10 5 2 V V V V mA mA mA mA mW C C C MIN TYP MAX UNITS
-40 -55 -65
+85 +125 +150
DIGITAL-TO-ANALOG CONVERTER
ADS7833N PARAMETER RESOLUTION Output Range Output Settling Time Linearity Error Differential Linearity Output Current Offset Error Full Scale Error CONDITIONS MIN 8-Bits 0 To 0.5LSB TYP MAX +2.5 1 1 1 1 10 2 UNITS V s LSB LSB A mV %
200
ABSOLUTE MAXIMUM RATINGS
Analog Input Voltage ............................................... .......................... 25V Ground Voltage Difference: AGND and DGND ................................. 0.3V Power Supply Voltages: VANA+ ................................................................................................. +7V VANA- ................................................................................................. -7V VDIG+ ................................................................................................. +7V VDIG- ................................................................................................. -7V Digital Inputs .............................................................. -0.3V to VDIG +0.3V Maximum Junction Temperature ................................................... +165C Internal Power Dissipation ............................................................. 825mW Lead Temperature (soldering, 10s) ............................................... +300C
PIN CONFIGURATION
REFGND AGND REFIN VANA+
V3-1N
V3-2N
V3-3N
V3-4N
V3-1P
VANA-
V3-2P
V3-3P
V3-4P
AOUT
CAP
NC
9 NC 10 V2-1N 11 V2-1P 12 NC 13 V2-2N 14 V2-2P 15 NC 16 V2-3N 17 V2-3P 18
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61 60 NC 59 V1-1N 58 V1-1P 57 NC 56 V1-2N 55 V1-2P 54 NC 53 V1-3N
CONVERSION AND DATA TIMING
SYMBOL tCONV CLK t1 t2 t3 t4 t5 DESCRIPTION A/D Conversion Time A/D Conversion Clock Setup Time for Conversion Before Rising Edge of Clock Hold Time for Conversion After Rising Edge of Clock Setup Time for Serial Out Setup Time for Serial Input Hold Time for Serial Input 30 30 MIN TYP MAX UNITS 6.6 2.1 50 50 25 4.0 2.8 s MHz ns ns ns ns ns
NC
ADS7833N
52 V1-3P 51 NC 50 NC 49 NC 48 NC 47 NC 46 NC 45 NC 44 NC
NC 19 NC 20 NC 21 NC 22 NC 23 NC 24 NC 25 NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
SOUT2
SOUT3
DGND
SOUT1
VDIG+
VDIG-
NC
ASH
SERIN
NC
CLK
CONV
BUSY
PACKAGE INFORMATION
PRODUCT ADS7833N PACKAGE 68-Lead PLCC PACKAGE DRAWING NUMBER(1) 312
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
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ADS7833
DCLOCK
TP1
TP2
NC
PIN DEFINITIONS
PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 NAME V3-4N V3-4P V3-3N V3-3P V3-2N V3-2P NC V3-1N V3-1P NC V2-1N V2-1P NC V2-2N V2-2P NC V2-3N V2-3P NC NC NC NC NC NC NC NC TP1 TP2 VDIG+ DGND VDIG- NC SOUT2 SOUT3 TYPE(1) AI AI AI AI AI AI -- AI AI -- AI AI -- AI AI -- AI AI -- -- -- -- -- -- -- -- -- -- P P P -- DO DO DESCRIPTION Voltage Input, Channel 3, Mux I/P 4, Negative Side Voltage Input, Channel 3, Mux IP 4, Positive Side Voltage Input, Channel 3, Mux I/P 3, Negative Side Voltage Input, Channel 3, Mux I/P 3, Positive Side Voltage Input, Channel 3, Mux I/P 2, Negative Side Voltage Input, Channel 3, Mux I/P 2, Positive Side No Connection Voltage Input, Channel 3, Mux I/P 1, Negative Side Voltage Input, Channel 3, Mux I/P 1, Positive Side No Connection Voltage Input, Channel 2, Mux I/P 1, Negative Side Voltage Input, Channel 2, Mux I/P 1, Positive Side No Connection Voltage Input, Channel 2, Mux I/P 2, Negative Side Voltage Input, Channel 2, Mux I/P 2, Positive Side No Connection Voltage Input, Channel 2, Mux I/P 3, Negative Side. Voltage Input, Channel 2, Mux I/P 3, Positive Side No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection Test Point 1, Make No Connection Test Point 2, Make No Connection Digital Supply Voltage, +5V Digital Supply Voltage, Ground Digital Supply Voltage, -5V No Connection Serial Digital Output, Channel 2 Serial Digital Output, Channel 3 PIN NO 35 36 37 NAME SOUT1 CLK CONV TYPE(1) DO DI DI DESCRIPTION Serial Digital Output, Channel 1 Clock for A/D Converters Start A/D Converters. When CONV goes to "0" (low) the next rising edge of CLK starts the conversion. Digital Control for Asynchronous Sample Hold. If signal is "1" (high), signals are sampled. Serial Digital Input for Input Control Word A/D Converters Busy. Busy if signal is "0" (low). A Delayed and Truncated Version of the CLK Signals. It is Delayed 50ns from the CLK Signal and Stays Low after 13 DCLOCK Cycles. No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection Voltage Input, Channel 1, Mux I/P 3, Positive Side Voltage Input, Channel 1, Mux I/P 3, Negative Side No Connection Voltage Input, Channel 1, Mux I/P 2, Positive Side Voltage Input, Channel 1, Mux I/P 2, Negative Side No Connection Voltage Input, Channel 1, Mux I/P 1, Positive Side Voltage Input, Channel 1, Mux I/P 1, Negative Side No Connection No Connection Output of DAC Decoupling Point for Internal Reference Input Pin for External Reference Ground Pin for External Reference Analog Supply Voltage, -5V Analog Supply Voltage, Ground Analog Supply Voltage, +5V
38
ASH
DI
39 40 41
SERIN BUSY DCLOCK
DI DO DO
42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
NC NC NC NC NC NC NC NC NC NC V1-3P V1-3N NC V1-2P V1-2N NC V1-1P V1-1N NC NC AOUT CAP REFIN REFGND VANA- AGND VANA+
-- -- -- -- -- -- -- -- -- -- AI AI -- AI AI -- AI AI -- -- AO AO AI P P P P
NOTE: (1) AI is Analog Input, AO is Analog Output, DI is Digital Input, DO is Digital Output, P is Power Supply Connection.
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ADS7833
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TYPICAL PERFORMANCE CURVES
At VANA+ = +5V, VANA- = -5V, VDIG+ = +5V, VDIG- = -5V and TA = 25C, using internal reference, fCLOCK = 2.1MHz.
OFFSET vs TEMPERATURE 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.2 0 -55 -40 -25 0 25 70 85 125 Temperature (C) 0.1 0 -55 -40 0.9 0.8 0.7
FULL SCALE vs TEMPERATURE
Full Scale (%)
Offset (LSB)
0.6 0.5 0.4 0.3
-25
0
25
70
85
125
Temperature (C)
DIFFERENTIAL LINEARITY (MIN) vs TEMPERATURE 0.000 -0.100 -0.200 -0.300 -0.400 -0.500 -0.600 -0.700 -55 -40 -25 0 25 70 85 125 Temperature (C) 0.40 0.35
DIFFERENTIAL LINEARITY (MAX) vs TEMPERATURE
Differential Linearity (LSB)
Differential Linearity (LSB)
0.30 0.25 0.20 0.15 0.10 0.05 0 -55 -40 -25 0 25 70 85 125 Temperature (C)
INTEGRAL LINEARITY (MIN) vs TEMPERATURE 0.000 -0.050 Integral Linearity (LSB) 0.45 0.40
INTEGRAL LINEARITY (MAX) vs TEMPERATURE
-0.150 -0.200 -0.250 -0.300 -0.350 -0.400 -0.450 -55 -40 -25 0 25 70 85 125 Temperature (C)
Integral Linearity (LSB)
-0.100
0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 -55 -40 -25 0 25 70 85 125 Temperature (C)
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ADS7833
TYPICAL PERFORMANCE CURVES (CONT)
At VANA+ = +5V, VANA- = -5V, VDIG+ = +5V, VDIG- = -5V and TA = 25C, using internal reference, fCLOCK = 2.1MHz.
DAC OFFSET vs TEMPERATURE 3.5 3.0
DAC FULL SCALE vs TEMPERATURE 0 -0.05 -0.10
DAC Full Scale (%)
DAC Offset (mV)
2.5 2.0 1.5 1.0 0.5 0 -55 -40 -25 0 25 70 85 125 Temperature (C)
-0.15 -0.20 -0.25 -0.30 -0.35 -0.40 -0.45 -55 -40 -25 0 25 70 85 125 Temperature (C)
BASIC CIRCUIT CONFIGURATION
+5V GND -5V GND
4.7F
4.7F
2.2F
100nF
100nF
2.2F
REFGND
V3-1N
V3-1N
V3-3N
V3-4N
REFOUT
AGND
V3-1P
VANA-
REFIN
VANA+
V3-2P
V3-3P
V3-4P
AOUT
NC
9 NC 10 V2-1N 11 V2-1P 12 NC 13 V2-2N 14 V2-2P 15 NC 16 V2-3N 17
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61 60 NC 59 V1-1N 58 V1-1P 57 NC 56 V1-2N 55 V1-2P 54 NC 53 V1-1N IN- IN+
V2-3P 18 NC 19 NC 20 NC 21 NC 22 NC 23 NC 24 NC 25 NC 26
NC
52 V1-1N 51 NC 50 NC 49 NC 48 NC 47 NC 46 NC 45 NC 44 NC
ADS7833N
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DGND
NC
CLK
CONV
VDIG-
ASH
SERIN
BUS
DCLOCK
NC
VDIG+
SOUT2
SOUT3
4.7F
4.7F + 100nF
100nF
SOUT1
TP1
TP2
NC
Ground Plane
+5V
GND
-5V
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ADS7833
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FUNCTIONAL DESCRIPTION
(See Figure 1) ADCs AND PGAs The ADS7833 contains three signal channels each with a 12-bit analog-to-digital converter output. The ADCs operate synchronously and their serial outputs occur simultaneously. (Table VI gives the analog input/digital output relationships). The ADCs are preceded by programmable gain amplifiers. (Table II gives gain select information). For channels one and two, the PGAs are effective for all three analog inputs. For the third channel, only the V3-1 input is gain changed by the PGA. Inputs V3-2, V3-3, and V3-4 are connected to ADC3 at a fixed gain of 1V/V regardless of the Gain Select value.
V1-1 V1-2 V1-3
2 2 2
2
SH1 2 2 2
2
SH2
2
PGA1
2
ADC1
SOUT1
SH6
2
Ref Conv
ASH V2-1 V2-2 V2-3 2 2 2 2 SH3 2 2 2
2
SH4
2
PGA2
2 ADC2
SOUT2
SH7
2
Ref Conv
ASH V3-1 V3-2 V3-3 V3-4 2 2 2 2 Ref CAP REFIN 2.5V Ref Conv Sample 2 SH5
V3-2 Through V3-4
2
PGA3
2 V3-1 Only
ADC3
SOUT3
Input Gain Select Select Decoder 3 2 Input Setup Register DAC Input 8
Ref Conv
SERIN
Control Logic
DAC 8-Bit
AOUT ASH CLK CONV BUSY DCLOCK
FIGURE 1. Functional Diagram. SAMPLE HOLDS The ADS7833 contains seven sample holds. Five of them (SH1 through SH5) sample simultaneously and have their sample/hold timing internally synchronized. (The timing is shown in Figure 2). Three of the sample holds (SH1, SH3, and SH5) are connected to the input multiplexers so that they can provide simultaneous sampling for all of their channels inputs. In addition, SH2 and SH4 simultaneously sample the third input of their channels (Vl-3 and V2-3, respectively). This is useful in motor control applications where V1-2 and Vl-3 are the quadrature inputs for one position sensor, and V2-2 and V2-3 are the quadrature inputs for a second position sensor (see Figure 6). In that application, it is desirable to sample
the quadrature inputs of a given position sensor at the same time (even though they are converted on successive conversion cycles) (see Table III), so that their values are captured at the same shaft position. The ADS7833 also has the capability for limited asynchronous sampling. The sampling of SH6 and SH7 is controlled asynchronously by the control signal ASH (see Table III). This allows two inputs each on channel 1 and channel 2 (see Table IV) to be sampled asynchronously from the timing of the other sample holds. This can be useful in motor control applications where the two inputs for each channel come from a position sensor and it is desired to sample based on position sensor timing rather than system clock timing.
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ADS7833
MULTIPLEXERS The ADS7833 also contains several multiplexers that are used to select the desired analog inputs and connect the proper sample hold outputs to the PGAs and ADCs. The MUXs are driven by a decoder which receives its inputs from the Input Setup Register. (See Table III and Table IV for information on input channel selection). The input multiplexers can take full differential input signals (see Figure 3 and Table VII). The analog signals stay differential through the sample holds and the PGAs all the way to the inputs of the ADSs. This is done to provide the best possible high frequency noise rejection. INPUT SETUP As the ADCs are converting and transmitted their serial digital data for one conversion cycle, a setup word is being received to be used for the next conversion cycle. The 13-bit word is supplied at the SERIN pin (see Figure 1), and is stored in the buffered Input Setup Register. The Input Select and Gain Select portions of the word are decoded and determine the state of the multiplexers and PGAs (see CONFIGURABLE PARAMETERS section). DIGITAL-TO-ANALOG CONVERTER An 8-bit DAC provides 256 output voltage levels from 0V to 2.5V (see Table V for input/output relationships). The DAC is controlled by the DAC Input portion of the input setup word. The DAC Input portion of the word is strobed into the DAC at the end of the conversion cycle (14th CLK pulse in Figure 2). VOLTAGE REFERENCE The ADS7833 contains an internal 2.5V voltage reference. It is available externally through an output buffer amplifier. If it is desired to use an external reference, one may be
CLOCK AND CONTROL SIGNALS(1) Clock Pulse Reference No. CLK (Input)(2) DCLOCK (Output) t1 t2 CONV (Input)
connected at the REFIN pins. This then overrides the internal 2.5V reference, is connected to the ADCs and is available buffered at the CAP pin. OTHER DIGITAL INPUTS AND OUTPUTS Sampling and conversion is controlled by the CONV input (see Figure 2). The ADS7833 is designed to operate from an external clock supplied at the CLK input. This allows the conversion to be done synchronously with system timing so that transient noise effects can be minimized. The CLK signal may run continuously or may be supplied only during convert sequences. The BUSY and DCLOCK signals are internally generated and are supplied to make interfaces with microprocessors easier (see Figures 2, 4, and 6). CONFIGURABLE PARAMETERS Configurable parameters are: * PGA Gain * Input multiplexer and sample/hold selection * DAC output voltage Configuration information for these parameters is contained in the SERIN word (See Figure 2). As one conversion is taking place, the configuration for the next conversion is being loaded into the buffered Input Setup Register via the SERIN word. Table I shows information regarding these parameters.
CLOCK POSITIONS(1) 2-9 10-11 12-14
DESCRIPTION DAC Input0-7 Gain Select0-1 Input Select0-2
FUNCTIONS Sets DAC Output Voltage Sets PGA Gains Determines Multiplexers Conditions
NOTE: (1) See Figure 2. "Clock Pulse Reference No."
TABLE I. Description of Configurable Parameters.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
SAMPLE (Internal) BUSY (Output) A-to-D CONVERTER OUTPUTS SERIAL OUT1 SERIAL OUT2 SERIAL OUT3 CONTROL WORD INPUT SERIN t4 t5 Bit 1 6 Bit 2 5 Bit 3 4 Bit 4 3 Bit 5 2 Bit 6 1 Bit 7 0 Bit 8 1 Bit 9 Bit 10 Bit 11 Bit 12 0 2 1 Input Select 0-2 0 t3 Bit 0 MSB Bit 0 MSB Bit 0 MSB Bit 1 Bit 1 Bit 1 Bit 2 Bit 2 Bit 2 Bit 3 Bit 3 Bit 3 Bit 4 Bit 4 Bit 4 Bit 5 Bit 5 Bit 5 Bit 6 Bit 6 Bit 6 Bit 7 Bit 7 Bit 7 Bit 8 Bit 8 Bit 8 Bit 9 Bit 10 Bit 11 LSB Bit 9 Bit 10 Bit 11 LSB Bit 9 Bit 10 Bit 11 LSB tCONV
Bit 0 7
How Used
DAC Input 0-7
Gain Select 0-1
NOTE: (1) See the specification table for timing specifications. (2) 50% duty cycle.
FIGURE 2. Timing Diagram.
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ADS7833
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PGA GAIN The PGA gain is determined by the Gain Select portion (bits 8 and 9) in the SERIN word (see Figure 2). There is one gain input that sets the same gain for all three PGAs. The gain values and allowable full scale inputs are shown in Table II. For channels one and two the PGAs set the gain for all three analog inputs. For the third channel, only the V3-1 input is gain changed by the PGA. Inputs V3-2, V3-3 and V3-4 are connected to ADC3 at a fixed gain of 1V/V regardless of the Gain Select value.
GAIN SELECT0-1 0H 1H 2H 3H GAIN SETTING 5.0V/V 2.5V/V 1.25V/V 1.0V/V FULL SCALE INPUT 0.5V 1.0V 2.0V 2.5V
Input Select = 3H--Convert V1-3 via SH2, V2-3 via SH4, and V3-3 (V1-3 and V2-3 are from the value sampled in a preceding conversion cycle with Input Select = 4H, 5H or 6H). Input Select = 2H--Convert V1-3 via SH1, V2-3 via SH3, and V3-3 (V1-3 is sampled on SH2 in this conversion cycle). Input Select = 1H--Input V3-4 is converted by PGA3/ ADC3. The output of the asynchronous sample holds, SH6 and SH7, are converted by PGA1/ADC1 and PGA2/ADC2, respectively. Note that the inputs to SH6 and SH7 are determined by previous Input Select values (see Table IV). Thus, to properly convert the output of one of the asynchronous sample holds it is first necessary to choose its input with a previous conversion cycle. Also, the output of SH6 or SH7 will only be converted if ASH goes low before the CONV command is received. Input Select = 0H--V3-4 is converted by PGA3/ADC3. The inputs to PGA1/ADC1 and PGA2/ADC2 are undefined. CONVERSIONS FROM THE ASYNCHRONOUS SAMPLE HOLDS Decoding the Input Select value also determines which inputs are applied to the two asynchronously controlled sample holds SH6 and SH7. (See Table IV.) One of the three possible inputs is selected by the Input Select value being 4, 5, or 6. The "No Effect" states indicate that these values of Input Select have no effect on the multiplexers at the input of SH6 and SH7. When one of the "No Effect" values of Input Select is presented, the multiplexers will not be changed (i.e., their condition is determined by the last 4, 5, or 6 value of Input Select that existed prior to the "No Effect" state). Note that Input Select = 1H presents the output of SH6 and SH7 (1ASHX and 2ASHX) to PGA1/ADCl and PGA2/ADC2, respectively (see Table III). Therefore, in order to properly convert the asynchronous sampled signals, it is first necessary to choose an input signal (Input Select equal 5 or 6 in Table IV) with one load/convert cycle and then convert the sample hold output (Input Select = 4 in Table III) in a following conversion cycle.
INPUT SELECT0-2
TABLE II. Gain Select Information. INPUT MULTIPLEXER AND SAMPLE HOLD SELECTION The Input Select portion of the SERIN word (bits 10, 11 and 12) (see Figure 2) are decoded and determine the open/closed condition of the multiplexer switches. This in turn determines which input signals are connected to the sample holds and which sample holds are connected to the PGAs/ADCs. INPUT SIGNALS FOR PGAs/ADCs Table III shows the relationships between the value of Input Select0-2 and the signals that are converted.
INPUT SELECT0-2 HEX CODE 0H 1H 2H 3H 4H 5H 6H 7H BINARY CODE 000 001 010 011 100 101 110 111 ANALOG SIGNAL CONNECTED TO PGAX/ADCX PGA1/ADC1 Undefined V1-X via SH6(1) V1-3 via SH1 V1-3 via SH2 V1-2 V1-2 V1-2 V1-1 PGA2/ADC2 Undefined V2-X via SH7(1) V2-3 via SH3 V2-3 via SH4 V2-2 V2-2 V2-2 V2-1 PGA3/ADC2 V3-4 V3-4 V3-3 V3-3 V3-2 V3-2 V3-2 V3-1
NOTE: (1) See Table IV for Operation.
TABLE III. Input Controls for Synchronous Sample Holds. Input Select = 7H--Synchronously sample and convert input signals V1-1, V2-1, and V3-1. Input Select = 4H, 5H, 6H--Synchronously sample and convert input signals V1-2, V2-2, and V3-2. These codes also cause SH2 and SH4 to sample their inputs. Values 4H, 5H, 6H have different effects on the inputs to SH6 and SH7 (see Table IV).
HEX CODE 0H 1H 2H 3H 4H 5H 6H 7H
BINARY CODE 000 001 010 011 100 101 110 111
ANALOG SIGNAL CONNECTED TO SH6 No Effect No Effect No Effect No Effect Open V1-3 V1-2 No Effect SH7 No Effect No Effect No Effect No Effect Open V2-3 V1-2 No Effect
TABLE IV. Input Controls for Asynchronous Sample Holds.
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ADS7833
DAC OUTPUT VOLTAGE The value of the DAC output voltage is determined by the DAC Input portion of the SERIN word (bits 0 through 7--see Figure 2). The 8-bit DAC has 256 possible output voltages from 0V to +2.49V. The value of 1 LSB is 0.0098V.
ANALOG-TO-DIGITAL CONVERTERS
ARCHITECTURE The ADCs are 12-bit, successive approximation types implemented with a switched capacitor circuitry. SPEED The clock for the ADC conversion is supplied externally at the CLK pin. Maximum clock frequency for specified accuracy is 2.1MHz. This results in a complete conversion cycle (S/H acquisition and A/D conversion) of 6.6s. INPUT/OUTPUT The ADS7833 is designed for bipolar input voltages and uses a binary two's complement digital output code. A programmable gain function is associated with each ADC. This changes the full scale analog input range and the analog resolution of the converter. Details are shown in Table VI. DIFFERENTIAL AND COMMON-MODE INPUT VOLTAGES The ADS7833 is designed with full differential signal paths all the way from the multiplexer inputs through to the input of the ADCs. This was done to provide superior high frequency noise rejection.
DIGITAL INPUT DAC INPUT0-7 HEX CODE 00H 01H
* * *
As is common with most differential input semiconductor devices, there are compound restrictions on the combination of differential and common-mode input voltages. This matter is made slightly more complicated by the fact that most of the analog inputs are capable of being affected by the programmable gain function. The possible differential and single ended configurations are shown in Figures 3a and 3b. The maximum differential and common mode restrictions are shown in Table VII.
GAIN SELECT CODE Gain Full Scale Range (VD with VCM = 0) Largest Positive Common Mode Voltage, VCM+ Largest Negative Common Mode Voltage, VCM- 0 5.0V/V 0.5V 1 2.5V/V 1.0V 2 1.25V/V 2.0V 3 1.0V/V 2.5V
+2.7V
+2.4V
+1.9V
+1.6V
-2.7V
-2.4V
-1.9V
-1.6V
TABLE VII. Differential and Common Mode Voltage Restrictions.
(A) + VD 2 - + VD 2 - V1 - 1N (B) + V1 - 1P VCM + - V1 - 1P
V1 - 1 + VD 2 V1 - 1 - VCM
VD 2
VCM
V1 - 1 VD VCM
ANALOG OUTPUT
VD - + V1 - 1N
BINARY CODE 0000 0000 0000 0001
* * *
0V +0.0098V
* * *
VCM -
FFH
1111 1111
+2.499
TABLE V. DAC Input/Output Relationships.
DESCRIPTION GAIN SELECT CODE GAIN FULL SCALE RANGE +Full Scale (FS -1LSB) One Bit above Mid-Scale Mid-Scale One Bit Below Mid-Scale -Full Scale 0 5V/V 0.5V +0.49976 +0.244mV 0V -0.244V -0.500V 1 2.5V/V 1.0V +0.9995V +0.488mV 0V -0.488mV -1.000V ANALOG INPUT 2
FIGURE 3. (a) Differential Signal Source, and (b) Single Ended Signal Source.
DIGITAL OUTPUT 3 1.0V/V 2.5V +2.499 +1.22mV 0V -1.22mV -2.500V BINARY TWO'S COMPLIMENT FORMAT HEX CODE 7FFH 001H 000H FFFH 800H BINARY CODE 0111 0000 0000 1111 1000 1111 0000 0000 1111 0000 1111 0001 0000 1111 0000
1.25V/V 2.0V +1.999V +0.976mV 0V -0.976mV -2.000V
NOTE: The programmable gain function applies to all three input channels for ADC1 and ADC2. However, the programmable gain function only applies to the first input (V3-1) for ADC3. The other three inputs (V3-2, V3-3, and V3-4) are not affected by the GAIN SEL input. They operate at a fixed gain of 1V/V and thus have a fixed 2.5V full scale input range.
TABLE VI. Analog Input - Digital Output Relationships.
(R)
ADS7833
10
MICROPROCESSOR INTERFACE The internal logic of the ADS7833 is designed for easy control and data interface with microprocessors. Figure 4 shows the interface for loading the input control word from the microprocessor data bus into the serial input of the ADS7833. Table VIII provides a sample assembly code and Figure 4 shows the connection diagram for connecting an ADS7833 to the DSP56004N--or DSP56007 a Motorola Digital Signal Processor. This configuration allows for full control of the ADS7833 as well as receiving all three conversion results simultaneously. The start of conversion is generated by the DSP56004 as well as the sample time of the asynchronous sample/holds.
While this is one of the most useful, the DSP56004/7 is flexible enough to allow various other configurations. These will free up the serial outputs for use with other serial peripherals, such as DACs. TYPICAL ISOLATED ANALOG INPUT Figure 5 shows an ISO130 used to isolate the current measurement in a motor speed control application. This amplifier is well suited for this application because of its high transient immunity (l0kV/s). Its differential output feature is well suited to the differential input of the ADS7833. Keeping the signal transmission differential helps to preserve the high frequency noise rejection of the system. A unique characteristic of the ISO130 is that it has a common mode output voltage of approximately 2.39V. To accept this level of CMV, the ADS7833 must be operated at a gain of 5V/V (0.5V full scale differential input). (See Figure 3 and Table VII). Since the ISO130 has a gain of 8V/V, the maximum value of VSENSE is 62.5mV. Thus, the value of RSENSE is chosen to scale VSENSE to this maximum value. POWER-UP INITIALIZATION When power is applied to the ADS7833, two conversion cycles are required for initialization and valid digital data is transmitted on the third cycle. The first conversion after power is applied is performed with indeterminate configuration values in the double buffer output of the Input Setup Register. The second conversion cycle loads the desired values into the register. The third conversion uses those values to perform proper conversions and output valid digital data from each of the ADCs.
DSP56004/7 SDO0 SDO1 SOI0 SOI1 MOSI/HA0 MISO/NAU SCKT SCKR SCK/SCL WST WSR SS/HA2 SDO2 (optional)
ADS7833 CONV SERIN SOUT1 SOUT2 SOUT3 ASH CLK V2-1 V2-2 V2-3 V3-1 V3-2 V3-3 V3-4 AOUT V1-1 V1-2 V1-3
FIGURE 4. Microprocessor Interface for Motorola DSP56004/7.
movep movep movep ; movep movep movep movep movep movep movep movep ; btst jcs btst jcc movep move movep move move movep
#>$0,x:$ffe4 #>$0,x:$ffe1 #>$0,x:$fff1 #>$dfff00,x:$ffe5 #>$101f00,x:$ffe6 #>$0,x:$ffe7 #>$10d,x:$ffe0 #>$3,x:$ffe1 #>$2001,x:$fff0 #>$5,x:$fff1 #>$f,x:$ffe4 #14,x:$ffe1 data #15,x:$ffe1 wait x:$ffe2,x0 x0,x:$00 x:$ffe3,x0 x0,x:$01 x:$fff3,x0 x0,x:$02
; Disable SAI transmit port ; Disable SAI receive port ; Disable SHI port ; ; ; ; ; Convert command DAC to midscale, G=1V/V, Channel 1 all ADCs For SS pin--enables SHI at proper time Divide by 1 pre, divide by 13--96kHz conv @ 40MHz Enable SAI recv (rsng edge, MSB 1st, 16-bits, slave)
; Set narrow spike filter, CPOL=0, CPHA=1 ; Enable SHI (slave, no fifo, 16-bits) ; Enable SAI trans (rsng edge, MSB 1st, 16-bits, mstr) ; Look for a receive flag (left or right)
wait
data
; ; ; ; ; ;
Get Sout1 Save it Get Sout2 Save it Get Sout3 Save it
TABLE VIII. Sample Code for Motorola DSP56004/7.
(R)
11
ADS7833
HV+
*** +V In 78L05 Out 0.1F 0.1F 2 1 8 7 ISO130 G = 8V/V 0.01F 5 VSENSE ***
+ -
+5V
0.1F
ADS7833 + V1 - 1
V1 - 1P V1 - 1N
6
-
Typical Analog Input
3
4 V1 - 1CMV = 2.5V V1- 1DIFF 500mV
RSENSE *** HV-
VSENSE 62.5mV
FIGURE 5. Typical Isolated Differential Analog Input.
ADS7833 ISO130 CLK CONV Phase A V1 - 1 ASH ISO130 SOUT1 Phase B V2 - 1 SOI0 SCKT SCKR SCK/SCL SDO0 MISO/HAO DSP56004
ISO130
Phase C
V3 - 1 SOUT2 SOI1
V1 - 2 Position Sensor V1 - 3 SOUT3 V2 - 2 Position Sensor V2 - 3 IREF MOSI/HA0
RTD REF 200
V3 - 2
V3 - 3 V3 - 4
SERIN
SDO1
DC Link Voltage
Aux Input ISO122
FIGURE 6. Motor Control Application Using Position Sensors.
(R)
ADS7833
12

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