View CXD2555_236040.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
HI2555, CXD2555
EW ED FOR N C O M ME N D NOT RE DESIGNS
September 1997
1-Bit, AD/DA Converter For Audio Application
Features
* Two-Channel AD/DA Converters and Their Respective Digital Filters for Decimation and Oversampling Into a Single Chip * Peripheral Analog Circuits for AD Converter Greatly Reduces External Elements * Distortion (Typ) - ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.01% - DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.008% (-3dB) * S/N Ratio (Typ) - ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86dB - DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96dB * Ripple in the Digital Filter Pass Band . . . . . . . 0.05dB * Attenuation in the Digital Filter Stop Band . . . . . . . .-45dB
Description
The HI2555, CXD2555 is a 1-bit stereo AD/DA converter featuring a 2nd-order DA system noise shaper. This LSI has also built-in digital filters and provides good cost performance.
Functions
* Data Can Be Input/Output at Rate of 1 x fS with a BuiltIn Digital Filter * Simple Connection of Multiple HI2555, CXD2555s Enable Multi-Channel System * The 32-Slot Serial Data Interface Enables Independent Selection of Data Frontward Packing/Rearward Packing and MSB First/LSB First * The Master Clock is Applicable to Four Sources * 256fS, 512fS, 768fS, and 1024fS * The Sampling Frequency May be Adjusted to Low fS Frequencies Such as 16kHz or 8kHz, in Addition to Normal Ones of 48kHz, 44.1kHz, and 32Hz * Various Frequency Divider Clocks Can Be Output for LSIs Chips Connected
Ordering Information
PART NUMBER HI2555JCQ CXD2555Q TEMP. RANGE ( oC) -20 to 75 -20 to 75 PACKAGE 48 Ld MPQF 48 Ld MPQF PKG. NO. Q48.12x12-S Q48.12x12-S
Pinout
HI2555, CXD2555 (48 LEAD MQFP) TOP VIEW
AOUT1+ AVSS3 WO DASL1 DVDD DASL0 AIN1 AVDD1 AVSS1 SUB
AVDD3 AOUT1AVSS3 UCLK XCLK XVDD XTLI XTLO XVSS AVSS4 AOUT2AVDD4
1 2 3 4 5 6 7 8 9 10
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
NC NC
XSL2 XSL1 XSL0 MLSL MASL DVSS SOUT SIN BCK LRCK MS DVDD
26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24
AVSS4
AVSS2 AIN2
AVDD2
AOUT2+
DVSS XMCK2
SUB NC
TEST
CLR
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 4-301
File Number
4121.1
HI2555, CXD2555 Block Diagram
UCLK 4 XCLK 5 XSL2 XSL1 XSL0 XTL0 XTL1 7
36
35
34
8
CLOCK GENERATOR/ TIMING CIRCUIT 16 MAF1 16 SOUT 30 LRCK 27 BCK 28 SIN 29 16 DAC2 16 RAM 32 MASL 33 MLSL 10 ROM 13 AOUT2(+) S MAF2 ADC2 16 AIN2 2 DAC1 48 AOUT1(+) 11 AOUT2(-) AOUT1(-) ADC1 45 AIN1
P SP
16
DIGITAL FILTER (OVER SAMPLING DECIMATION)
16
Pin Descriptions
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 12 14 15 16 SYMBOL AV DD 3 AOUT1(-) AVSS 3 UCLK XCLK XV DD XTLI XTLO XVSS AVSS 4 AOUT2(-) AV DD 4 AOUT2 (+) AVSS 4 AVSS 2 AIN2 I/O O O O I O O O I DESCRIPTION Analog power supply for Channel-1 DA converter. Analog opposite-phase output of Channel-1 DA converter Analog GND for Channel-1 DA converter. Outputs a 1/2 frequency divider of the clock input form the oscillator pin XTLI (Pin 7). User clock output for externally connected ICs. 256 fS clock output. this provides the master clock for ICs operating in the slave mode when multiple CXD255Qs are connected. (When XSL2 = Low) Digital power supply for the master clock. Crystal oscillator circuit input. Connects the crystal oscillator selected by the crystal selection pins XSLO to 2 (Pins 34, 35, and 36). Used to input the master clock from external. Crystal oscillator circuit output. Connects the crystal oscillator selected by the crystal selection pins XSLO to 2 (Pins 34, 35, and 36). Digital GND for the master clock. Analog GND for Channel-2 DA converter. Analog opposite-phase output for Channel-2 DA converter. Analog power supply for Channel-2 DA converter. Analog in-phase output for Channel-2 DA converter. Analog GND for Channel-2 DA converter. Analog GND for Channel-2 AD converter. Analog input for Channel-2 AD converter.
4-302
HI2555, CXD2555 Pin Descriptions
PIN NO. 17 18 19 20 21 22 23 24 25 26 27 28 (Continued) I/O O I I I I/O I/O Digital GND. IC measurement. Low is output normally. Test pin. Normally fixed to Low. Equipped with a pull-down resistor. System clear input. Normally High; cleared when Low. Equipped with a pull-up resistor. Digital power supply. Master/slave mode switching input. Master mode when High; slave mode when Low. Equipped with a pull-up resistor. Serial I/O sampling frequency clock. Output i master mode (Pin 26 = High); input in slave mode (Pin 26 = Low). Transfers Channel-1 data when high, and Channel-2 data when Low. Serial bit transfer clock (64 fS) for serial input data SIN and serial output data SOUT. Output in master mode (Pin 26 = High); input in slave mode (Pin 26 = Low). Serial input data is retrieved at the rising edge; serial output data is transferred at the falling edge. Two channels per sampling serial data input. Data format is represented by 2's complements, and consists of 32-bit slots. Two channels per sampling serial data input. Data format is represented by 2's complements, and consists of 32-bit slots. Digital GND. Selects whether 16-bit serial data is place din the first 16-bit or the second 16-bit slots of the serial I/O 32-bit slots. Forward packing when High; rearward packing when Low. Selects whether 16-bit serial data is input/output at LSB-first or MSB-first. MSB-first when High; LSB-first when Low. Crystal selection. Selects the clock frequency to be input from XTLI (Pin 7) using three bits, XSL 0 to 2. Crystal selection. Selects the clock frequency to be input from XTLI (Pin 7) using three bits, XSL 0 to 2. Crystal selection. Selects the clock frequency to be input from XTLI (Pin 7) using three bits, XSL 0 to 2. IC measurement. Normally fixed to High. IC measurement. Normally fixed to Low. Synchronization window open input. Window masked when High; window open when Low (forced synchronization). Equipped with a pull-up resistor. Digital power supply Connected to the IC internal circuit board (same electric potential as power supply). Connect to GND on the printed circuit board via a capacitor. DESCRIPTION Analog power supply for Channel-2 AD converter.
SYMBOL AV DD 2 NC SUB NC DVSS XMCK2 TEST CLR DVDD MS LRCK BCK
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SIN SOUT DVSS MASL MLSL XSL0 XSL1 XSL2 DASL0 DASL1 WO DVDD NC NC SUB AV DD 1 AIN1 AVSS 1 AVSS 3 AOUT1(+)
I O I I I I I I I I I O
Connected to the IC internal circuit board (same electric potential as power supply). Connect to GND on the printed circuit board via a capacitor. Analog power supply for Channel-1 AD converter. Analog input for Channel-1 AD converter. Analog GND for Channel-1 AD converter. Analog GND for Channel-1 DA converter. Analog in-phase output for Channel-1 DA converter.
4-303
HI2555, CXD2555
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Operating Temperature (TOPR) . . . . . . . . . . . . . . . . . -20oC to 75oC Storage Temperature (TSTG) . . . . . . . . . . . . . . . . . . -55oC to 150oC
Supply Voltage (V DD). . . . . . . . . . . . . . . . . . . . . . . .VSS -0.5V to 7V Input Voltage (V 1). . . . . . . . . . . . . . . . . . . . VSS -0.5V to V DD +0.5V Output Voltage (V 0) . . . . . . . . . . . . . . . . . . VSS -0.5V to V DD +0.5V
Recommended Operating Conditions
ITEM MIN Supply Voltage (Note 1) (VDD) . . . . . . . . . . . +4.75 Ambient Temperature (TA) . . . . . . . . . . . . . . -20oC Sampling Frequency (Note 2) (fS) . . . . . . . . 30kHz NOTES: TYP +5.0 MAX +5.25V 75oC 50kHz ITEM MIN TYP MAX Input Pin (CIN). . . . . . . . . . . . . . . . . . . . . . . 9pF Output Pin (COUT . . . . . . . . . . . . . . . . . . . . 11pF Bi-Directional Pin (CI/O) . . . . . . . . . . . . . . . 11pF Measurement Conditions . . . . . . . . . . . . . VDD = VI = 0V, f = 1MHz
1. The analog power supplies for AD converters (Pins 17 and 44) must be turned on simultaneously with or before other power supplies. turning on these power supplies after any other power supply may cause the device to fall into latch-up condition. This precaution, however, does not apply when turning off the power supplies. 2. Although the device can operate with low fS frequencies such as fS = 8kHz or 16kHz, its analog characteristics deteriorate to extent. When used at only these low frequencies, the CXD2570Q is recommended that is pin-compatible with the CXD2555Q.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications (AVDD1 = AVDD 2 = AVDD 3 = AVDD 4 = XVDD = 5.0V 10%,
AVSS 1 = AVSS 2 = AVSS 3 = AVSS 4 = XVSS = DVSS = 0V, TA = -20oC to 75oC) TEST CONDITIONS MIN 0.7 VDD Analog Input IOH = -2mA IOL = 4mA IOH = -4mA IOL = 4mA IOH = 12mA IOL = 16mA IOH = -2mA IOL = 4mA VSS VDD -0.5 0 VDD -0.5 0 VDD/2 0 VDD -0.8 0 -10 -40 -20 20 -40 VIN = VSS or VDD (Note 3) 250k TYP -50 50 1M 57 MAX 0.3 VDD VDD 0.4 0.4 VDD 0.4 V VDD/2 VDD 0.4 10 40 -120 120 40 2.5M 75 A A A A A mA (Note 10) (Note 11) (Note 12) (Note 13) (Note 14) (Note 15) V (Note 9) V (Note 8) V (Note 7) V V (Note 5) (Note 6) UNITS V APPLICABLE PIN (Note 4)
PARAMETER Input Voltage
SYMBOL VIHC VILC VIN
Output Voltage
VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4
Input Leakage Current
IL11 IL12 IL13 IL14
Output Leakage Current Feedback Resistance Supply Current NOTES:
ILZ RFB IDD
3. This includes current consumption at load resistance (R L = 3.9k). 4. When all input pins except AIN1 and AIN2, and bi-directional pins (BCK, LRCK) are input. 5. AIN1 and AIN2. 6. XCLK, XMCK2, and SOUT. 7. AOUT1 (+), AOUT 1 (-), AOUT2 (+), AOUT2 (-), and UCLK. 8. XTLO. 9. When bi-directional pins (BCK, LRCK) are output. 10. All input pins except AIN1 and AIN2. 11. When bi-directional pins (BCK, LRCK) are input. 12. MS, WO, and CLR. 13. TEST. 14. SOUT, AOUT1 (+), AOUT1 (-), AOUT2 (+), AOUT2 (-), and UCLK. 15. Resistance between XTLO and XTLI.
4-304
HI2555, CXD2555
AC Electrical Specifications
PARAMETER SIN Setup Time SIN Hold Time LRCK Setup Time LRCK Hold Time LRCK Delay Time SOUT Delay Time SOUT Data Reset Time SOUT Data Erase Time XTLI Pulse Width AVSS 1 = AVSS 2 = AVSS 3 = AVSS 4 = XVSS = DVSS = 0V, TA = -20oC to 75oC SYMBOL tsus ths tsul thl tdl tds tzd tdz twl fS = 48kHz, 256fS (XSL0 = XSL1 = XSL2 = L) Slave Mode Slave Mode Master Mode CL = 130pF CL = 60pF TEST CONDITIONS MIN 10 15 10 15 -40 9 7 6 40 MAX 30 65 42 40 60 UNITS ns ns ns ns ns ns ns ns ns AVDD1 = AVDD 2 = AVDD 3 = AVDD 4 = XVDD = 5.0V 10%,
Analog Specifications
PARAMETER
AVDD1 = AVDD 2 = AVDD 3 = AVDD 4 = XVDD = 5.0V 10%, AVSS 1 = AVSS 2 = AVSS 3 = AVSS 4 = XVSS = DVSS = 0V, TA = -20oC to 75oC TEST CONDITIONS MIN TYP MAX UNIT
Overall Characteristics of ADC + DAC Connection: The following conditions apply unless otherwise specified: Input waveform = 1kHz sine wave, 1.4VRMS (= 0dB) XTAI = 33.8688MHz (= 768fS, fS = 44.1kHz) CLR = MS = WO = Open (= 5V) SOUT and SIN directly coupled
S/N THD + N Dynamic Range Channel Separation Gain Difference Between Channels Gain Input Level RL = 3.9k RIN = 0 RIN = 4.7k DC Offset (ADC Output) ADC Input Impedance A-Weighting Filter 20kHz LPF 1kHz, - 60dB, 20kHz LPF 20kHz, 0dB 80 80 -3 86 0.010 85 96 0.1 0 0.286 1.4 069F 1.2 0.018 +3 dB % dB dB dB dB VRMS VRMS Hex k
Analog Specifications AVDD1 = AVDD 2 = AVDD 3 = AVDD 4 = XVDD = 5.0V 10%,
PARAMETER TEST CONDITIONS
AVSS 1 = AVSS 2 = AVSS 3 = AVSS 4 = XVSS = DVSS = 0V, TA = -20oC to 75oC MIN TYP MAX UNIT
DAC Specifications in Single Unit: The following conditions apply unless otherwise specified: Input data = 1kHz sine wave,full
scale (= 0dB), XTAI = 33.8688MHz (= 768fS, fS = 44.1kHz), CLR = MS = WO = Open (= 5V), MS = GND S/N THD + N Dynamic Range Channel Separation Gain Difference Between Channels Output Level RL = 3.9k A-Weighting Filter 20kHz LPF 1kHz, - 60dB, 20kHz LPF 20kHz, 0dB 92 85 1.80 96 0.008 89 100 0.05 1.93 0.012 2.10 dB % dB dB dB VRMS
4-305
HI2555, CXD2555 Test Circuits
IN 10F 4.7K
+
+
AIN 1/2 100K
FIGURE 34. ADC INPUT SECTION
+5V RL AOUT 1/2 (-) RL 130K
820pF
+ 47pF 4.7K
0.015F 4.7K
+
4.7K
4.7K 1800pF
4.7K
OUT + 82pF
4.7K +5V RL AOUT 1/2 (+) RL 130K
4.7K
820pF
+ 47pF RL = 3.9k
FIGURE 35. DAC OUTPUT SECTION
4-306
HI2555, CXD2555 Timing Diagram
tzd tds tdz
SOUT
BCK tsus ths
SIN
LRCK (SLAVE MODE) thl BCK tdl tsul
LRCK (MASTER MODE) twl
XTLI
FIGURE 36.
Description of Functions
Serial Data Interface (Related Pins) LRCK, BCK, SOUT, SIN, MASL, MLSL The serial data format is common for both SIN (DA converter input) and SOUT (AD converter output), consisting of two channels per sampling serial data represented by 2's complement. Each channel is divided into 32-bit slots, of which 16 bits are handled as data. MASL is used to select whether the 16 bits of valid data is placed in the first or the second half of the 32-bit slots.
TABLE 1. MASL H L Forward Packing Rearward Packing MLSL L LSB first TABLE 2.
Similarly, MLSL is used to select whether the serial data is arranged at LSB first or MSB first.
TABLE 2. MLSL H MSB first
4-307
HI2555, CXD2555
Master Mode/Slave Mode (Related Pins) MS, LRCK, BCK When using the XCS2555Q in multiple units or in a pair with DA converters such as the CXD2558M, one of these CXD2555Qs should be in the master mode to serve as the source of clocks LRCK and BCK. The other CXD2555Qs are used in the slave mode, with their clocks LRCK and BCK supplied by the master CXD2555Q.
TABLE 3. MS H L MODE Master Mode Slave Mode LRCK AND BCK I/O Output Input
Crystal Oscillator Frequency Selection (fS = 32kHz to 48kHz) (Related Pins) XTLI, XTLO, XSLO, XSL1, XSL2, UNCLK, XCLK By setting a combination of XSLO and XSL1, with XSL2 fixed Low, the frequency of the external crystal oscillator connected to XTLI and XTLO can be selected. In this case, XCLK outputs a clock whose frequency is always 256 times fS, and UCLK outputs a clock that is half the crystal oscillator frequency. When supplying the master clock fro some other external source, not a crystal oscillator, use XTLI for this clock input and leave XTLO open.
TABLE 4.
XSL2 L L L L
XSL1 L L H H
XSL0 L H L H
CRYSTAL OSCILLATOR FREQUENCY 256fS 512fS 768fS 1024fS
XCLK 256fS 256fS 256fS 256fS
UCLK 128fS 256fS 384fS 512fS
LRCK H
OUTPUT
INPUT
LRCK CXD2555Q MS (SLAVE MODE) BCK L
MS CXD2555Q (MASTER MODE) OUTPUT BCK
INPUT
INPUT INPUT
LRCK CXD2558M BCK
FIGURE 37. CONNECTION EXAMPLE
Crystal Oscillator Frequency Selection
(fS = 8kHz to 24kHz)
(Related Pins) XTLI, XTLO, XSLO, XSL1, XSL2, UNCLK, XCLK With XSL2 fixed High, the device can be operated with lowfS frequencies which may be 1/2 or 1/4 the normal fS frequency. In this case, the frequency of the crystal oscillator can be selected by setting a combination of XSL0 and XSL1 accordingly. AD Converter Input Level Given the constants shown in the Test Circuit on page 7, the AD converter input level V IN (operational amplifier input IN) is such that 4V P-P (1.4VRMS) is equivalent to the full-scale output. Also, the large-amplitude inputs are possible by varying the AD converter input resistance value (RIN). Use the equation shown below to calculate this resistance value. The AD converter generates full-scale outputs for inputs equal to or greater than the values thus obtained. RIN = 420 * VIN [RMS] - 1200 []
L H H
XSL2
UCLK
512fS
TO EXTERNAL IC, SUCH AS DSP
XSL1 CXD2555Q XSL0 XTL1 XCLK XTL0 256fS TO CXD2555Q IN SLAVE MODE
1024fS
FIGURE 38. CONNECTION EXAMPLE
Example: When input level = 1.4VRMS (4V P-P) RIN = 4200 * 1.4 - 1200 = 4680 4700 []
4-308
CXD2555Q
VIN
10F 10F
RIN AIN 100K
+
FIGURE 39. TABLE 5. CRYSTAL OSCILLATOR FREQUENCY (NOTE 16) 512fS 1024fS 1024fS 2048fS FREQUENCY DIVISION RATIO RELATIVE TO NORMAL f S FREQUENCY 1/2 1/4 1/2 1/4 EXAMPLE OF 32kHz NORMAL FREQUENCY fS = 16kHz fS = 8kHz fS = 16kHz fS = 8kHz
XSL2 H H H H NOTE:
XSL1 L L H H
XSL0 L H L H
XCLK 512fS 1024fS 512fS 1024fS
UCLK 256fS 512fS 512fS 1024fS
16. When the normal frequency is assumed to be 32kHz, its derived frequency is 16kHz when divided by 2, or 8kHz when divided by 4. When divided in the same way, the low-fS frequencies for 44.1kHz are 22.05kHz and 11.025kHz, and for 48kHz, they are 24kHz and 12kHz.
4-309
Serial Data Interface Timing
HI2555, CXD2555
4-310
Application Circuit Master Mode (MS = High)
HI2555, CXD2555
4-311

▲Up To Search▲

Price & Availability of CXD2555

	To Download CXD2555 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .