View TPS65020_230145.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TPS65020
www.ti.com
SLVS607 - SEPTEMBER 2005
POWER MANAGEMENT IC FOR LI-ION POWERED SYSTEMS
FEATURES
* * * * * * * * * * * * * * * * * * * * * 1.2 A, 97% Efficient Step-Down Converter for System Voltage (VDCDC1) 1 A, Up to 95% Efficient Step-Down Converter for Memory Voltage (VDCDC2) 800 mA, 90% Efficient Step-Down Converter for Processor Core (VDCDC3) 20 mA LDO/Switch for Real Time Clock (VRTC) 2 x 50 mA LDO for SRAM and PLL Dynamic Voltage Management for Processor Core Externally Adjustable Reset Delay Time Battery Backup Functionality Separate Enable Pins for Inductive Converters I2CTM Compatible Serial Interface 85-A Quiescent Current Low Ripple PFM Mode Thermal Shutdown Protection Push Button I/O
DESCRIPTION
The TPS65020 is an integrated Power Management IC for applications powered by one Li-Ion or Li-Polymer cell, and which require multiple power rails. The TPS65020 provides three highly efficient, step-down converters targeted at providing the core voltage, peripheral, I/O and memory rails in a processor based system. All three step-down converters enter a low-power mode at light load for maximum efficiency across the widest possible range of load currents. The TPS65020 also integrates two 50 mA LDO voltage regulators, which are enabled with an external input pin. Each LDO operates with an input voltage range between 1.5 V and 6.5 V, allowing them to be supplied from one of the step-down converters or directly from the main battery. The two 50-mA LDO voltage regulators are intended for use with the SDRAM and PLL power supply in a Intel PXA270 based system. The serial interface is used for dynamic voltage scaling of the core voltage, masking interrupts, or for dis/enabling and setting the LDO output voltages. The interface is compatible with the Fast/Standard mode I2CTM specification, allowing transfers at up to 400 kHz. The TPS65020 incorporates a push button debounced input and latched output for implementation of a push-button turn-on feature, typically required in smartphones or wireless PDAs.
APPLICATIONS
PDA Cellular/Smart Phone Internet Audio Player Digital Still Camera Digital Radio Player Split Supply DSP and P Solutions: OMAP1610, OMAP1710, OMAP330 Intel PXA270, etc.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. I2C is a trademark of Philips Electronics.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2005, Texas Instruments Incorporated
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION
TA -40C to 85C (1) PACKAGE 40 pin QFN (RHA) PART NUMBER (1) TPS65020RHA
The RHA package is available in tape and reel. Add the R suffix (TPS65020RHAR) to order quantities of 2500 parts per reel. Add the T suffix (TPS65020RHAT) to order quantities of 250 parts per reel.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE VI Input voltage range on all pins except AGND and PGND pins with respect to AGND Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3 Peak Current at all other pins Continuous total power dissipation TA TJ Operating free-air temperature Maximum junction temperature Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds (1) -0.3 to 7 2000 1000 See Dissipation Rating Table -40 to 85 125 -65 to 150 260 C C C C UNIT V mA mA
Tstg Storage temperature
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
DISSIPATION RATINGS
PACKAGE RHA (1) (2) (1) (2) TA 25C POWER RATING 2.85 W DERATING FACTOR ABOVE TA = 25C 28 mW/C TA = 70C POWER RATING 1.57 W TA = 85C POWER RATING 1.4 W
The thermal resistance junction to ambient of the RHA package is 32C/W measured on a high K board. The thermal resistance junction to case (exposed pad) of the RHA package is 5C/W
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN VCC Input voltage range step-down convertors (VINDCDC1, VINDCDC2, VINDCDC3) Output voltage range for VDCDC1 step-down VO VI VO IO(DCDC1) CI(DCDC1) CO(DCDC1) IO(DCDC2) convertor (1) convertor (1) Output voltage range for VDCDC2 step-down convertor (1) Output voltage range for VDCDC3 (core) step-down Input voltage range for LDOs (VINLDO1, VINLDO2) Output voltage range for LDOs (VLDO1, VLDO2) Output current at L1 Inductor at L1 (2) Input Capacitor at VI(DCDC1) (2) Output Capacitor at VDCDC1 Output current at L2 Inductor at L2 (1) (2) 2
(2) (2)
NOM
MAX 6 VINDCDC1 VINDCDC2 VINDCDC3 6.5 VINLDO1-2 1200
UNIT V
2.5 0.6 0.6 0.6 1.5 1 2.2 10 10 2.2 22 3.3
V V V mA H F F
1000 3.3
mA H
When using an external resistor divider at DEFDCDC3, DEFDCDC2, DEFDCDC1 See applications section for more information.
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
MIN CI(DCDC2) CO(DCDC2) IO(DCDC3) CI(DCDC3) CO(DCDC3) CI(VCC) Ci(VINLDO) CO(VLDO1-2) IO(VLDO1-2) CO(VRTC) TA TJ Input Capacitor at VI(DCDC2) (2) Output Capacitor at VDCDC2 Output current at L3 Inductor at L3
(2) (2)
NOM 22
MAX
UNIT F F
10 10 2.2 10
(2)
800 3.3 22
mA H F F F F F
Input Capacitor at VI(DCDC3) (2) Output Capacitor at VDCDC3 Input Capacitor at VCC
(2) (2) (2)
10 1 1 2.2
Input Capacitor at VINLDO
Output Capacitor at VLDO1, VLDO2 Output current at VLDO1, VLDO2 Output Capacitor at VRTC
(2)
50 4.7 -40 -40 1 85 125 10
mA F C C
Operating ambient temperature Operating junction temperature Resistor from VINDCDC3, VINDCDC2, VINDCDC1 to VCC used for filtering (3)
(3)
Up to 3 mA can flow into VCC when all 3 converters are running in PWM. This resistor causes the UVLO threshold to be shifted accordingly.
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted)
PARAMETER VIH VIL IH VIH VIL High level input voltage Low level input voltage Input bias current High level input voltage Low level input voltage Pull up resistor at /HOT_RESET, connected to VCC tglitch VOH VOL Deglitch time at HOT_RESET High level output voltage Low level output voltage Duration of low pulse at RESPWRON Resetpwron threshold VRTC falling Resetpwron threshold VRTC rising IIL = 5 mA External capacitor 1 nF -3% -3% 0 100 2.4 2.52 3% 3% 25 CONTROL SIGNALS : LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (output) 6 0.3 V V ms V V 1.3 0 1000 30 35 TEST CONDITIONS Rpullup = 4.7 kR, pulled to VRTC Rpullup = 4.7 kR, pulled to VRTC MIN 1.3 0 0.01 TYP MAX VCC 0.4 0.1 VCC 0.4 UNIT V V A V V k ms CONTROL SIGNALS : SCLK, SDAT (input), DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN
CONTROL SIGNALS : HOT_RESET
3
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted)
PARAMETER TEST CONDITIONS All 3 DCDC converters enabled, zero load and no switching, LDOs enabled All 3 DCDC converters enabled, zero load and no switching, LDOs enabled DCDC1 and DCDC2 converters enabled, zero load and no switching, LDOs off DCDC1 converter enabled, zero load & no switching, LDOs off All 3 DCDC converters enabled and running in PWM, LDOs off II Current into VCC; PWM DCDC1 and DCDC2 converters enabled and running in PWM, LDOs off DCDC1 converter enabled and running in PWM, LDOs off All converters disabled, LDOs off I(q) Quiescent current All converters disabled, LDOs off All converters disabled, LDOs off VCC = 3.6 V, VBACKUP = 3 V; VVSYSIN = 0 V VCC = 3.6 V, VBACKUP = 3 V; VVSYSIN = 0 V VCC = 3.6 V, VBACKUP = 3 V; VVSYSIN = 0 V VCC = 3.6 V, VBACKUP = 3 V; VVSYSIN = 0 V VCC = 3.6 V, VBACKUP = 3 V; VVSYSIN = 0 V VCC = 3.6 V, VBACKUP = 3 V; VVSYSIN = 0 V VCC = 3.6 V, VBACKUP = 3 V; VVSYSIN = 0 V VCC = 3.6 V, VBACKUP = 3 V; VVSYSIN = 0 V VCC = 2.6 V, VBACKUP = 3 V; VVSYSIN = 0 V VCC = 3.6 V, VBACKUP = 3 V; VVSYSIN = 0 V MIN TYP MAX UNIT SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3 85 100
I(qPFM)
Operating quiescent current, PFM
78
90 A
57 43 2 1.5 0.85 23 3.5
70 55 3 2.5 2 33 5 43 A A A mA
4
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted)
PARAMETER SUPPLY PINS: VCACKUP, VSYSIN, VRTC I(q) I(SD) Operating quiescent current Operating quiescent current VRTC LDO output voltage IO Output current for VRTC VRTC short-circuit current limit Maximum output current at VRTC for RESPWRON = 1 VO Output voltage accuracy for VRTC Line regulation for VRTC Load regulation VRTC Regulation time for VRTC Ilkg Input leakage current at VSYSIN rDS(on) of VSYSIN switch rDS(on) of VBACKUP switch Input voltage range at VBACKUP (1) Input voltage range at VSYSIN (1) VSYSIN threshold VSYSIN threshold VBACKUP threshold VBACKUP threshold SUPPLY PIN: VINLDO I(q) I(SD) (1) Operating quiescent current Shutdown current Current per LDO into VINLDO Total current for both LDOs into VINLDO, VLDO = 0 V 16 0.1 30 1 A A VSYSIN falling VSYSIN rising VBACKUP falling VBACKUP falling 2.73 2.73 -3% -3% -3% -3% 2.55 2.65 2.55 2.65 VBACKUP = 3 V, VSYSIN = 0 V; VCC = 2.6 V, current into VBACKUP VBACKUP < V_VBACKUP, current into VBACKUP VSYSIN = VBACKUP = 0 V, IO = 0 mA VSYSIN < 2.57 V and VBACKUP < 2.57 V VRTC = GND; VSYSIN = VBACKUP = 0 V VRTC > 2.6 V, VCC = 3 V; VSYSIN = VBACKUP = 0 V VSYSIN = VBACKUP = 0 V; Io = 0 mA VCC = VRTC + 0.5 V to 6.5 V, IO = 5 mA IO = 1 mA to 20 mA; VSYSIN = VBACKUP = 0 V Load change from 10% to 90% VSYSIN < V_VSYSIN 10 2 12.5 12.5 3.75 3.75 3% 3% 3% 3% 30 1% 1% 2% s A V V V V V V 20 2 3 20 100 33 3 A A V mA mA mA TEST CONDITIONS MIN TYP MAX UNIT
Based on the requirements for the Intel PXA270 processor.
5
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted)
PARAMETER VDCDC1 STEP-DOWN CONVERTER VI IO I(SD) rDS(on) Ilkg rDS(on) Ilkg fS Input voltage range, VINDCDC1 Maximum output current Shutdown supply current in VINDCDC1 P-channel MOSFET on-resistance P-channel leakage current N-channel MOSFET on-resistance N-channel leakage current Forward current limit (P- and N-channel) Oscillator frequency Fixed output voltage FPWMDCDC1=0 3V 3.3 V 3V 3.3 V VINDCDC1 = 3.3 V to 6 V; 0 mA IO 1.2 A VINDCDC1 = 3.6 V to 6 V; 0 mA IO 1.2 A VINDCDC1 = 3.3 V to 6 V; 0 mA IO 1.2 A VINDCDC1 = 3.6 V to 6 V; 0 mA IO 1.2 A VINDCDC1 = VDCDC1 +0.3 V (min 2.5 V) to 6 V; 0 mA IO 1.2 A VINDCDC1 = VDCDC1 +0.3 V (min 2.5 V) to 6 V; 0 mA IO 1.2 A VINDCDC1 = VDCDC1 + 0.3 V (min. 2.5 V) to 6 V; IO = 10 mA IO = 10 mA to 1200 mA VDCDC1 ramping from 5% to 95% of target value DCDC1_EN = GND VINDCDC1 = V(GS) = 3.6 V VINDCDC1 = 6 V VINDCDC1 = V(GS) = 3.6 V V(DS) = 6 V 2.5 V < VI(MAIN) < 6 V 1.55 1.3 -2% -2% -1% -1% -2% -1% 0 0.25 750 1 300 130 7 1.75 1.5 2.5 1200 0.1 125 1 261 2 260 10 1.95 1.7 2% 2% 1% 1% 2% 1% %/V %/A s M 6.0 V mA A m A m A A MHz TEST CONDITIONS MIN TYP MAX UNIT
Fixed output voltage FPWMDCDC1=1
Adjustable output voltage with resistor divider at DEFDCDC1 FPWMDCDC1=0 Adjustable output voltage with resistor divider at DEFDCDC1; FPWMDCDC1=1 Line Regulation Load Regulation Soft start ramp time Internal resistance from L1 to GND VDCDC1 discharge resistance
6
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted)
PARAMETER VDCDC2 STEP-DOWN CONVERTER VI IO I(SD) rDS(on) Ilkg rDS(on) Ilkg ILIMF fS Input voltage range, VINDCDC2 Maximum output current Shutdown supply current in VINDCDC2 P-channel MOSFET on-resistance P-channel leakage current N-channel MOSFET on-resistance N-channel leakage current Forward current limit (P- and N-channel) Oscillator frequency Fixed output voltage FPWMDCDC2=0 1.8 V 2.5 V 1.8 V 2.5 V VINDCDC2 = 2.5 V to 6 V; 0 mA IO 1.0 A VINDCDC2 = 2.8 V to 6 V; 0 mA IO 1 A VINDCDC2 = 2.5 V to 6 V; 0 mA IO 1 A VINDCDC2 = 2.8 V to 6 V; 0 mA IO 1 A VINDCDC2 = VDCDC2 +0.3 V (min 2.5 V) to 6 V; 0 mA IO 1.0 A VINDCDC2 = VDCDC2 +0.3 V (min 2.5 V) to 6 V; 0 mA IO 1.0 A VINDCDC2 = VDCDC2 + 0.3 V (min. 2.5 V) to 6 V; IO = 10 mA IO = 10 mA to 1 mA VDCDC2 ramping from 5% to 95% of target value DCDC2_EN = GND VINDCDC2 = V(GS) = 3.6 V VINDCDC2 = 6 V VINDCDC2 = V(GS) = 3.6 V V(DS) = 6 V 2.5 V < VINDCDC2 < 6 V 1.40 1.3 -2% -2% -2% -1% -2% -1% 0 0.25 750 1 300 150 7 1.55 1.5 2.5 1000 0.1 140 1 300 2 297 10 1.70 1.7 2% 2% 2% 1% 2% 1% %/V %/A s M 6 V mA A m A m A A MHz TEST CONDITIONS MIN TYP MAX UNIT
Fixed output voltage FPWMDCDC2=1
Adjustable output voltage with resistor divider at DEFDCDC2 FPWMDCDC2=0 Adjustable output voltage with resistor divider at DEFDCDC2; FPWMDCDC2=1 Line Regulation Load Regulation Soft start ramp time Internal resistance from L2 to GND VDCDC2 discharge resistance
7
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted)
PARAMETER VDCDC3 STEP-DOWN CONVERTER VI IO I(SD) rDS(on) Ilkg rDS(on) Ilkg fS Input voltage range, VINDCDC3 Maximum output current Shutdown supply current in VINDCDC3 P-channel MOSFET on-resistance P-channel leakage current N-channel MOSFET on-resistance N-channel leakage current Forward current limit (P- and N-channel) Oscillator frequency Fixed output voltage FPWMDCDC3=0 Fixed output voltage FPWMDCDC3=1 VINDCDC3 = 2.5 V to 6 V; 0 mA IO 600 mA VINDCDC3 = 2.5 V to 6 V; 0 mA IO 600 mA VINDCDC3 = VDCDC3 +0.4 V (min 2.5 V) to 6 V; 0 mA IO 600 mA VINDCDC3 = VDCDC3 +0.4 V (min 2.5 V) to 6 V; 0 mA IO 600 mA VINDCDC3 = VDCDC3 + 0.3 V (min. 2.5 V) to 6 V; IO = 10 mA IO = 10 mA to 400 mA VDCDC3 ramping from 5% to 95% of target value DCDC3_EN = GND VINDCDC3 = V(GS) = 3.6 V VINDCDC3 = 6 V VINDCDC3 = V(GS) = 3.6 V V(DS) = 6 V 2.5 V < VINDCDC3 < 6 V 1.05 1.3 -2% -1% -2% -1% 0.0 0.25 750 1 300 2.5 800 0.1 310 0.1 220 7 1.2 1.5 1 698 2 503 10 1.35 1.7 2% 1% 2% 1% %/V %/A s M 6 V mA A m A m A A MHz TEST CONDITIONS MIN TYP MAX UNIT
All VDCDC3
Adjustable output voltage with resistor divider at DEFDCDC3 FPWMDCDC3=0 Adjustable output voltage with resistor divider at DEFDCDC3; FPWMDCDC3=1 Line Regulation Load Regulation Soft start ramp time Internal resistance from L3 to GND VDCDC3 discharge resistance
8
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted)
PARAMETER VLDO1 and VLDO2 LOW DROPOUT REGULATORS VI VO VO IO I(SC) Input voltage range for LDO1, 2 LDO1 output voltage range LDO2 output voltage range Maximum output current for LDO1, LDO2 LDO1 and LDO2 short circuit current limit Minimum voltage drop at LDO1, LDO2 Minimum voltage drop at LDO1, LDO2 Output voltage accuracy for LDO1, LDO2 Line regulation for LDO1, LDO2 Load regulation for LDO1, LDO2 Regulation time for LDO1, LDO2 VIH VIL IH High level input voltage Low level input voltage Input bias current Low level output voltage at PB_OUT High level output voltage PB_OUT Low level input voltage PB_IN High level input voltage PB_IN II Input leakage current PB_IN THERMAL SHUTDOWN T(SD) Thermal shutdown Thermal shudown hysteresis INTERNAL UNDER VOLTAGE LOCK OUT UVLO V(UVLO_HYST) Internal UVLO Internal UVLO comparator hysteresis Comparator threshold (PWRFAIL_SNS, LOWBAT_SNS) Hysteresis Propagation delay POWER GOOD V(PGOODF) V(PGOODR) (1) VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, decreasing VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, increasing -12% -7% -10% -5% -8% -3% 25 mV overdrive VCC falling -2% 2.35 120 2% V mV Increasing junction temperature Decreasing junction temperature 160 20 C C 1.3 VLDO1 = GND, VLDO2 = GND IO = 50 mA, VINLDO = 1.8 V IO = 50 mA, VINLDO = 1.5 V IO = 10 mA VINLDO1,2 = VLDO1,2 + 0.5 V (min. 2.5 V) to 6.5 V, IO = 10 mA IO = 0 mA to 50 mA Load change from 10% to 90% 1.3 0 0.001 -2% -1% -1% 10 VCC 0.4 0.05 65 1.5 1 1.0 50 400 120 150 1% 1% 1% s V V A 6.5 3.3 3.3 V V V mA mA mV mV TEST CONDITIONS MIN TYP MAX UNIT
ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3
LOGIC SIGNALS PB_IN; PB_OUT VOL VOH VIL VIH IOL = 20 mA 0.5 6 0.4 Vcc (1) 1 V V V V A
VOLTAGE DETECTOR COMPARATORS Falling threshold -1% 40 1.0 50 1% 60 10 V mV s
The input voltage can go as high as 6 V. If the input voltage exceeds VCC, an input current of (V(PB_IN) - 0.7 V - VCC) / 10 kR flows.
9
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
PIN ASSIGNMENT (TOP VIEW)
PWRFAIL_SNS LOWBAT_SNS
DEFDCDC2
VINDCDC2
40 39 38 37 36 35 34 33 32 31 DEFDCDC3 VDCDC3 PGND3 L3 VINDCDC3 VINDCDC1 L1 PGND1 VDCDC1 DEFDCDC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 30
29
PWRFAIL
VDCDC2
AGND1
PGND2
VCC
L2
SCLK SDAT INT RESPWRON TRESPWRON DCDC1_EN DCDC2_EN DCDC3_EN LDO_EN LOWBAT
28 27 26 25 24 23 22 21
VSYSIN
VBACKUP
AGND2
VLDO2
HOT_RESET
TERMINAL FUNCTIONS
TERMINAL NAME AGND1 AGND2 PowerPADTM VINDCDC1 L1 VDCDC1 PGND1 VINDCDC2 L2 VDCDC2 PGND2 VINDCDC3 L3 VDCDC3 PGND3 VCC NO. 40 17 - 6 7 9 8 36 35 33 34 5 4 2 3 37 I I I I I I I I/O DESCRIPTION
SWITCHING REGULATOR SECTION Analog ground connection. All analog ground pins are connected internally on the chip. Analog ground connection. All analog ground pins are connected internally on the chip. Connect the power pad to analog ground. Input voltage for VDCDC1 step-down converter. This must be connected to the same voltage supply as VINDCDC2, VINDCDC3, and VCC. Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here. VDCDC1 feedback voltage sense input, connect directly to VDCDC1 Power ground for VDCDC1 converter Input voltage for VDCDC2 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC3, and VCC. Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here. VDCDC2 feedback voltage sense input, connect directly to VDCDC2 Power ground for VDCDC2 converter Input voltage for VDCDC3 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC2, and VCC. Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here. VDCDC3 feedback voltage sense input, connect directly to VDCDC3 Power ground for VDCDC3 converter Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 dc-dc converters. This must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2. Also supplies serial interface block
10
PB_OUT
VINLDO
VLDO1
PB_IN
VRTC
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
TERMINAL FUNCTIONS (continued)
TERMINAL NAME DEFDCDC1 NO. 10 I/O DESCRIPTION Input signal indicating default VDCDC1 voltage, 0 = 3 V, 1 = 3.3 V This pin can also be connected to a resistor divider between VDCDC1 and GND. If the output voltage of the DCDC1 converter is set in a range from 0.6 V to VINDCDC1 V Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 2.5 V This pin can also be connected to a resistor divider between VDCDC2 and GND. If the output voltage of the DCDC2 converter is set in a range from 0.6 V to VINDCDC2 V Input signal indicating default VDCDC3 voltage, 0 = 1.3 V, 1 = 1.55 V This pin can also be connected to a resistor divider between VDCDC3 and GND. If the output voltage of the DCDC3 converter is set in a range from 0.6 V to VINDCDC3 V VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator. VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator. VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator. I Input voltage for LDO1 and LDO2 Output voltage of LDO1 Output voltage of LDO2 Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs Connect the backup battery to this input pin. Output voltage of the LDO/switch for the real time clock Input of system voltage for VRTC switch Push button input used to reboot or wake-up processor via RESPWRON output pin Connect the timing capacitor to this pin to set the reset delay time: 1 nF 100 ms Open drain System reset output Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition. Open drain output of LOW_BAT comparator Open drain output Serial interface clock line Serial interface data/address Input for the comparator driving the PWRFAIL output Input for the comparator driving the LOW_BAT output Push button input debounced and output fed to latch at PB_OUT Open drain output of latch driven by PB_IN. Low after power up.
I
DEFDCDC2
32
I
DEFDCDC3 DCDC1_EN DCDC2_EN DCDC3_EN VINLDO VLDO1 VLDO2 LDO_EN VBACKUP VRTC VSYSIN CONTROL AND HOT_RESET TRESPWRON RESPWRON PWRFAIL LOW_BAT INT SCLK SDAT PWRFAIL_SNS LOWBAT_SNS PB_IN PB_OUT I2C
1 25 24 23 19 20 18 22 15 16 14 SECTION 11 26 27 31 21 28 30 29 38 39 12 13
I I I I I O O I I O I I I O O O O I I/O I I I/O I/O
LDO REGULATOR SECTION
11
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
VSYSIN THERMAL SHUTDOWN BBAT SWITCH VINDCDC1 DCDC1 STEP-DOWN CONVER TER Serial Interface L1 VDCDC1 DEFDCDC1 PGND1 SCLK SDAT
VCC VBACKUP VRTC
DCDC1_EN DCDC2_EN DCDC3_EN LDO_EN HOT_RESET RESPWRON CONTROL DCDC2 STEP-DOWN CONVERTER
VINDCDC2 L2 VDCDC2 DEFDCDC2 PGND2
VCC INT AGND1 VINDCDC3 LOWBAT_SNS PWRFAIL_SNS LOW_BATT PWRFAIL TRESPWRON L3 UVLO VREF OSC DCDC3 VDCDC3 STEP-DOWN CONVERTER DEFDCDC3 PGND3 PB_IN Input buffer
VLDO1 JK-flipflop PB_OUT 50-mA LDO
VLDO1
AGND2 VINLDO
VLDO2 VLDO2 50-mA LDO
12
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
TYPICAL CHARACTERISTICS
Graphs were taken using the EVM with the following inductor/output capacitor combinations:
CONVERTER VDCDC1 VDCDC2 VDCDC3 INDUCTOR VLCF4020-2R2 VLCF4020-2R2 VLF4012AT-2R2M1R5 OUTPUT CAPACITOR C2012X5R0J106M C2012X5R0J106M C2012X5R0J106M OUTPUT CAPACITOR VALUE 2 x 10 F 2 x 10 F 2 x 10 F
Table 1. Table of Graphs
FIGURE Efficiency Line transient response Load transient response VDCDC2 PFM operation VDCDC2 low ripple PFM operation VDCDC2 PWM operation Startup VDCDC1, VDCDC2 and VDCDC3 Startup LDO1 and LDO2 Line transient response Load transient response DCDC1: EFFICIENCY vs OUTPUT CURRENT
VI = 3.8 V
vs Output current
1, 2, 3, 4, 5, 6, 7 8, 9, 10 11, 12, 13 14 15 16 17 18 19, 20, 21 22, 23, 24 DCDC1: EFFICIENCY vs OUTPUT CURRENT
VI = 5 V
VI = 4.2 V
VI = 4.2 V VI = 3.8 V VI = 5 V
Efficiency - %
TA = 25 C VO = 3.3 V PFM / PWM Mode 0.01 0.1 1 10 100 1k 10 k 0.01 0.1 1 10
o
Efficiency - %
TA = 25 C VO = 3.3 V PWM Mode 100 1k 10 k
o
IO - Output Current - mA
IO - Output Current - mA
Figure 1.
Figure 2.
13
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
DCDC2: EFFICIENCY vs OUTPUT CURRENT
VI = 2.5 V
DCDC2: EFFICIENCY vs OUTPUT CURRENT
VI = 3.8 V
Efficiency - %
Efficiency - %
VI = 3.8 V VI = 4.2 V
VI = 2.5 V
VI = 4.2 V
VI = 5 V TA = 25 C VO = 1.8 V PWM / PFM Mode
o
VI = 5 V
o
TA = 25 C VO = 1.8 V PWM Mode
0.01
0.1
1
10
100
1k
10 k
0.01
0.1
1
10
100
1k
10 k
IO - Output Current - mA
IO - Output Current - mA
Figure 3. DCDC3: EFFICIENCY vs OUTPUT CURRENT
VI = 3 V VI = 2.5 V TA = 25 C VO = 1.55 V PWM Mode
o
Figure 4. DCDC3: EFFICIENCY vs OUTPUT CURRENT
VI = 3.8 V
Efficiency - %
Efficiency - %
VI = 3.8 V VI = 4.2 V
VI = 3 V
VI = 5 V TA = 25 C VO = 1.55 V PWM / PFM Mode 0.1 1 10 100
1k
o
VI = 2.5 V
VI = 4.2 V
VI = 5 V
10 k
0.1
1
10
100
1k
10 k
IO - Output Current - mA
IO - Output Current - mA
Figure 5.
Figure 6.
14
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
DCDC3: EFFICIENCY vs OUTPUT CURRENT
VI = 3 V
VDCDC1 LINE TRANSIENT RESPONSE
Ch1 = VI Ch2 = VO
IO = 100 mA VO = 3.3 V PWM Mode
C1 High 4.74 V
Efficiency - %
VI = 2.5 V VI = 4.2 V VI = 5 V
VI = 3.8 V
C1 Low 3.08 V
C2 PK-PK 85 mV
TA = 25 C VO = 1.3 V Low Ripple PFM Mode 0.01 0.1 1 10
o
IO - Output Current - mA
Figure 7. VDCDC2 LINE TRANSIENT RESPONSE
IO = 100 mA VO = 1.8 V PWM Mode
Figure 8. VDCDC3 LINE TRANSIENT RESPONSE
Ch1 = VI Ch2 = VO IO = 100 mA VO = 1.6 V PWM Mode
Ch1 = VI Ch2 = VO
C1 High 4.04 V
C1 High 4.05 V
C1 Low 2.94 V
C1 Low 2.95 V
C2 PK-PK 49.9 mV
C2 PK-PK 46.0 mV
Figure 9.
Figure 10.
15
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
VDCDC1 LOAD TRANSIENT RESPONSE
VDCDC2 LOAD TRANSIENT RESPONSE
C4 High 1.09 A
C4 High 830 mA
C4 Low 120 mA
C4 Low 90 mA
C2 PK-PK 188 mV
C2 PK-PK 80 mV
Ch2 = VO Ch4 = IO
VI = 3.8 V VO = 3.3 V PWM Mode
Ch2 = VO Ch4 = IO
VI = 3.8 V VO = 1.8 V PWM Mode
Figure 11. VDCDC3 LOAD TRANSIENT RESPONSE
Figure 12. VDCDC2 OUTPUT VOLTAGE RIPPLE
VI = 3.8 V VO = 1.8 V IO = 1 mA o TA = 25 C PFM Mode
C4 High 730 mA
C4 Low 80 mA C2 PK-PK 17.0 mV
C2 PK-PK 80 mV
Ch2 = VO Ch4 = IO
VI = 3.8 V VO = 1.6 V TA = 25oC PWM Mode
Figure 13.
Figure 14.
16
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
VDCDC2 OUTPUT VOLTAGE RIPPLE
VO = 1.8 V VI = 3.8 V IO = 1 mA o TA = 25 C Low Ripple PFM Mode
VDCDC2 OUTPUT VOLTAGE RIPPLE
VI = 3.8 V VO = 1.8 V IO = 1 mA o TA = 25 C PWM Mode
C2 PK-PK 7.7 mV
Figure 15. STARTUP VDCDC1, VDCDC2, AND VDCDC3
ENABLE
Figure 16. STARTUP LDO1 AND LDO2
ENABLE
VDCDC1 LDO1
VDCDC2
VDCDC3
LDO2
Figure 17.
Figure 18.
17
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
LDO1 LINE TRANSIENT RESPONSE
Ch1 = VI Ch2 = VO IO = 25 mA VO = 1.1 V o TA = 25 C Ch1 = VI Ch2 = VO
LDO2 LINE TRANSIENT RESPONSE
IO = 25 mA VO = 3.3 V o TA = 25 C
C1 High 3.83 V
C1 High 4.51 V
C1 Low 3.29 V
C1 Low 3.99 V
C2 PK-PK 6.2 mV
C2 PK-PK 6.1 mV
Figure 19. VRTC LINE TRANSIENT RESPONSE
Ch1 = VI Ch2 = VO IO = 10 mA VO = 3 V o TA = 25 C
Figure 20. LDO1 LOAD TRANSIENT RESPONSE
C1 High 3.82 V
C4 High 48.9 mA
C1 Low 3.28 V
C4 Low 2.1 mA
C2 PK-PK 22.8 mV
C2 PK-PK 42.5 mV
Ch2 = VO Ch4 = IO
VI = 3.3 V VO = 1.1 V o TA = 25 C
Figure 21.
Figure 22.
18
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
LDO2 LOAD TRANSIENT RESPONSE
VRTC LOAD TRANSIENT RESPONSE
C4 High 47.8 mA
C4 High 21.4 mA
C4 Low -2.9 mA
C4 Low -1.4 mA
C2 PK-PK 40.4 mV
C2 PK-PK 76 mV
Ch2 = VO Ch4 = IO
VI = 4 V VO = 3.3 V o TA = 25 C
Ch2 = VO Ch4 = IO
VI = 3.8 V VO = 3 V o TA = 25 C
Figure 23.
Figure 24.
19
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
DETAILED DESCRIPTION VRTC OUTPUT AND OPERATION WITH OR WITHOUT BACKUP BATTERY
The VRTC pin is an always-on output, intended to supply up to 20 mA to a permanently required rail. This is the VCC_BATT rail of the Intel PXA270 processor for example. In applications using a backup battery, the backup voltage can be either directly connected to the TPS65020 VBACKUP pin if a Li-Ion cell is used, or via a boost converter (e.g. TPS61070) if a single NiMH battery is used. The voltage applied to the VBACKUP pin is fed through a PMOS switch to the VRTC pin. The TPS65020 asserts the RESPWRON signal if VRTC drops below 2.4 V. This, together with 250 mV at 20 mA drop out for the PMOS switch means that the voltage applied at VBACKUP must be greater than 2.65 V for normal system operation. When the voltage at the VSYSIN pin exceeds 2.65 V, the path from VBACKUP to VRTC is cut, and VRTC is supplied by a similar PMOS switch from the voltage source connected to the VSYSIN input. Typically this is the VDCDC1 converter but can be any voltage source within the appropriate range. In systems where no backup battery is used, the VBACKUP pin is connected to GND. In this case, a low power LDO is enabled, supplied from VCC and capable of delivering 20 mA to the 3 V output. This LDO is disabled if the voltage at the VSYSIN input exceeds 2.65 V. VRTC is then supplied from the external source connected to this pin as previously described
VSYSIN VBACKUP VCC
Vref V_VSYSIN priority #1
Vref V_VBACKUP V_VSYSIN V_VBACKUP EN VRTC LDO priority #3
priority #2
VRTC
Vref
RESPWRON
A. B.
V_VSYSIN, V_VBACKUP thresholds: falling = 2.55 V, rising = 2.65 V 3% RESPWRON thresholds: falling = 2.4 V, rising = 2.52 V 3%
Figure 25.
STEP-DOWN CONVERTERS, VDCDC1, VDCDC2, and VDCDC3
The TPS65020 incorporates three synchronous step-down converters operating typically at 1.5 MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the converters automatically enter the power save mode (PSM), and operate with pulse frequency modulation (PFM). The VDCDC1 converter is capable of delivering 1.2 A output current, the VDCDC2 converter is capable of delivering 1 A and the VDCDC3 converter is capable of delivering up to 800 mA. The converter output voltages can be programmed via the DEFDCDC1, DEFDCDC2 and DEFDCDC3 pins. The
20
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
DETAILED DESCRIPTION (continued)
pins can either be connected to GND, VCC, or to a resistor divider between the output voltage and GND. The VDCDC1 converter defaults to 3 V or 3.3 V depending on the DEFDCDC1 configuration pin. If DEFDCDC1 is tied to ground, the default is 3 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC1 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC1 V. See the application information section for more details. The VDCDC2 converter defaults to 1.8 V or 2.5 V depending on the DEFDCDC2 configuration pin. If DEFDCDC2 is tied to ground, the default is 1.8 V. If it is tied to VCC, the default is 2.5 V. When the DEFDCDC2 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC2 V. The VDCDC3 converter defaults to 1.3 V or 1.55 V depending on the DEFDCDC3 configuration pin. If DEFDCDC3 is tied to ground the default is 1.3 V. If it is tied to VCC, the default is 1.55 V. When the DEFDCDC3 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC3 V. The core voltage can be reprogrammed via the serial interface in the range of 0.8 V to 1.6 V with a programmable slew rate. The converter is forced into PWM operation whilst any programmed voltage change is underway, whether the voltage is being increased or decreased. The DEFCORE and DEFSLEW registers are used to program the output voltage and slew rate during voltage transitions. The step-down converter outputs (when enabled) are monitored by power good (PG) comparators, the outputs of which are available via the serial interface. The outputs of the dc-dc converters can be optionally discharged via on-chip 300 resistors when the dc-dc converters are disabled. This feature can be enabled using the I2C interface. During PWM operation, the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on. The inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded. After the adaptive dead time used to prevent shoot through current, the N-channel MOSFET rectifier is turned on, and the inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel rectifier and turning on the P-channel switch. The three dc-dc converters operate synchronized to each other with the VDCDC1 converter as the master. A 180 phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90 shift to the VDCDC3 switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for a typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7 V to 3.3 V, the VDCDC2 converter from 3.7 V to 2.5 V, and the VDCDC3 converter from 3.7 V to 1.5 V. The phase of the three converters can be changed using the CON_CTRL register.
POWER SAVE MODE OPERATION
As the load current decreases, the converters enter the power save mode operation. During PSM, the converters operate in a burst mode (PFM mode) with a switching frequency between half of the switching frequency and switching frequency for one burst cycle. However, the frequency between different burst cycles depends on the actual load current and is typically far less than the switching frequency with a minimum quiescent current to maintain high efficiency. In order to optimize the converter efficiency at light load, the average current is monitored and if in PWM mode the inductor current remains below a certain threshold, then PSM is entered. The typical threshold to enter PSM is calculated as follows:
21
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
DETAILED DESCRIPTION (continued)
IPFMDCDC1 enter = VINDCDC1 24 W VINDCDC2 26 W VINDCDC3 39 W
IPFMDCDC2 enter =
IPFMDCDC3 enter =
(1)
During the PSM the output voltage is monitored with a comparator, and by maximum skip burst width. As the output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the converter effectively delivers a constant current defined as follows. VINDCDC1 IPFMDCDC1 leave = 18 W
IPFMDCDC2 leave = VINDCDC2 20 W VINDCDC3 29 W
IPFMDCDC3 leave =
(2)
If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage has dropped below the threshold again. If the load current is greater than the delivered current, then the output voltage falls until it crosses the COMP LOW threshold, set to 2% below nominal VO, or the skip burst exceeds 16x1/switching frequency. Power Save Mode is exited and the converter returns to PWM mode. These control methods reduce the quiescent current to typically 14 A per converter, and the switching activity to a minimum, thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal output voltage at light load current results in a low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor. Increasing capacitor values makes the output ripple tend to zero. The PSM is disabled through the I2C interface to force the individual converters to stay in fixed frequency PWM mode.
LOW RIPPLE MODE
Setting Bit 3 in register CON-CTRL to 1 enables the low ripple mode for all of the dc-dc converters if operated in PFM mode. For an output current less than approximately 10 mA, the output voltage ripple in PFM mode is reduced, depending on the actual load current. The lower the actual output current on the converter, the lower the output ripple voltage. For an output current above 10 mA, there is only minor difference in output voltage ripple between PFM mode and low ripple PFM mode. As this feature also increases switching frequency, it is used to keep the switching frequency above the audible range in PFM mode down to a low output current.
SOFT START
Each of the three converters has an internal soft start circuit that limits the inrush current during start-up. The soft start is realized by using a very low current to initially charge the internal compensation capacitor. The soft start time is typically 750 s if the output voltage ramps from 5% to 95% of the final target value. If the output is already precharged to some voltage when the converter is enabled, then this time is reduced proportionally. There is a short delay of typically 170 s between the converter being enabled and switching activity actually starting. This is to allow the converter to bias itself properly, to recognize if the output is precharged, and if so to prevent discharging of the output while the internal soft start ramp catches up with the output voltage.
22
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
DETAILED DESCRIPTION (continued) 100% DUTY CYCLE LOW DROPOUT OPERATION
The TPS65020 converters offer a low input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage required to maintain dc regulation depends on the load current and output voltage. It is calculated as:
Vin min + Vout min * Iout max r DS(on) max * R L
(3)
with: Ioutmax = maximum load current (Note: ripple current in the inductor is zero under these conditions) rDS(on)max = maximum P-channel switch rDS(on) RL = DC resistance of the inductor Voutmin = nominal output voltage minus 2% tolerance limit
ACTIVE DISCHARGE WHEN DISABLED
When the VDCDC1, VDCDC2, and VDCDC3 converters are disabled, due to an UVLO, EN_x or OVERTEMP condition, it is possible to actively pull down the outputs. This feature is disabled per default and is individually enabled via the CON_CTRL2 register in the serial interface. When this feature is enabled, the VDCDC1, VDCDC2, and VDCDC3 outputs are discharged by a 300 (typical) load which is active as long as the converters are disabled.
POWER GOOD MONITORING
All three step-down converters and both the LDO1 and LDO2 linear regulators have power good comparators. Each comparator indicates when the relevant output voltage has dropped 10% below its target value with 5% hysteresis. The outputs of these comparators are available in the PGOODZ register via the serial interface. An interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled when the converters are disabled and the relevant PGOODZ register bits indicate that power is good.
LOW DROPOUT VOLTAGE REGULATORS
The low dropout voltage regulators are designed to operate well with low value ceramic input and output capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 150 mV at rated output current. Each LDO supports a current limit feature. Both LDOs are enabled by the EN_LDO pin, both LDOs can be disabled or programmed via the serial interface using the REG_CTRL and LDO_CTRL registers. The LDOs also have reverse conduction prevention. This allows the possibility to connect external regulators in parallel in systems with a backup battery. The TPS65020 step-down and LDO voltage regulators automatically power down when the VBAT voltage drops below the UVLO threshold or when the junction temperature rises above 160C.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit for the five regulators on the TPS65020 prevents the device from malfunctioning at low-input voltages and from excessive discharge of the battery. It disables the converters and LDOs. The UVLO circuit monitors the VCC pin, the threshold is set internally to 2.35 V with 5% (120 mV) hysteresis. Note that when any of the dc-dc converters are running, there is an input current at the VCC pin, which is up to 3 mA when all three converters are running in PWM mode. This current needs to be taken into consideration if an external RC filter is used at the VCC pin to remove switching noise from the TPS65020 internal analog circuitry supply.
POWER-UP SEQUENCING
The TPS65020 power-up sequencing is designed to be entirely flexible and customer driven. This is achieved by providing separate enable pins for each switch-mode converter, and a common enable signal for the LDOs. The relevant control pins are described in Table 2.
23
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
DETAILED DESCRIPTION (continued)
Table 2. Control Pins and Status Outputs for DC-DC Converters
PIN NAME DEFDCDC3 DEFDCDC2 DEFDCDC1 DCDC3_EN DCDC2_EN DCDC1_EN HOT_RESET INPUT OUTPUT I I I I I I I FUNCTION Defines the default voltage of the VDCDC3 switching converter. DEFDCDC3 = 0 defaults VDCDC3 to 1.3 V, DEFDCDC3 = VCC defaults VDCDC3 to 1.55 V. Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to 1.8 V, DEFDCDC2 = VCC defaults VDCDC2 to 2.5 V. Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 3 V, DEFDCDC1 = VCC defaults VDCDC1 to 3.3 V. Set DCDC3_EN = 0 to disable and DCDC3_EN = 1 to enable the VDCDC3 converter Set DCDC2_EN = 0 to disable and DCDC2_EN = 1 to enable the VDCDC2 converter Set DCDC1_EN = 0 to disable and DCDC1_EN = 1 to enable the VDCDC1 converter The HOT_RESET pin generates a reset (RESPWRON) for the processor.HOT_RESET does not alter any TPS65020 settings except the output voltage of VDCDC3. Activating HOT_RESET sets the voltage of VDCDC3 to its default value defined with the DEFDCDC3 pin. A 1 M pull-up resistor to VCC is integrated in TPS65020. HOT_RESET is internally de-bounced by the TPS65020. RESPWRON is held low when power is initially applied to the TPS65020. The VRTC voltage is monitored: RESWPRON is low when VRTC < 2.4 V and remains low for a time defined by the external capacitor at the TRESPWRON pin. RESPWRON can also be forced low by activation of the HOT_RESET pin. Connect a capacitor here to define the RESET time at the RESPWRON pin. 1 nF typically gives 100 ms.
RESPWRON TRESPWRON
O I
SYSTEM RESET + CONTROL SIGNALS
The RESPWRON signal can be used as a global reset for the application. It is an open drain output. The RESPWRON signal is generated according to the power good comparator of VRTC, and remains low for tnrespwron seconds after VRTC has risen above 2.52 V (falling threshold is 2.4 V, 5% hysteresis). tnrespwron is set by an external capacitor at the TRESPWRON pin. 1 nF gives typically 100 ms. RESPWRON is also triggered by the HOT_RESET input. This input is internally debounced, with a filter time of typically 30 ms. The PWRFAIL and LOW_BAT signals are generated by two voltage detectors using the PWRFAIL_SNS and LOWBAT_SNS input signals. Each input signal is compared to a 1 V threshold (falling edge) with 5% (50 mV) hysteresis. The VDCDC3 converter is reset to its default output voltage defined by the DEFDCDC3 input, when HOT_RESET is asserted. Other I2C registers are not affected. Generally, the VDCDC3 converter is set to its default voltage with one of these conditions: HOT_RESET active, VRTC lower than its threshold voltage, undervoltage lockout (UVLO) condition, RESPWRON active, both VDCDC3-converter AND VDCDC1-converter disabled. In addition, the voltage of VDCDC3 changes to 1xxx0, if the VDCDC1 converter is disabled. Where xxx is the state before VDCDC1 was disabled. PB_IN and PB_OUT In the TPS65020 the PB_IN pin is defined as an input. It is active high and debounces the input signal. For example from a push button, before passing it to a latch associated with PB_OUT (active low). This feature allows the implementation of a push-button on-off-switch. PB_OUT is actively pulled low per default. See the application information section. Interrupt Management and the INT Pin The INT pin combines the outputs of the PGOOD comparators from each dc-dc converter and LDOs. The INT pin is used as a POWER_OK pin indicating when all enabled supplies are in regulation. If the PGOODZ register is read via the serial interface, any active bits are then blocked from the INT output pin. Interrupts can be masked using the MASK register; default operation is not to mask any interrupts since this gives the simple POWER_OK function.
24
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
TIMING DIAGRAMS
HOT_RESET
tDEGLITCH
RESPWRON
tNRESPWRON
VO DCDC3
any voltage set 2 with I C interface
default voltage
Figure 26. HOT_RESET Timing
2.47 V 2.35 V 1.9 V 1.2 V
VCC
1.9 V 0.8 V
UVLO*
VRTC
2.52 V 3V
2.4 V
RESPWRON tNRESPWRON ENDCDCx Ramp Within 800 ms
VODCDCx
1.8 V
slope depending on load ENLDO
VOLDOx
1.5 V
*... Internal Signal
Figure 27. Power-Up and Power-Down Timing
25
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
VCC
RESPWRON
T NRESPWRON
ENDCDC1
ENDCDC2
VODCDC1
3.3 V or 3 V Ramp Within 800 ms Ramp Within 800 ms
VODCDC2
2.5 V or 1.8 V Ramp Within 800 ms
DEFCORE register
Default Value
Set Higher Output Voltage for DCDC3
GO bit in CON_CTRL2 Cleared Automatically
Automatically Set to Default Value
ENDCDC3
VODCDC3
1.3 V or 1.55 V
1.3 V or 1.55 V
Ramp Within 800 ms
Programmed Slope Depending On Load Slew Rate
Ramp Within 800 ms
Figure 28. DVS Timing
26
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
VCC 0.8 V Threshold Depending on External Voltage Divider Connected to VCC
PWRFAIL
PB_IN (GPIO1)
tDEGLITCH tDEGLITCH tDEGLITCH
PB_OUT (GPIO2)
ON-OFF
Figure 29. PB-ON-OFF Timing
SERIAL INTERFACE
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to 400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as VCC remains above 2 V. The TPS65020 has a 7bit address: 1001000, other addresses are available upon contact with the factory. Attempting to read data from the register addresses not listed in this section results in FFh being read out. For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS65020 device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS65020 device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TPS65020 device must leave the data line high to enable the master to generate the stop condition
DATA
CLK Data Line Stable; Data Valid Change of Data Allowed
Figure 30. Bit Transfer on the Serial Interface
27
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
CE
DATA
CLK S START Condition P STOP Condition
Figure 31. START and STOP Conditions
SCLK
SDAT
A6
A5
A4
A0
R/W 0
AC K 0
R7
R6
R5
R0
AC K 0
D7
D6
D5
D0
AC K 0
Start
Slave Address
Register Address
Data
Stop
Note: SLAVE = TPS65020
Figure 32. Serial i/f WRITE to TPS65020 Device
SCLK
SDAT A6 A0 R/W 0 Start Slave Address
AC K 0
R7
R0
AC K 0
A6
A0
R/W 1
AC K 0
D7
D0
AC K
Register Address Repeated Start
Slave Address
Slave Drives the Data
Stop Master Drives ACK and Stop
Note: SLAVE = TPS65020
Figure 33. Serial i/f READ from TPS65020: Protocol A
28
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
SCLK
SDA A6 A0 R/W 0 Start Slave Address
AC K 0
R7
R0
AC K 0 Stop Start
A6
A0
R/W 1
AC K 0
D7
D0
AC K Stop Master Drives ACK and Stop
Register Address
Slave Address
Slave Drives the Data
Note: SLAVE = TPS65020
Figure 34. Serial i/f READ from TPS65020: Protocol B
DATA
t(BUF) t(LOW) tr tf
th(STA)
CLK
th(STA) t(HIGH) th(DATA) tsu(STA) tsu(DATA) tsu(STO)
STO
STA
STA
STO
Figure 35. Serial i/f Timing Diagram
MIN fMAX twH(HIGH) twL(LOW) tR tF th(STA) th(DATA) th(DATA) tsu(DATA) tsu(STO) t(BUF) Clock frequency Clock high time Clock low time DATA and CLK rise time DATA and CLK fall time Hold time (repeated) START condition (after this period the first clock pulse is generated) Setup time for repeated START condition Data input hold time Data input setup time STOP condition setup time Bus free time 600 600 0 100 600 1300 600 1300 300 300 MAX 400 UNIT kHz ns ns ns ns ns ns ns ns ns ns
VERSION. Register Address: 00h (read only)
VERSION Bit name and function Read/Write B7 0 R B6 0 R B5 0 R B4 1 R B3 0 R B2 0 R B1 0 R B0 0 R
29
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
PGOODZ. Register Address: 01h (read only)
PGOODZ Bit name and function Set by signal Default value loaded by: Read/Write B7 PWRFAILZ PWRFAIL PWRFAILZ R B6 LOWBATTZ LOWBATT LOWBATTZ R B5 PGOODZ VDCDC1 PGOODZ VDCDC1 PGOOD VDCDC1 R B4 PGOODZ VDCDC2 PGOODZ VDCDC2 PGOOD VDCDC2 R B3 PGOODZ VDCDC3 PGOODZ VDCDC3 PGOOD VDCDC3 R B2 PGOODZ LDO2 PGOODZ LDO2 PGOOD LDO2 R B1 PGOODZ LDO1 PGOODZ LDO1 PGOOD LDO1 R R B0
Bit 7
PWRFAILZ: 0= 1= indicates that the PWRFAIL_SNS input voltage is above the 1-V threshold. indicates that the PWRFAIL_SNS input voltage is below the 1-V threshold. indicates that the LOWBATT_SNS input voltage is above the 1-V threshold. indicates that the LOWBATT_SNS input voltage is below the 1-V threshold. indicates that the VDCDC1 converter output voltage is within its nominal range. This bit is zero if the VDCDC1 converter is disabled. indicates that the VDCDC1 converter output voltage is below its target regulation voltage indicates that the VDCDC2 converter output voltage is within its nominal range. This bit is zero if the VDCDC2 converter is disabled. indicates that the VDCDC2 converter output voltage is below its target regulation voltage indicates that the VDCDC3 converter output voltage is within its nominal range. This bit is zero if the VDCDC3 converter is disabled and during a DVM controlled output voltage transition indicates that the VDCDC3 converter output voltage is below its target regulation voltage indicates that the LDO2 output voltage is within its nominal range. This bit is zero if LDO2 is disabled. indicates that LDO2 output voltage is below its target regulation voltage indicates that the LDO1 output voltage is within its nominal range. This bit is zero if LDO1 is disabled. indicates that the LDO1 output voltage is below its target regulation voltage
Bit 6
LOWBATTZ: 0= 1=
Bit 5
PGOODZ VDCDC1: 0= 1=
Bit 4
PGOODZ VDCDC2: 0= 1=
Bit 3
PGOODZ VDCDC3: . 0= 1=
Bit 2
PGOODZ LDO2: 0= 1=
Bit 1
PGOODZ LDO1 0= 1=
30
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
The MASK register can be used to mask particular fault conditions from appearing at the INT pin. MASK = 1 masks PGOODZ. MASK. Register Address: 02h (read/write)
MASK Bit name and function Default Default value loaded by: Read/Write B7 MASK PWRFAILZ 1 UVLO R/W B6 MASK LOWBATTZ 1 UVLO R/W B5 MASK VDCDC1 0 UVLO R/W
Default Value: C0h
B4 MASK VDCDC2 0 UVLO R/W B3 MASK VDCDC3 0 UVLO R/W B2 MASK LDO2 0 UVLO R/W B1 MASK LDO1 0 UVLO R/W 0 UVLO R/W B0
The REG_CTRL register can be used to disable and enable all power supplies via the serial interface. Default is to allow all supplies to be on, providing the relevant enable pin is high. The following tables indicate how the enable pins and the REG_CTRL register are combined. The REG_CTRL bits are automatically reset to default when the corresponding enable pin is low. REG_CTRL. Register Address: 03h (read/write)
REG_CTRL Bit name and function Default Set by signal Default value loaded by: Read/Write 1 1 B7 B6 B5 VDCDC1 ENABLE 1
Default Value: FFh
B4 VDCDC2 ENABLE 1 B3 VDCDC3 ENABLE 1 B2 LDO2 ENABLE 1 LDO_ENZ UVLO R/W B1 LDO1 ENABLE 1 LDO_ENZ UVLO R/W DCDC2 CONVERTER disabled disabled enabled B0
DCDC1_ENZ DCDC2_ENZ DCDC3_ENZ UVLO R/W DCDC1 CONVERTER disabled disabled enabled DCDC3 CONVERTER disabled disabled enabled LDO_EN PIN 0 1 1 REG_CTRL<1> x 0 1 UVLO R/W UVLO R/W
DCDC1_EN PIN 0 1 1
REG_CTRL<5> x 0 1
DCDC2_EN PIN 0 1 1
REG_CTRL<4> x 0 1
DCDC3_EN PIN 0 1 1
REG_CTRL<3> x 0 1
LDO_EN PIN 0 1 1 LDO1
REG_CTRL<2> x 0 1
LDO2 disabled disabled enabled
disabled disabled enabled
31
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
The CON_CTRL register is used to force any or all of the converters into forced PWM operation, when low output voltage ripple is vital. It is also used to control the phase shift between the three converters in order to minimize the input rms current, hence reduce the required input blocking capacitance. The DCDC1 converter is taken as the reference and consequently has a fixed zero phase shift. CON_CTRL. Register Address: 04h (read/write)
CON_CTRL Bit name and function Default Default value loaded by: Read/Write B7 DCDC2 PHASE1 1 UVLO R/W B6 DCDC2 PHASE0 0 UVLO R/W B5 DCDC3 PHASE1 1 UVLO R/W
Default Value: B0h
B4 DCDC3 PHASE0 1 UVLO R/W B3 LOW RIPPLE 0 UVLO R/W B2 FPWM DCDC2 0 UVLO R/W B1 FPWM DCDC1 0 UVLO R/W B0 FPWM DCDC3 0 UVLO R/W
CON_CTRL<7:6> 00 01 10 11
DCDC2 CONVERTER DELAYED BY zero 1/4 cylce 1/2 cycle 3/4 cycle
CON_CTRL<5:4> 00 01 10 11
DCDC3 CONVERTER DELAYED BY zero 1/4 cylce 1/2 cycle 3/4 cycle
Bit 3
LOW RIPPLE: 0= 1= Skip mode operation optimized for high efficiency for all converters Skip mode operation optimized for low output voltage ripple for all converters DCDC2 converter operates in PWM / PFM mode DCDC2 converter is forced into fixed frequency PWM mode DCDC1 converter operates in PWM / PFM mode DCDC1 converter is forced into fixed frequency PWM mode DCDC3 converter operates in PWM / PFM mode DCDC3 converter is forced into fixed frequency PWM mode
Bit 2
FPWM DCDC2: 0= 1=
Bit 1
FPWM DCDC1: 0= 1=
Bit 0
FPWM DCDC3: 0= 1=
32
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
The CON_CTRL2 register can be used to take control the inductive converters. CON_CTRL. Register Address: 05h (read/write)
CON_CTRL2 Bit name and function Default Default value loaded by: Read/Write B7 GO 0 UVLO + DONE R/W B6 Core adj allowed 1 UVLO R/W 0 0 0 B5
Default Value: 40h
B4 B3 B2 DCDC2 discharge 0 UVLO R/W B1 DCDC1 discharge 0 UVLO R/W B0 DCDC3 discharge 0 UVLO R/W
Bit 7
GO: 0= 1= no change in the output voltage for the DCDC3 converter the output voltage of the DCDC3 converter is changed to the value defined in DEFCORE with the slew rate defined in DEFSLEW. This bit is automatically cleared when the DVM transition is complete. The transition is considered complete in this case when the desired output voltage code has been reached, not when the VDCDC3 output voltage is actually in regulation at the desired voltage. the output voltage is set with the I2C register DEFDCDC3 is either connected to GND or VCC or an external voltage divider. When connected to GND or VCC, VDCDC3 defaults to 1.3 V or 1.55 V respectively at start-up the output capacitor of the associated converter is not actively discharged when the converter is disabled the output capacitor of the associated converter is actively discharged when the converter is disabled. This decreases the fall time of the output voltage at light load
Bit 6
CORE ADJ Allowed: 0= 1=
Bit 2- 0
0= 1=
33
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
DEFCORE. Register Address: 06h (read/write
DEFCORE Bit name and function Default Default value loaded by: Read/Write 0 0 0 B7 B6 B5
Default Value: 14h/1Eh
B4 CORE4 1 RESET(1) R/W B3 CORE3 DEFDCDC3 RESET(1) R/W B2 CORE2 1 RESET(1) R/W B1 CORE1 DEFDCDC3 RESET(1) R/W B0 CORE0 0 RESET(1) R/W
RESET(1): DEFCORE is reset to its default value by one of these events: * undervoltage lockout (UVLO) * DCDC1 AND DCDC3 disabled * HOT_RESET pulled low * RESPWRON active * VRTC below threshold
CORE4 CORE3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CORE2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CORE1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CORE0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VDCDC3 0.8 V 0.825 V 0.85 V 0.875 V 0.9 V 0.925 V 0.95 V 0.975 V 1V 1.025 V 1.05 V 1.075 V 1.1 V 1.125 V 1.15 V 1.175 V CORE4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CORE3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CORE2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CORE1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CORE0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VDCDC3 1.2 V 1.225 V 1.25 V 1.275 V 1.3 V 1.325 V 1.35 V 1.375 V 1.4 V 1.425 V 1.45 V 1.475 V 1.5 V 1.525 V 1.55 V 1.6 V
DEFSLEW. Register Address: 07h (read/write)
DEFSLEW Bit name and function Default Default value loaded by: Read/Write SLEW2 0 0 0 0 1 1 1 1 SLEW1 0 0 1 1 0 0 1 1 B7 B6 B5
Default Value: 06h
B4 B3 B2 SLEW2 1 UVLO R/W SLEW0 0 1 0 1 0 1 0 1 VDCDC3 SLEW RATE 0.15 mV/s 0.3 mV/s 0.6 mV/s 1.2 mV/s 2.4 mV/s 4.8 mV/s 9.6 mV/s Immediate B1 SLEW1 1 UVLO R/W B0 SLEW0 0 UVLO R/W
34
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
LDO_CTRL. Register Address: 08h (read/write)
LDO_CTRL Bit name and function Default Default value loaded by: Read/Write B7 B6 LDO2_2 0 UVLO R/W B5 LDO2_1 1 UVLO R/W
Default Value: 23h
B4 LDO2_0 0 UVLO R/W B3 B2 LDO1_2 0 UVLO R/W B1 LDO1_1 1 UVLO R/W B0 LDO1_0 1 UVLO R/W
The LDO_CTRL registers can be used to set the output voltage of LDO1 and LDO2.
LDO1_2 0 0 0 0 1 1 1 1 LDO1_1 0 0 1 1 0 0 1 1 LDO1_0 0 1 0 1 0 1 0 1 LDO1 OUTPUT VOLTAGE 1V 1.05 V 1.1 V 1.3 V 1.8 V 2.5 V 3V 3.3 V LDO2_2 0 0 0 0 1 1 1 1 LDO2_1 0 0 1 1 0 0 1 1 LDO2_0 0 1 0 1 0 1 0 1 LDO2 OUTPUT VOLTAGE 1V 1.05 V 1.1 V 1.3 V 1.8 V 2.5 V 3V 3.3 V
DESIGN PROCEDURE
Inductor Selection for the DC-DC Converters Each of the converters in the TPS65020 typically use a 3.3 H output inductor. Larger or smaller inductor values are used to optimize the performance of the device for specific operation conditions. The selected inductor has to be rated for its dc resistance and saturation current. The dc resistance of the inductance influences directly the efficiency of the converter. Therefore, an inductor with lowest dc resistance should be selected for highest efficiency. For a fast transient response, a 2.2-H inductor in combination with a 22-F output capacitor is recommended. Equation 4 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 4. This is needed because during heavy load transient the inductor current rises above the value calculated under Equation 4. 1 * Vout Vin DI + Vout L L (4)
I Lmax * I outmax DI L 2
(5)
with: f = Switching Frequency (1.5 MHz typical) L = Inductor Value IL = Peak-to-Peak inductor ripple current ILMAX = Maximum Inductor current The highest inductor current occurs at maximum Vin. Open core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents versus a comparable shielded inductor. A more conservative approach is to select the inductor current rating just for the maximum switch current of the TPS65020 (2 A for the VDCDC1 and VDCDC2 converters, and 1.3 A for the VDCDC3 converter). The core material from inductor to inductor differs and has an impact on the efficiency especially at high switching frequencies.
35
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
See Table 3 and the typical applications for possible inductors. Table 3. Tested Inductors
DEVICE INDUCTOR VALUE 3.3 H 3.3 H DCDC3 converter 3.3 H 2.2 H 2.2 H 3.3 H DCDC2 converter 3.3 H 2.2 H 3.3 H DCDC1 converter 3.3 H 3.3 H 2.2 H TYPE CDRH2D14NP-3R3 LPS3010-332 VLF4012AT-3R3M1R3 VLF4012AT-2R2M1R5 NR3015T2R2 CDRH2D18/HPNP-3R3 VLF4012AT-3R3M1R3 VLCF4020-2R2 CDRH3D14/HPNP-3R2 CDRH4D28C-3R2 MSS5131-332 VLCF4020-2R2 COMPONENT SUPPLIER Sumida Coilcraft TDK TDK Taiyo-Yuden Sumida TDK TDK Sumida Sumida Coilcraft TDK
Output Capacitor Selection The advanced Fast Response voltage mode control scheme of the inductive converters implemented in the TPS65020 allow the use of small ceramic capacitors with a typical value of 10 F for a 3.3-H inductor for each converter without having large output voltage under and overshoots during heavy load transients. For a fast transient response a 22-F capacitor with a 2.2-H inductor should be used on each converter. Ceramic capacitors having low ESR values have the lowest output voltage ripple and are recommended. See Table 4 for recommended components. If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application requirements. Just for completeness, the RMS ripple current is calculated as: 1 * Vout Vin 1 I + RMSCout L 2 3 (6) At nominal load current, the inductive converters operate in PWM mode. The overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor: 1 + Vout Vin 1 I * ESR RMSCout L 8 Cout (7) Where the highest output voltage ripple occurs at the highest input voltage Vin. At light load currents, the converters operate in PSM and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage. Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. Each dc-dc converter requires a 10-F ceramic input capacitor on its input pin VINDCDCx. The input capacitor is increased without any limit for better input voltage filtering. The VCC pin is separated from the input for the dc-dc converters. A filter resistor of up to 10R and a 1-F capacitor is used for decoupling the VCC pin from switching noise. Note that the filter resistor may affect the UVLO threshold since up to 3 mA can flow via this resistor into the VCC pin when all converters are running in PWM mode.
36
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
Table 4. Possible Capacitors
CAPACITOR VALUE 22 F 22 F 10 F 10 F 22 F 22 F CASE SIZE 1206 1206 0805 0805 0805 0805 COMPONENT SUPPLIER TDK C3216X5R0J226M Taiyo Yuden JMK316BJ226ML Taiyo Yuden JMK212BJ106M TDK C2012X5R0J106M TDK C2012X5R0J226MT Taiyo Yuden JMK212BJ226MG COMMENTS Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic
Output Voltage Selection The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down converter. See the table for the default voltages if the pins are pulled to GND or to VCC. If a different voltage is needed, an external resistor divider can be added to the DEFDCDCx pin as shown in Table 5. The output voltage of VDCDC3 is set with the I2C interface. If the voltage is changed from the default, using the DEFCORE register, the output voltage only depends on the register value. Any resistor divider at DEFDCDC3 does not change the voltage set with the register. Bit B6 in the CON_CTRL2 register is used to switch between the internal voltage setting or the voltage set with the external DEFDCDC3 pin for the VDCDC3 converter. Table 5.
PIN DEFDCDC1 DEFDCDC2 DEFDCDC3 LEVEL VCC GND VCC GND VCC GND DEFAULT OUTPUT VOLTAGE 3.3 V 3V 2.5 V 1.8 V 1.55 V 1.3 V
Using an external resistor divider at DEFDCDCx:
10 R V(bat) 1 mF VINDCDC3 CI VCC VDCDC3 L3 L CO DCDC3_EN DEFDCDC3 R2 AGND PGND R1 VO
When a resistor divider is connected to DEFDCDCx, the output voltage can be set from 0.6 V up to the input voltage V(bat). The total resistance (R1+R2) of the voltage divider should be kept in the 1-MR range in order to maintain a high efficiency at light load. V(DEFDCDCx) = 0.6 V
37
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
V
OUT
V
DEFDCDC3
R1 * R2 R2
V R1 R2 V
OUT
DEFDCDC3
+ R2
(8)
VRTC Output The VRTC output is typically connected to the Vcc_Batt pin of a Intel PXA270 processor. During power-up of the processor, the TPS65020 internally switches from the LDO or the backup battery to the system voltage connected at the VSYSIN pin (see Figure 25). It is recommended to add a capacitor of 4.7-F minimum to the VRTC pin. LDO1 and LDO2 The LDOs default voltage is 1.1 V for LDO2 and 1.3 V for LDO1. They are intended to provide power to VCC_PLL and the VCC_SRAM pin on a PXA270 processor. The minimum output capacitor required is 2.2 F. The LDOs output voltage is changed to different voltages between 1 V and 3.3 V using the I2C interface. Therefore, they can also be used as general-purpose LDOs in applications powering processors different from PXA270. The supply voltage for the LDOs needs to be connected to the VINLDO pin, giving the flexibility to connect the lowest voltage available in the system, and providing the highest efficiency. Trespwron This is the input to a capacitor that defines the reset delay time after the voltage at VRTC rises above 2.52 V. The timing is generated by charging and discharging the capacitor with a current of 2 A between a threshold of 0.25 V and 1 V for 128 cycles. A 1-nF capacitor gives a delay time of 100 ms. Vcc-Filter An RC filter connected at the VCC input is used to keep noise from the internal supply for the bandgap and other analog circuitry. A typical value of 10R and 1 F is used to filter the switching spikes, generated by the dc-dc converters. A larger resistor than 10R should not be used because the current into VCC of up to 3 mA causes a voltage drop at the resistor causing the undervoltage lockout circuitry connected at VCC internally to switch off too early.
38
www.ti.com
TPS65020
SLVS607 - SEPTEMBER 2005
APPLICATION INFORMATION IMPLEMENTING A PUSH-BUTTON ON-OFF FUNCTION USING PB_IN AND PB_OUT
In mobile phone applications, usually the device must not automatically power up when the battery is inserted. Such a function can be implemented using PB_IN and PB_OUT. After the main battery is inserted, the PB_OUT open drain output is low. When this pins is connected with PWRFAIL, the signal is pulled low, preventing Intel PXA270 to start up.
VCC TPS65020 PWRFAIL_SNS LOWBAT_SNS 1V + PWRFAIL PXA270
+ VCC 1V PB_OUT nBatt_Fault
PB_IN Input buffer JK-flipflop
39
TPS65020
SLVS607 - SEPTEMBER 2005
www.ti.com
APPLICATION INFORMATION (continued) TYPICAL CONFIGURATION FOR THE Intel Bulverde PROCESSOR
VCC 10 R VCC 1 mF 10 mF 10 mF 10 mF VCC VINDCDC1 VINDCDC2 VINDCDC3 PWRFAIL LOW_BATT VR TC 4.7 mF DCDC2_EN DCDC1_EN VDCDC1 L1 VDCDC2 L2 LOWBAT_SNS VIN_LDO DCDC3_EN LDO_EN TRESPWRON 1 nF PB_IN PB_OUT VDCDC1 VCC VSYSIN DEFDCDC1 DEFDCDC2 DEFDCDC3 VBACKUP 3V Backup Battery VDCDC3 INT RESPWRON SCLK SDAT 4.7 kW VRTC 4.7 kW LDO1
2.2 mF
nBatt_Fault
Vcc_Batt SYS_EN
3V
Vcc_IO 2.2 mH Vcc_LCD 22 mF Vcc_BB Vcc_MEM
22 mF
3 V; 3.3 V 1.8 V; 2.5 V; 3 V; 3.3 V 1.8 V; 2.5 V; 3 V; 3.3 V 1.8 V; 2.5 V; 3 V; 3.3 V 1.8 V; 3 V
TPS65020
PWRFAIL_SNS
2.2 mH
Vcc_USIM
VCC
HOT_RESET
PWR_EN Vcc_PLL Vcc_SRAM
2.2 mF
1.3 V 1.1 V Variable 0.8 V to 1.6 V
LDO2 L3 2.2 mH
22 mF
Vcc_CORE
nVcc_Fault nRESET SCLK SDAT
40
PACKAGE OPTION ADDENDUM
www.ti.com
23-Sep-2005
PACKAGING INFORMATION
Orderable Device TPS65020RHAR TPS65020RHAT
(1)
Status (1) ACTIVE ACTIVE
Package Type QFN QFN
Package Drawing RHA RHA
Pins Package Eco Plan (2) Qty 40 40 2500 Green (RoHS & no Sb/Br) 250 Green (RoHS & no Sb/Br)
Lead/Ball Finish CU NIPDAU CU NIPDAU
MSL Peak Temp (3) Level-3-260C-168 HR Level-3-260C-168 HR
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless

▲Up To Search▲

Price & Availability of TPS65020

	To Download TPS65020 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .