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STV7697A
PLASMA DISPLAY PANEL SCAN DRIVER
. . . . . . . . . .
PRODUCT PREVIEW
64 OUTPUTS PLASMA DISPLAY DRIVER 170V ABSOLUTE MAXIMUM SUPPLY 5V SUPPLY FOR LOGIC 100/400mA SOURCE / SINK OUTPUT 700mA SOURCE / SINK OUTPUT DIODE 64-BIT SHIFT REGISTER (20MHz) BLANK CONTROL COMPLEMENTARY OUTPUT CONTROL BCD TECHNOLOGY 100 PINS PQFP PACKAGE OR DICE
PQFP100 (14 x 20 x 2.80mm) (Full Plastic Quad Flat Pack) ORDER CODE : STV7697A
DESCRIPTION The STV7697A is a scan driver for Plasma Display Panel (PDP) implemented in ST's proprietary BCD technology. Using a 64-bit cascadable 20MHz shift register, it drives 64 high current & high voltage outputs. By serialy connecting several STV7697A, any vertical pixel definition can be performed. The STV7697A is supplied with a separated 160V power output supply and a 5V logic supply. PIN CONNECTIONS
OUT35 OUT36 OUT37 OUT38 OUT39 OUT40 OUT41 OUT42 OUT43 OUT44 OUT45 OUT46 OUT47 OUT48 OUT49 OUT50 OUT51 OUT52 OUT53 OUT54 OUT55 OUT56 OUT57
All command inputs are CMOS compatible. The STV7697A package is a 100 pins PQFP.
OUT58
OUT59
OUT60
OUT61
OUT62
OUT63 2
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
OUT34 OUT33 VPP VSSP VSSP VSSP VPP VSSSUB VSSLOG VSSLOG VCC VSSLOG VSSSUB VPP VSSP VSSP VSSP VPP OUT32 OUT31
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
1
OUT64
100 99 98 97 96 95 94 93
VPP VSSP VSSP VPP NC NC VSSLOG CLK STB SOUT(SIN) VCC SIN(SOUT) NC F/R BLK POL VPP VSSP VSSP VPP
STV7697A
PQFP100
92 91 90 89 88 87 86 85 84 83 82 81
January 1999
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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7697A-01.EPS
OUT30
OUT29
OUT28
OUT27
OUT26
OUT25
OUT24
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
OUT17
OUT16
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
STV7697A
PIN ASSIGNMENT (PQFP100)
Pin Number 33-37-44-48-81-84-97-100 41-90 34-35-36-45-46-47-82-83-98-99 38-43 39-40-42-94 1 to 32, 49 to 80 91 85 86 87 89 92 93 88-95-96 Symbol VPP VCC VSSP VSSSUB VSSLOG OUT64 to OUT 1 SOUT (SIN) POL BLK F/R SIN (SOUT) STB CLK NC Type Supply Supply Ground Ground Ground Output Output Input Input Input Input Input Input 5V Logic Supply Ground of power outputs Substrate Ground Logic Ground Power Output Shift Register Data Output (forward) Polarity Selection Output Blanking Command Selection of shift direction Shift Register Data Input (forward) Clock of data shift register
7697A-01.TBL
Function High Voltage Supply of power outputs
Latch of data to outputs
PIN ASSIGNMENT (Power Outputs)
Output N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin N 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 Output N 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin N 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Output N 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin N 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Output N 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin N 16 15 14 13 12 11 10 9 8 7 6 5 4 2 1
7697A-02.TBL
3
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STV7697A
BLOCK DIAGRAM
VCC CLK 93 SIN (SOUT) 89
P1
64-BIT SHIFT REGISTER
P64
87 F/R 91 SOUT (SIN) VSSSUB Pins 38-43 VSSLOG Pins 39-40-42-94 VCC Pins 41-90 VSSP Pins 34-35-36-45-46 47-82-83-98-99 VPP Pins 33-37-44-48 81-84-97-100
S1
S64
STB 92
Q1 Q2
LATCH
Q63Q64
VCC BLK 86 VCC POL 85
80 OUT1
1 OUT64
CIRCUIT DESCRIPTION The STV7697A contains all the logic and the power circuits necessary to drive rows of a Plasma Display Panel (P. D. P.). The state of the displayed line is loaded into the shift register. Data are shifted at each low to high transition of the (CLK) shift clock. After 64 shifts the first bit is available at the serial output. This output can be used to cascade several drivers to perform any vertical resolution. The forward/reverse (F/R) input is used to select the direction of the shift register, data input/output status is set according to the selected direction. SIN, CLK, STB inputs are Smith trigger inputs . If not used on the application, F/R, BLK, POL logical inputs are internaly pulled to level "1". The maximum frequency of the shift clock is 20MHz. All the the data are memorized into the latch stage when the strobe input (STB) is pulled high. Blanking input (BLK) forces the power outputs to high level when pulled high with polarity input (POL) Power Output Truth Table
Qn (1) X X H L H L X X STB X X L L L L H H BLK H H L L L L L L POL H L L L H H L H Driver Output All H All L H L L H Qn Qn Comments Forced to High Forced to Low Copy Data Copy Data Copy Inverted Data Copy Inverted Data Data Latched Inverted Data Latched
at high level and forced to low level with POL at low level. The level of the power output is inverted when the polarity command (POL) is pulled high. Sustain current must not be sunk in the power output to VPP when the power supply is applied. VSSLOG and VSSSUB must be connected as close as possible to the logical reference ground of the application. Shift Register Truth Table
Input F/R H H L L CLK Rise H or L Rise H or L Input/Output SIN IN IN OUT OUT SOUT OUT OUT IN IN Shift Register Function Output Q Forward shift Steady Reverse Shift Steady
Note : 1. Qn is the parallel output of the shift register (n = 1 to 64). Qn takes the value of serial input (SIN) after "n" shift clock periods.
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7697A-02.EPS
STV7697A
VSSP
VPP
VSSP
VPP
STV7697A
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VPP VIN VOUT VPOUT IPOUT IDOUT Toper Tj Tstg Parameter Logic Supply Range Driver Supply Range Logic Input Voltage Range Logic Output Voltage Range Driver Output Voltage Range Driver Output Current (2)(4) Diode Output Current (3)(4) Operating Temperature Junction Temperature (1) Storage Temperature Value -0.3, +7 -0.3, +170 -0.3, VCC + 0.3 -0.3, VCC + 0.3 -0.3, VPP +100/-400 700 -20, +85 +125 -50, +150 Unit V V V V V mA mA C C C
THERMAL DATA
Max.
7697A-04.TBL 7697A-05.TBL
Symbol Rth(j-a) Poper
Notes : 1. 2. 3. 4.
Parameter Junction-ambient Thermal Resistance (1) Maximum Operating Power Dissipation (Tamb = 25C)
Value 50 2
Unit C/W W
For PQFP100 packaging. Through one power output. Through one power output with VPP = VSSP (see test diagram). These parameters are measured during ST's internal qualification which includes temperature characterisation on standard batc hes and on corners batches of the process. These parameters are not tested on the parts.
ELECTRICAL CHARACTERISTICS (VCC = 5V, VPP = 130V, VSSP = 0V, VSSLOG = VSSSUB = 0V, Tamb = 25C, fCLK = 20MHz, unless otherwise specified)
Symbol SUPPLY VCC ICCH ICCL VPP IPPH OUTPUT OUT1-OUT64 VPOUTH VPOUTL VDOUTH VDOUTL SOUT VOH VOL Logic Output High Level Logic Output Low Level IOH = 1mA IOL = -1mA 4 0.4 V V Power Output High Level Power Output Low Level Output Diode High Level Output Diode Low Level IPOUTH = - 10mA IPOUTH = -40mA IPOUTL = 200mA IDOUTH = +400mA (5) IDOUTL = -400mA (5) 120 TBD 125 3.1 2.3 2.2 10 10 10 V V V V V Logic Supply Voltage Logic Supply Current (all inputs high) Logic Supply Current Power Output Supply Voltage Power Output Supply Current (steady outputs) fCLK = 8MHz, SIN =1010 4.5 TBD 5 5.3 5.5 10 TBD 160 100 V A mA V A Parameter Test Conditions Min. Typ. Max. Unit
INPUT (CLK, F/R, STB, POL, BLK, SIN) VIH VIL IIH IIL Input High Level Input Low Level High Level Input Current Low Level Input Current CLK, SIN, STB F/R, BLK, POL VIH = VCC VIL = 0V 0.8 VCC 70 0.2 VCC 10 10 100 V V A A A
Notes : 5. Compatible with power dissipation (see test diagram).
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7697A-03.TBL
STV7697A
AC TIMINGS REQUIREMENTS (VCC = 4.5V to 5.5V, Tamb = -20 to +85C, input signals max leading edge & trailing edge (tR, tF) = 10ns)
Symbol tCLK tWHCLK tWLCLK tSDAT tHDAT tSFR tDSTB tSTB tBLK tPOL Data Clock Period Duration of clock (CLK) pulse at high level Duration of clock (CLK) pulse at low level Set-up Time of data input before clock low to high transition Hold Time of data input after clock low to high transition Forward/Reverse(F/R) set up time before low to high clock transition Minimum Delay to latch (STB) after clock low to high transition Strobe (STB) Pulse Duration Blank (BLK) Pulse Duration Polarity (POL) Pulse Duration Parameter Min. 50 15 15 10 10 100 10 20 500 500 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns
7697A-06.TBL
AC TIMING CHARACTERISTICS (VCC = 5V, VPP = 130V, VSSP = 0V, VSSLOG = VSSSUB = 0V, Tamb = 25C, fCLK = 20MHz, VILMax. = 0.2VCC, VIHMin. = 0.8VCC, VOH = 4.0V, VOL = 0.4V, CL = 15pF, unless otherwise specified)
Symbol tCLK tRDAT tFDAT tPHL1 tPLH1 tPHL2 tPLH2 tPHL3 tPLH3 tPHL4 tPLH4 tROUT tFOUT Data Clock Period Logical Data Output Rise Time Logical Data Output Fall Time Delay of logic data output after clock (CLK) high to low transition Delay of logic data output after clock (CLK) low to high transition Delay of power output change after clock (CLK) high to low transition Delay of power output change after clock (CLK) low to high transition Delay of power output change after blanking (BLK) high to low transition Delay of power output change after blanking (BLK) low to high transition Delay of power output change after polarity (POL) high to low transition Delay of power output change after polarity (POL) low to high transition Power Output Rise Time (6) Power Output Fall Time (6) Parameter Min. 50 Typ. 20 11 45 48 120 120 110 110 100 60 Max. 180 180 165 165 160 160 200 200 Unit ns ns ns ns ns ns ns ns ns
7697A-07.TBL
ns ns ns ns
Notes : 6. One output among 64, loading capacitor COUT = 100pF, other outputs at low level.
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STV7697A
Figure 1 : AC Characteristics Waveform
tCLK tWLCLK tWHCLK "1" CLK 50% 50% tSDAT 50% "0" tHDAT "1" SIN 50% tPLH1 "1" 50% "0" tRDAT STB 50% tSFR "1" F/R 50% "0" tPHL2 "1" OUTn 90% 10% tPLH2 tBLK "1" BLK 50% tPLH3 50% "0" tPHL3 90% OUTn 10% "0" tPOL "1" POL tROUT 90% 10% 90% 10% tFOUT 50% tPHL4 90% 10% 50% "0" tPLH4 "1"
7697A-03.EPS
50% "0"
tFDAT SOUT 10% 10% 90% 90%
tSTB tDSTB 50% "0" "1"
"0"
"1"
OUTn
"0"
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STV7697A
Figure 2 : Test Configuration
VPP VDOUTH OUTI IDOUTL
VPP OUTI VDOUTL IDOUTL
VSSP
VSSP
7697A-04.EPS
Output sinking current as positive value, sourcing current as negative value
INPUT/OUTPUT SCHEMATICS Figure 3 : F/R, BLK, POL, HIZ
VCC (Pins 41, 90)
Figure 4 : CLK, STB
VCC (Pins 41, 90)
F/R, BLK, POL (Pins 87, 86, 85)
CLK, STB (Pins 93, 92)
7697A-05.EPS
VSSSUB (Pins 38, 43)
VSSLOG (Pins 39, 40, 42, 94)
Figure 5 : SIN, SOUT
VCC (Pins 41, 90)
Figure 6 : Power Output
VPP (Pins 33, 37, 44, 48, 81, 84, 97, 100)
SIN, SOUT (Pins 89, 91)
OUTi (Pins 1 to 32, 49 to 80)
VSSSUB (Pins 38, 43) VSSLOG (Pins 39, 40, 42, 94)
7697A-07.EPS 7697A-08.EPS
VSSLOG (Pins 39, 40, 42, 94)
VSSP (Pins 34, 35, 36, 45, 46, 47, 82, 83, 98, 99)
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7697A-06.EPS
VSSSUB (Pins 38, 43)
VSSLOG (Pins 39, 40, 42, 94)
STV7697A
PACKAGE MECHANICAL DATA 100 PINS - PLASTIC QUAD FLAT PACK (PQFP100)
A A2 80 e A1 51 0,10 mm .004 inch SEATING PLANE 50
81
100
31
E3 E1 E
B
1
D3 D1 D
30
c
L1
L
K
Dimensions A A1 A2 B c D D1 D3 e E E1 E3 L L1 K
Min. 0.25 2.55 0.22 0.13 22.95 19.90
Millimeters Typ.
Max. 3.40 3.05 0.38 0.23 23.45 20.10
Min. 0.010 0.100 0.0087 0.005 0.903 0.783
Inches Typ.
Max. 0.134 0.120 0.015 0.009 0.923 0.791
2.80
0.110
16.95 13.90 0.65
0o (Min.), 7o (Max.)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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5F.TBL
23.20 20.00 18.85 0.65 17.20 14.00 12.35 0.80 1.60
17.45 14.10 0.95
0.667 0.547 0.026
0.913 0.787 0.742 0.026 0.677 0.551 0.486 0.031 0.063
0.687 0.555 0.037
PM-5F.EPS

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