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XC2C32 CoolRunner-II CPLD
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DS091 (v2.7) November 8, 2004
Preliminary Product Specification
Note: This product is no longer recommended for new designs. It has been superseded by the XC2C32A, a device with I/O Banking and Pb-free package options.
Description
The CoolRunner-II 32-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved This device consists of two Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. The CoolRunner-II 32-macrocell CPLD is I/O compatible with standard LVTTL and LVCMOS18, LVCMOS25, and LVCMOS33 (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.
Features
* Optimized for 1.8V systems - As fast as 3.0 ns pin-to-pin logic delays - As low as 12 A quiescent current Industries best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation: 1.5V through 3.3V Available in multiple package options - 44-pin PLCC with 33 user I/O - 44-pin VQFP with 33 user I/O - 56-ball CP BGA with 33 user I/O Advanced system features - Fastest in system programming * 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - RealDigital 100% CMOS product term generation - Flexible clocking modes - Optional DualEDGE triggered registers - Global signal options with macrocell control * Multiple global clocks with phase selection per macrocell * Multiple global output enables * Global set/reset - Efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks - Advanced design security - Open-drain output option for Wired-OR and LED drive - Optional configurable grounds on unused I/Os - Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels - PLA architecture * Superior pinout retention * 100% product term routability across function block - Hot pluggable
*
*
*
Refer to the CoolRunnerTM-II family data sheet for architecture description.
(c) 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS091 (v2.7) November 8, 2004 Preliminary Product Specification
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XC2C32 CoolRunner-II CPLD
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RealDigital Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. CoolRunner-II CPLDs employ RealDigital, a design technique that makes use of CMOS technology in both the fabrication and design methodology. RealDigital design technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this technology, Xilinx CoolRunner-II CPLDs achieve both high performance and low power operation.
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs. Table 1: I/O Standards for XC2C32 Output VCCIO 3.3 3.3 2.5 1.8 1.5 Input VCCIO 3.3 3.3 2.5 1.8 1.5 Input VREF N/A N/A N/A N/A N/A Board Terminatio nVoltage VT N/A N/A N/A N/A N/A
I/O Types LVTTL LVCMOS33 LVCMOS25 LVCMOS18 1.5V I/O
Supported I/O Standards
The CoolRunner-II 32 macrocell features both LVCMOS and LVTTL I/O implementations. See Table 1 for I/O standard voltages. The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The
20
15 -3
ICC (mA)
10 -4, -6 5
0 0 50 100 150 200 250 300
DS091_01_042303
350
400
Frequency (MHz)
Figure 1: ICC vs Frequency Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25C)(1) Frequency (MHz) 0 Typical -3 ICC (mA) Typical -4, -6 ICC (mA) 0.03 0.016 25 0.98 0.87 50 1.92 1.75 75 2.90 2.61 100 3.82 3.44 150 5.68 5.16 175 6.65 5.99 200 7.54 6.81 225 8.41 7.63 250 9.35 8.36 300 11.16 9.93 350 12.97 385 14.09 -
Notes: 1. 16-bit up/down, resettable binary counter (one counter per function block).
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DS091 (v2.7) November 8, 2004 Preliminary Product Specification
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XC2C32 CoolRunner-II CPLD
Absolute Maximum Ratings
Symbol VCC VCCIO VJTAG VIN
(2)
Description Supply voltage relative to ground Supply voltage for output drivers JTAG input voltage limits JTAG input supply voltage Input voltage relative to ground Voltage applied to 3-state output Storage Temperature (ambient) Junction Temperature
Value -0.5 to 2.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -65 to +150 +150
Units V V V V V V C C
VAUX
(1)
VTS(1) TSTG(3) TJ
Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions, the device pins may undershoot to -2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Valid over commercial temperature range. 3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free packages, see XAPP427.
Recommended Operating Conditions
Symbol VCC VCCIO Parameter Supply voltage for internal logic and input buffers Commercial TA = 0C to +70C Industrial TA = -40C to +85C Min 1.7 1.7 3.0 2.3 1.7 1.4 1.7 Max 1.9 1.9 3.6 2.7 1.9 1.6 3.6 Units V V V V V V V
Supply voltage for output drivers @ 3.3V operation Supply voltage for output drivers @ 2.5V operation Supply voltage for output drivers @ 1.8V operation Supply voltage for output drivers @ 1.5V operation
VAUX
JTAG programming pins
DC Electrical Characteristics (Over Recommended Operating Conditions)
Symbol ICCSB ICCSB ICCSB ICC (1) ICC
(1)
Parameter Standby current (-3) Standby current (-4, -6) Standby current ( -6 industrial) Dynamic current (-3) Dynamic current (-4, -6) JTAG input capacitance Global clock input capacitance I/O capacitance Input leakage current I/O High-Z leakage
Test Conditions VCC = 1.9V, VCCIO = 3.6V VCC = 1.9V, VCCIO = 3.6V VCC = 1.9V, VCCIO = 3.6V f = 1 MHz f = 50 MHz f = 1 MHz f = 50 MHz f = 1 MHz f = 1 MHz f = 1 MHz VIN = 0V or VCCIO to 3.9V VIN = 0V or VCCIO to 3.9V
Typical 150 22 38 -1 -1
Max. 1000 50 80 1.2 4.0 0.25 2.5 10 12 10 1 1
Units A A A mA mA mA mA pF pF pF A A
CJTAG CCLK CIO IIL
(2)
IIH(2)
Notes: 1. 16-bit up/down resettable binary counter (one per Function Block) tested at VCC = VCCIO = 1.9V. 2. See Quality and Reliability section of the CoolRunner-II family data sheet.
DS091 (v2.7) November 8, 2004 Preliminary Product Specification
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LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH VOL Parameter Input source voltage High level input voltage Low level input voltage High level output voltage Low level output voltage IOH = -8 mA, VCCIO = 3V IOH = -0.1 mA, VCCIO = 3V IOL = 8 mA, VCCIO = 3V IOL = 0.1 mA, VCCIO = 3V Test Conditions Min. 3.0 2 -0.3 VCCIO - 0.4V VCCIO - 0.2V Max. 3.6 3.9 0.8 0.4 0.2 Units V V V V V V V
LVCMOS 2.5V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH VOL Parameter Input source voltage High level input voltage Low level input voltage High level output voltage Low level output voltage IOH = -8 mA, VCCIO = 2.3V IOH = -0.1 mA, VCCIO = 2.3V IOL = 8 mA, VCCIO = 2.3V IOL = 0.1mA, VCCIO = 2.3V Test Conditions Min. 2.3 1.7 -0.3 VCCIO - 0.4V VCCIO - 0.2V Max. 2.7 3.9 0.7 0.4 0.2 Units V V V V V V V
LVCMOS 1.8V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH VOL Parameter Input source voltage High level input voltage Low level input voltage High level output voltage Low level output voltage IOH = -8 mA, VCCIO = 1.7V IOH = -0.1 mA, VCCIO = 1.7V IOL = 8 mA, VCCIO = 1.7V IOL = 0.1 mA, VCCIO = 1.7V Test Conditions Min. 1.7 0.65 x VCCIO -0.3 VCCIO - 0.45 VCCIO - 0.2 Max. 1.9 3.9 0.35 x VCCIO 0.45 0.2 Units V V V V V V V
1.5V DC Voltage Specifications(1)
Symbol VCCIO VT+ VTVOH VOL High level output voltage Low level output voltage IOH = -8 mA, VCCIO = 1.4V IOH = -0.1 mA, VCCIO = 1.4V IOL = 8 mA, VCCIO = 1.4V IOL = 0.1 mA, VCCIO = 1.4V
Notes: 1. Hysteresis used on 1.5V inputs.
Parameter Input source voltage Input hysteresis threshold voltage
Test Conditions
Min. 1.4 0.5 x VCCIO 0.2 x VCCIO VCCIO - 0.45 VCCIO - 0.2 -
Max. 1.6 0.8 x VCCIO 0.5 x VCCIO 0.4 0.2
Units V V V V V V V
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DS091 (v2.7) November 8, 2004 Preliminary Product Specification
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XC2C32 CoolRunner-II CPLD
Schmitt Trigger Input DC Voltage Specifications
Symbol VCCIO VT+ VTParameter Input source voltage Input hysteresis threshold voltage Test Conditions Min. 1.4 0.5 x VCCIO 0.2 x VCCIO Max. 3.9 0.8 x VCCIO 0.5 x VCCIO Units V V V
AC Electrical Characteristics Over Recommended Operating Conditions
-3 Symbol TPD1 TPD2 TSUD TSU1 TSU2 THD TH TCO FTOGGLE
(1)
-4 Max. 2.8 3.0 2.8 500 417 385 233 222 3.7 4.0 5.3 4.8 4.9 4.0 50 Min. 1.7 1.9 2.1 0.0 0.0 0.4 0.6 0.8 1.5 1.3 2.0 0.0 1.4 4.0 4.0 Max. 3.8 4.0 3.7 450 323 303 179 172 5.0 4.2 5.5 5.0 5.5 4.5 50 Min. 2.2 2.6 3.1 0.0 0.0 0.9 1.3 1.8 1.6 1.2 3.0 0.0 2.2 6.0 6.0 -
-6 Max . 5.5 6.0 4.7 300 200 182 137 128 6.0 5.5 6.7 6.9 6.8 5.5 50 Unit s ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
Parameter Propagation delay single p-term Propagation delay OR array Direct input register clock setup time Setup time fast (single p-term) Setup time (OR array) Direct input register hold time P-term hold time Clock to output Internal toggle rate Maximum system frequency Maximum system frequency Maximum external frequency Maximum external frequency Direct input register p-term clock setup time P-term clock setup time (single p-term) P-term clock setup time (OR array) Direct input register p-term clock hold time P-term clock hold P-term clock to output Global OE to output enable/disable P-term OE to output enable/disable Macrocell driven OE to output enable/disable P-term set/reset to output valid Global set/reset to output valid Register clock enable setup time Register clock enable hold time Global clock pulse width High or Low P-term pulse width High or Low Asynchronous preset/reset pulse width (High or Low) Configuration time
Min. 1.5 1.5 1.7 0.0 0.0 0.6 0.6 0.8 0.9 0.9 1.8 0.0 0.9 3.0 3.0 -
FSYSTEM1(2) FSYSTEM2 FEXT1 FEXT2
(3) (3) (2)
TPSUD TPSU1 TPSU2 TPHD TPH TPCO TOE/TOD TPOE/TPOD TMOE/TMOD TPAO TAO TSUEC THEC TCW TPCW TAPRPW TCONFIG(4)
Notes: 1. FTOGGLE is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet). 2. FSYSTEM1 (1/TCYCLE) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per macrocell while FSYSTEM2 is through the OR array. 3. FEXT1 (1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array. 4. Typical configuration current during TCONFIG is 500 A.
DS091 (v2.7) November 8, 2004 Preliminary Product Specification
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Internal Timing Parameters
-3 Symbol Buffer Delays TIN Input buffer delay TDIN TGCK TGSR TGTS TOUT Parameter(1) Min. 1.5 0.0 0.9 0.0 Max. 0.8 1.2 1.2 1.2 0.8 1.4 3.2 1.3 0.4 0.2 0.2 1.0 0.2 1.4 0.3 0.2 2.5 0.5 3.0 2.0 0.0 3.0 Min. 1.5 0.0 0.7 0.0 -4 Max. 1.3 1.5 1.3 1.6 1.3 1.8 2.9 1.3 0.4 0.2 0.3 1.5 0.6 1.1 0.6 0.2 3.0 0.8 4.0 3.0 0.0 4.0 Min. 1.8 0.0 1.7 0.0 -6 Max. 1.7 2.4 2.0 2.0 2.1 2.0 3.4 1.6 1.1 0.5 0.7 2.5 0.7 1.5 1.4 0.8 4.0 1.0 5.0 4.0 0.0 5.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Direct register input delay Global Clock buffer delay Global set/reset buffer delay Global 3-state buffer delay Output buffer delay
TEN Output buffer enable/disable delay P-term Delays TCT Control term delay TLOGI1 Single p-term delay adder TLOGI2 Multiple p-term delay adder Macrocell Delay TPDI Input to output valid TLDI TSUI THI TECSU TECHO TCOI Setup before clock (transparent latch) Setup before clock Hold after clock Enable clock setup time Enable clock hold time Clock to output valid
TAOI Set/reset to output valid Feedback Delays TF Feedback delay TOEM Macrocell to global OE delay I/O Standard Time Adder Delays 1.5V I/O THYS15 Hysteresis input adder TOUT15 Output adder TSLEW15 Output slew rate adder I/O Standard Time Adder Delays 1.8V CMOS THYS18 Hysteresis input adder TOUT18 TSLEW Output adder Output slew rate adder
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XC2C32 CoolRunner-II CPLD
Internal Timing Parameters (Continued)
-3 Symbol TIN25 THYS25 TOUT25 Parameter(1) Standard input adder Hysteresis input adder Output adder Min. Max. 0.7 2.5 0.8 4.0 0.7 2.5 1.2 4.0 Min. I/O Standard Time Adder Delays 2.5V CMOS
-4 Max. 0.8 3.0 1.0 5.0 0.8 3.0 1.5 5.0 Min. -
-6 Max. 1.0 4.0 2.0 7.0 1.0 4.0 2.5 7.0 Units ns ns ns ns ns ns ns ns
TSLEW25 Output slew rate adder I/O Standard Time Adder Delays 3.3V CMOS/TTL TIN33 Standard input adder THYS33 TOUT33 TSLEW33 Hysteresis input adder Output adder Output slew rate adder
Notes: 1. 1.5 ns input pin signal rise/fall.
Switching Characteristics
VCC = VCCIO = 1.8V @ 25oC
5.5
AC Test Circuit
VCC R1
5.0
Device Under Test R2 CL
Test Point
4.5
TPD2 (ns)
4.0
Output Type
3.5
R1 268 275 188 112.5 150
R2 235 275 188 112.5 150
CL 35 pF 35 pF 35pF 35pF 35pF
LVTTL33 LVCMOS33 LVCMOS25
1 2 4 8 16
3.0
LVCMOS18 LVCMOS15
Number of Outputs Switching
DS091_02_112002
CL includes test fixtures and probe capacitance. 1.5 nsec maximum rise/fall times on inputs.
DS_ACT_08_14_02
Figure 2: Derating Curve for TPD
Figure 3: AC Load Circuit
DS091 (v2.7) November 8, 2004 Preliminary Product Specification
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XC2C32 CoolRunner-II CPLD
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Typical I/O Output Curves
3.3V
60
50
IO (Output Current mA)
40 1.8V 30
2.5V
Iol
20 1.5V 10
0 0 .5 1.0 1.5 2.0 2.5 3.0 3.5
VO (Output Volts)
XC32_VoIo_all_0403
Figure 4: Typical I/V Curve for XC2C32
Pin Descriptions
Function Block 1 1 1 1(GTS1) 1(GTS0) 1(GTS3) 1(GTS2) 1(GSR) 1 1 1 1 1 1 1 1 2 2 2 2 2(GCK0) 2(GCK1) 2(GCK2) Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 PC44 44 43 42 40 39 38 37 36 35 34 33 29 28 27 26 25 1 2 3 4 5 6 7 VQ44 38 37 36 34 33 32 31 30 29 28 27 23 22 21 20 19 39 40 41 42 43 44 1 CP56 F1 E3 E1 D1 C1 A3 A2 B1 A1 C4 C5 C8 A10 B10 C10 E8 G1 F3 H1 G3 J1 K1 K2
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XC2C32 CoolRunner-II CPLD
Pin Descriptions (Continued)
Function Block 2 2 2 2 2 2 2 2 2 Macrocell 8 9 10 11 12 13 14 15 16 PC44 8 9 11 12 14 18 19 20 22 VQ44 2 3 5 6 8 12 13 14 16 CP56 K3 H3 K5 H5 H8 K8 H10 G10 F10
Notes: 1. GTS = global output enable, GSR = global set reset, GCK = global clock
XC2C32 Global, JTAG, Power/Ground and No Connect Pins
Pin Type TCK TDI TDO TMS Input Only VAUX (JTAG supply voltage) Power internal (VCC) Power external I/O (VCCIO) Ground No connects PC44(1) 17 15 30 16 24 41 21 13, 32 10,23,31 VQ44(1) 11 9 24 10 18 35 15 7,26 4,17,25 CP56(1) K10 J10 A6 K9 D10 D3 G8 H6, C6 H4, F8, C7 K4, K6, K7, H7, E10, A7, A9, D8, A5, A8, A4, C3 33
Total user I/O (includes dual function pins)
33
33
Notes: 1. All packages pin compatible with larger macrocell densities
DS091 (v2.7) November 8, 2004 Preliminary Product Specification
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Ordering Information
Part Number XC2C32-3PC44C XC2C32-4PC44C XC2C32-6PC44C XC2C32-3VQ44C XC2C32-4VQ44C XC2C32-6VQ44C XC2C32-3CP56C XC2C32-4CP56C XC2C32-6CP56C XC2C32-6PC44I XC2C32-6VQ44I XC2C32-6CP56I Pin/Ball Spacing 1.27mm 1.27mm 1.27mm 0.8mm 0.8mm 0.8mm 0.5mm 0.5mm 0.5mm 1.27mm 0.8mm 0.5mm JA (C/Watt) 55.1 55.1 55.1 47.7 47.7 47.7 66.0 66.0 66.0 55.1 47.7 66.0 JC (C/Watt) 35.3 35.3 35.3 8.2 8.2 8.2 14.9 14.9 14.9 35.3 8.2 14.9 Package Type Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Very Thin Quad Flat Pack Very Thin Quad Flat Pack Very Thin Quad Flat Pack Chip Scale Package Chip Scale Package Chip Scale Package Plastic Leaded Chip Carrier Very Thin Quad Flat Pack Chip Scale Package Package Body Dimensions 16.5mm x 16.5mm 16.5mm x 16.5mm 16.5mm x 16.5mm 10mm x 10mm 10mm x 10mm 10mm x 10mm 6mm x 6mm 6mm x 6mm 6mm x 6mm 16.5mm x 16.5mm 10mm x 10mm 6mm x 6mm Comm. (C) I/O 33 33 33 33 33 33 33 33 33 33 33 33 Ind. (I)(1) C C C C C C C C C I I I
Notes: 1. C = Commercial (TA = 0C to +70C); I = Industrial (TA = -40C to +85C)
Standard Example: XC2C128 Device Speed Grade Package Type Number of Pins Temperature Range
-4 TQ
144
C
Pb-Free Example: XC2C128 Device Speed Grade Package Type Pb-Free Number of Pins Temperature Range
-4 TQ
G
144
C
Device Part Marking
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Device Type Package Speed Operating Range
XC2Cxxx TQ144 7C
This line not related to device part number
Part marking for non-chip scale package
Figure 5: Sample Package with Part Marking
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XC2C32 CoolRunner-II CPLD
Note: Due to the small size of chip scale packages, the complete ordering part number cannot be included on the package marking. Part marking on chip scale packages by line are: * * * * Line 1 = X (Xilinx logo) then truncated part number Line 2 = Not related to device part number Line 3 = Not related to device part number Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package codes: C3 = CP56, C4 = CPG56.
I/O(2) I/O(2) I/O I/O I/O I/O I/O I/O I/O VAUX I/O(1)
I/O(2) I/O(2) I/O I/O I/O I/O I/O I/O I/O VAUX I/O(1)
6 5 4 3 2 1 44 43 42 41 40
I/O(2) I/O I/O GND I/O I/O VCCIO I/O TDI TMS TCK
12 13 14 15 16 17 18 19 20 21 22
1 2 3 4 5 6 7 8 9 10 11
DS091 (v2.7) November 8, 2004 Preliminary Product Specification
I/O I/O I/O VCC I/O GND I I/O I/O I/O I/O
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset
Figure 6: VQ44 Package
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I/O I/O I/O VCC I/O GND I I/O I/O I/O I/O
VQ44 Top View
33 32 31 30 29 28 27 26 25 24 23
I/O(1) I/O(1) I/O(1) I/O(3) I/O I/O I/O VCCIO GND TDO I/O
18 19 20 21 22 23 24 25 26 27 28
I/O(2) I/O I/O GND I/O I/O VCCIO I/O TDI TMS TCK
7 8 9 10 11 12 13 14 15 16 17
PC44 Top View
39 38 37 36 35 34 33 32 31 30 29
I/O(1) I/O(1) I/O(1) I/O(3) I/O I/O I/O VCCIO Gnd TDO I/O
44 43 42 41 40 39 38 37 36 35 34
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset
Figure 7: PC44 Package
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XC2C32 CoolRunner-II CPLD
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K J H G F E D C B A
I/O(2) I/O(2)
I/O(2)
I/O
NC
I/O
NC
NC
I/O
TMS
TCK
TDI VCC IO
I/O
I/O
GND
I/O
NC
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
CP56 Bottom View
GND
I/O
I/O I/O(1) I/O(1) I/O(3) I/O(1)
I/O
I/O
NC
VAUX NC I/O I/O VCC IO GND
NC
I/O
I/O
I/O I/O(1)
I/O
NC
NC
TDO
NC
NC
NC
I/O
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset
Figure 8: CP56 Package
Additional Information
CoolRunner-II Data sheets and Application Notes Online Store Device Package Drawings
Revision History
The following table shows the revision history for this document. Date 06/04/02 10/15/02 11/26/02 01/09/03 04/15/03 08/18/03 01/26/04 03/30/04 7/1/04 Version 1.0 1.1 1.2 1.3 2.0 2.1 2.2 2.3 2.4 Initial Xilinx release. Add AC characteristics and minor edits. Minor edits. Minor edits. Added bin 1 timing information. Corrected package drawing, IIH, IIL consolidation. Added links to packages and application notes. Changed tFIN to tDIN. Recommended move to new XC2C32A device. Pb-free documentation Revision
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DS091 (v2.7) November 8, 2004 Preliminary Product Specification
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XC2C32 CoolRunner-II CPLD
Date 10/01/04 10/07/04 11/08/04
Version 2.5 2.6 2.7 Removed note, page 1.
Revision Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics. Add note recommending moving to XC2C32A for new designs.
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