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Ordering number : ENN7946
SANYO Semiconductors
DATA SHEET
LB11946
Overview
PWM Current Control Stepping Motor Driver
Monolithic Digital IC
The LB11946 is a stepping motor driver IC that implements PWM current control bipolar drive with a fixed off time. This IC features 15 current setting levels using a fixed VREF voltage and support for microstepping drive from 1-2 phase excitation drive to 4W1-2 phase excitation drive. This device is optimal for driving stepping motors such as those used for carriage drive and paper feed in printers.
Features
* PWM current control (with a fixed off time) * Logic input serial-parallel converter (allows 1-2, W1-2, 2W1-2, and 4W1-2 phase excitation drive) * Current attenuation switching function (with slow decay, fast decay, and mixed decay modes) * Built-in upper and lower side diodes * Simultaneous on state prevention function (through current prevention) * Noise canceller function * Thermal shutdown circuit * Shutoff on low logic system voltage circuit * Low-power mode control pin
Specifications
Absolute Maximum Ratings at Ta
Parameter Motor supply voltage Peak output current Continuous output current Logic system supply voltage Logic input voltage range Emitter output voltage Allowable power dissipation (IC internal) Operating temperature Storage temperature
25 C
Symbol VBB IO peak IO max VCC VIN VE VE Pdmax Topr Tstg VCC VCC Ta 5 V specifications 3.3 V specifications 25C, independent IC tw 20 S Conditions Ratings 50 1.2 1.0 7.0 0.3 to VCC 1.0 0.5 3.0 20 to 85 55 to 150 Unit V A A V V V V W C C
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co., Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
73004TN(OT) No.7946-1/12
LB11946
Recommended Operating Conditions at Ta
Parameter Motor supply voltage Logic system supply voltage Reference voltage Symbol VBB VCC VREF VCC VCC VCC VCC 5 V specifications 3.3 V specifications 5 V specifications 3.3 V specifications
25 C
Conditions Ratings 10 to 45 4.5 to 5.5 3.0 to 3.6 0.0 to 3.0 0.0 to 1.0 Unit V V V V V
Electrical Characteristics at Ta = 25C, VCC = 5 V, VBB = 42 V, VREF = 1.52 V
Parameter [Output Block] Output stage supply current Output saturation voltage 1 Output saturation voltage 2 Output saturation voltage 3 Output saturation voltage 4 Output leakage current Output sustain voltage [Logic Block] ICC ON Logic system supply current ICC OFF1 ICC OFF2 Input voltage Input current VIH VIL IIH IIL VIH VIL 2V 0.8 V 1, D3 1, D3 0, D3 0, D3 1, D3 1, D3 0, D3 0, D3 1, D3 1, D3 0, D3 0, D3 1, D3 1, D3 1 When these data 0 1 0 1 0 1 0 1 0 1 0 1 0 6 0.470 0.445 0.425 0.410 0.385 0.365 0.345 0.325 0.280 0.240 0.195 0.155 0.115 0.075 0.5 1.6 4.0 V 5.0 2.6 2.45 0.03 Design guarantee 2.8 2.65 0.15 170 3.0 2.85 0.35 1.2 0.8 0.50 0.48 0.46 0.43 0.41 0.39 0.37 0.35 0.30 0.26 0.22 0.17 0.13 0.09 0.525 0.505 0.485 0.465 0.435 0.415 0.385 0.365 0.325 0.285 0.235 0.190 0.145 0.100 D0 1, D1 1, D2 values are set D0 ST 0, D1 LOW 2 0.8 35 0, D2 1, D3 0, D3 1 When these data 0 24 22 35 32 0.05 46 42 0.1 mA mA mA V V A A V V V V V V V V V V V V V V A mA A V V V C IBB-ON IBB-OFF VO(sat) 1 VO(sat) 2 VO(sat) 3 VO(sat) 4 IO1 (leak) IO2 (leak) VSUS IO IO IO IO VO VO L 0.5 A (sink) 1.0 A (sink) 0.5 A (source) 1.0 A (source) VBB (sink) 0V (source) 15 mH, IO 1.0 A 50 45 0.9 0.52 1.3 0.7 1.1 1.4 1.9 2.2 1.7 1.05 1.4 1.7 2.2 2.5 50 mA mA V V V V A A V Symbol Conditions Ratings min typ max Unit
D0 1, D1 1, D2 values are set D0 D0 D0 D0 D0 Sense voltages VE D0 D0 D0 D0 D0 D0 D0 D0 Reference current CR pin current MD pin current Logic system on voltage Logic system off voltage LVSD hysteresis Thermal shutdown temperature IREF ICR IMD VLSDON VLSDOFF VLHIS Ts VREF CR MD 1, D1 1, D1 1, D1 1, D1 1, D1 1, D1 1, D1 0, D1 0, D1 0, D1 0, D1 0, D1 0, D1 1.5 V 1.0 V 1.0 V, CR 1, D2 1, D2 1, D2 0, D2 0, D2 0, D2 0, D2 1, D2 1, D2 1, D2 1, D2 0, D2 0, D2
No.7946-2/12
LB11946
AC Electrical Characteristics at VCC
Parameter Clock frequency Data setup time Data hold time Minimum clock high-level pulse width Minimum clock low-level pulse width SET pin stipulated time SET pin signal pulse width Symbol Fclk TDS TDH TSCH TSCL Tlat Tlatw VCC VCC VCC VCC VCC VCC VCC 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 0.9 0.9 0.9 0.9 0.9 1.9
5V
Conditions Ratings min typ 200 2.5 2.5 2.5 2.5 2.5 5.0 max 550 Unit kHz S S S S S S
Fclk
TSCH TSCL CLK TDS TDH DATA
D4 D5 D6 D10 D11 Tlat
SET
Tlatw
No.7946-3/12
LB11946
Electrical Characteristics at Ta = 25C, VCC = 3.3 V, VBB = 42 V, VREF = 1.0 V (When measuring the sense voltage: VREF = 1.03 V)
Parameter [Output Block] Output stage supply current Output saturation voltage 1 Output saturation voltage 2 Output saturation voltage 3 Output saturation voltage 4 Output leakage current Output sustain voltage [Logic Block] ICC ON Logic system supply current ICC OFF1 ICC OFF2 Input voltage Input current VIH VIL IIH IIL VIH VIL D0 D0 D0 D0 D0 D0 Sense voltages VE D0 D0 D0 D0 D0 D0 D0 D0 Reference current CR pin current MD pin current LVSD voltage Logic system off voltage LVSD hysteresis Thermal shutdown temperature IREF ICR IMD VLSDON VLSDOFF VLHIS Ts Design guarantee VREF CR MD 2V 0.8 V 1, D1 1, D1 1, D1 1, D1 1, D1 1, D1 1, D1 1, D1 0, D1 0, D1 0, D1 0, D1 0, D1 0, D1 1.0 V 1.0 V 1.0 V, CR 4.0V 1, D2 1, D2 1, D2 1, D2 0, D2 0, D2 0, D2 0, D2 1, D2 1, D2 1, D2 1, D2 0, D2 0, D2 1, D3 1, D3 0, D3 0, D3 1, D3 1, D3 0, D3 0, D3 1, D3 1, D3 0, D3 0, D3 1, D3 1, D3 1 VREF 0 VREF 1 VREF 0 VREF 1 VREF 0 VREF 1 VREF 0 VREF 1 VREF 0 VREF 1 VREF 0 VREF 1 VREF 0 VREF 1.03 V 1.03 V 1.03 V 1.03 V 1.03 V 1.03 V 1.03 V 1.03 V 1.03 V 1.03 V 1.03 V 1.03 V 1.03 V 1.03 V 6 0.303 0.290 0.276 0.263 0.250 0.236 0.223 0.209 0.183 0.155 0.128 0.102 0.074 0.047 0.5 0.91 5.0 2.6 2.45 0.03 2.8 2.65 0.15 170 3.0 2.85 0.35 0.7 0.49 0.330 0.315 0.300 0.286 0.272 0.257 0.243 0.228 0.200 0.170 0.143 0.114 0.085 0.057 0.356 0.341 0.324 0.309 0.294 0.278 0.263 0.247 0.217 0.185 0.158 0.126 0.096 0.067 D0 1, D1 1, D2 1, D3 1 When these data values are set D0 ST 0, D1 0.8 V 2 0.8 35 0, D2 0, D3 0 21 19 30 28 0.03 39 36.5 0.1 mA mA mA V V A A V V V V V V V V V V V V V V A mA A V V V C IBB ON IBB OFF VO(sat) 1 VO(sat) 2 VO(sat) 3 VO(sat) 4 IO1 (leak) IO2 (leak) VSUS IO IO IO IO VO VO L 0.5 A (sink) 1.0 A (sink) 0.5 A (source) 1.0 A (source) VBB (sink) 0 V (source) 15 mH IO 1.5A 50 45 0.9 0.52 1.3 0.7 1.2 1.5 2.0 2.3 1.7 1.05 1.5 1.8 2.3 2.6 50 mA mA V V V V A A V Symbol Conditions Ratings min typ max Unit
No.7946-4/12
LB11946
AC Electrical Characteristics at VCC
Parameter Clock frequency Data setup time Data hold time Minimum clock high-level pulse width Minimum clock low-level pulse width SET pin stipulated time SET pin signal pulse width Symbol Fclk TDS TDH TSCH TSCL Tlat Tlatw VCC VCC VCC VCC VCC VCC VCC 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 0.9 0.9 0.9 0.9 0.9 1.9
3.3 V
Conditions Ratings min typ 200 2.5 2.5 2.5 2.5 2.5 5.0 max 550 Unit kHz S S S S S S
Fclk TSCH TSCL
CLK
TDS TDH
DATA
D4
D5
D6
D10
D11 Tlat
SET
Tlatw
Package Dimensions unit: mm 3147C
SANYO : DIP-28H (500mil)
No.7946-5/12
LB11946
Pin Assignment
VREF1
VREF2
16 13
DATA
28
27
26
25
24
23
22
21
20
19
18
17
15
LB11946
1 2 3 4 5 6 7 8 9 10 11 12 14
NC
NC
NC
VBB
D-GNDA
OUTA
OUTA-
OUTB-
OUTB
D-GNDB
NC
Note : The D-GNDA and D-GNDB pins are the anode sides of the lower side diodes.
VBB
E1
E2
GND
VCC
CR1
CR2
CLK
SET
MD
NC
NC
NC
ST
No.7946-6/12
LB11946
Block Diagram
No.7946-7/12
LB11946
Timing Chart
T SCH C LO C K T SCL D AT A
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
SET
Serially Transferred Data Definition
IA4 No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 D0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 IA3 D1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 IA2 D2 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 IA1 D3 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 DE1 D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * PH1 D5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * IB4 D6 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 IB3 D7 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 IB2 D8 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 IB1 D9 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 DE2 D10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * PH2 D11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * OUTA H H H H H H H H H H H H H H L L L L L L L L L L L L L L OFF Output mode OUTA L L L L L L L L L L L L L L H H H H H H H H H H H H H H OFF OUTB H H H H H H H H H H H H H H L L L L L L L L L L L L L L OFF OUTB L L L L L L L L L L L L L L H H H H H H H H H H H H H H OFF I/O ratio 100% 96 91 87 83 78 74 70 61 52 44 35 26 17 100 96 91 87 83 78 74 70 61 52 44 35 26 17 0 DEC MODE SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST *
Note : Either 0 or 1. Note 1: In mixed decay mode, set D4 and D10 to 0 and set the MD pin to a level in the range 1.5 to 4.0 V.
No.7946-8/12
LB11946
Current Settings Truth Table Current Settings Truth Table * Items in parentheses are defined by the serial data.
IA4 (D0) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 IA3 (D1) 1 1 1 1 0 0 0 0 1 1 1 1 0 0 IA2 (D2) 1 1 0 0 1 1 0 0 1 1 0 0 1 1 IA1 (D3) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 11.5/11.5 11.0/11.5 10.5/11.5 10.0/11.5 9.5/11.5 9.0/11.5 8.5/11.5 8.0/11.5 7.0/11.5 6.0/11.5 5.0/11.5 4.0/11.5 3.0/11.5 2.0/11.5 Set current Iout VREF/3.04RE VREF/3.04RE VREF/3.04RE VREF/3.04RE VREF/3.04RE VREF/3.04RE VREF/3.04RE VREF/3.04RE VREF/3.04RE VREF/3.04RE VREF/3.04RE VREF/3.04RE VREF/3.04RE Vref/3.04RE Iout Iout Iout Iout Iout Iout Iout Iout Iout Iout Iout Iout Iout Iout Current ratio (%) 100 95.65 91.30 86.95 82.61 78.26 73.91 69.56 60.87 52.17 43.48 34.78 26.08 17.39
Note : The current ratios shown are calculated values.
Sample Application Circuit at VCC = 5 V
10 F 5V
30 k
680 pF
30 k 680 pF
1.5 V
0.1 F
MD voltage setting (1.6 to 3.9 V) Fast mode: ground Slow mode: VCC
Logic level inputs
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VREF1
VREF2 NC
13
DATA
LB11946
DGNDA DGNDB OUTAOUTBOUTA OUTB VBB VBB
14
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
M
E2
E1
12
GND
VCC
CR2
CR1
SET
CLK
MD
NC
NC
NC
ST
0.51
0.51
42 V
47 F
No.7946-9/12
LB11946
Sample Application Circuit at VCC = 3.3 V
10 F
3.3 V
30 k
680 pF
30 k 680 pF
1.0 V
0.1 F
MD voltage setting (1.2 to 2.5 V) Fast mode: ground Slow mode: VCC
Logic level inputs
28
27
26 NC
25
24
23
22
21
20
19
18
17
16
15
VREF1
VREF2 NC
13
DATA
LB11946
DGNDA DGNDB OUTAOUTBOUTA OUTB VBB VBB
14
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
M
E2
E1
12
GND
VCC
CR2
CR1
SET
CLK
MD
NC
NC
ST
0.51
0.51
42 V
47 F
No.7946-10/12
LB11946
Switching Off Time and Noise Canceller Time Calculations Notes on the CR Pin Setting (switching off time and noise canceller time) The noise canceller time (Tn) and the switching off time (Toff) are set using the following formulas. When VCC is 5 V Noise canceller time (Tn) Tn C R ln{(1.5-RI)/(4.0-RI)}[s] CR pin charge current: 1.25 mA Switching off time (Toff) Toff C R ln (1.5/4.8)[s] Component value ranges R: 5.6 k to 100 k C: 470 pF to 2000 pF When VCC is 3.3 V Noise canceller time (Tn) Tn C R ln {(1.06-RI)/(2.66-RI)}[s] CR pin charge current: 0.7 mA Switching off time (Toff) Toff C R ln (1.06/3.1)[s]
VCC line
One-shot multvibrator blanking time circuit
CR pin E1
C: 680pF
R: 30 k
CR Pin Internal Circuit Structure
Notes on the MD Pin If slow decay mode is set up by setting the D4 and D10 bits in the input serial data to 1, the MD pin must be shorted to ground. If fast decay mode is set up by setting the D4 and D10 bits in the input serial data to 0, mixed decay mode can be set with the MD pin. When the VCC = 5 V specifications are used the setting voltage range for mixed decay mode is 1.6 to 3.9 V. When the VCC = 3.3 V specifications are used the setting voltage range for mixed decay mode is 1.2 to 2.5 V. If mixed decay mode will not be used with the fast decay mode setting, either: (a) Short the MD pin to ground to select fast decay mode, or (b) Short the MD pin to VCC to select slow decay mode.
No.7946-11/12
LB11946
Usage Notes Notes on the VREF pin Since the VREF pin inputs the reference voltage used to set the current, applications must be designed so that noise does not occur at this pin. Notes on the ground pins Since this IC switches large currents, care is required with respect to the ground pins. The PCB pattern in sections where large currents flow must be designed with low impedances and must be kept separate from the small-signal system. In particular, the ground terminals of the E1 and E2 pin sense resistors (RE) and the external Schottky barrier diode ground terminals must be located as close as possible to the IC ground. The capacitors between VCC and ground and between VBB and ground must be as close as possible to the corresponding VCC and VBB pin in the pattern. Power on sequence When turning the power systems on VCC logic level inputs (CLK, DATA, SET, and ST)
VREF
VBB
When turning the power systems off VBB VREF logic level inputs (CLK, DATA, SET, and ST)
VCC
Note that if the power supply for the logic level inputs is on when the VCC power supply is off, a bias with an unstable state will be applied due to the protection diodes at the VCC pins, and this can cause incorrect operation.
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, of otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or This catalog provides information as of July, 2004. Specifications and information herein are subject to change without notice.
No.7946-12/12

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