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Genesys Logic, Inc.
GL811USB USB 2.0 to ATA / ATAPI Bridge Controller
Specification 1.3
May 10, 2002
Genesys Logic, Inc. 10F, No.11, Ln.155, Sec.3, Peishen Rd., Shenkeng, Taipei, Taiwan Tel: 886-2-2664-6655 Fax: 886-2-2664-5757 http://www.genesyslogic.com
GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
Contents
1. General Description ......................................................................................... 2 2. Features ............................................................................................................ 3 3. Function Block ................................................................................................. 4 3.1 Block Diagram .............................................................................................. 4 3.2 Functional Overview ..................................................................................... 5 4. Pinning Information ......................................................................................... 7 4.1 Pin Assignment............................................................................................. 7 4.2 Pin Description ............................................................................................. 8 5. Functional Description .................................................................................. 10 5.1 ATA/ ATAPI ................................................................................................. 10 5.2 USB 2.0 ...................................................................................................... 10 6. Electrical Characteristics .............................................................................. 11 6.1 Absolute Maximum Ratings ........................................................................ 11 6.2 Temperature Conditions ............................................................................. 11 6.3 DC Characteristics...................................................................................... 11 6.4 AC Characteristics- ATA/ ATAPI.................................................................. 13 6.5 AC Characteristics- USB 2.0 ...................................................................... 33 7. Package Dimension ....................................................................................... 34 8. Revision History............................................................................................. 35
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
1. General Description
The GL811USB is a highly-compatible, low cost USB 2.0 to ATA / ATAPI bridge controller, which integrates Genesys Logic own design high speed UTMI (USB 2.0 Transceiver Macrocell Interface) transceiver. As a one-chip solution which complies with Universal Serial Bus specification rev. 2.0 and ATA / ATAPI-6 specification rev 1.0, the GL811USB can support various kinds of ATA / ATAPI device. There are totally 4 endpoints in the GL811USB controller, Control (0), Bulk In (1), Bulk Out (2), and Interrupt (3). By complies with the USB Storage Class specification ver.1.0 (Bulk only protocol), the GL811USB can support not only plug and play but also Windows XP/ 2000/ ME default driver. The GL811USB uses 12MHz crystal and slew-rate controlled pads to reduce the EMI issue. With 48-pin LQFP (9mmX9mm) package, the GL811USB is the best cost/ performance solution to fit different situations in the USB 2.0 high speed storage class applications such as Hard Disk, CD-ROM, CD-R / RW and DVD-ROM.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
2. Features
Complies with Universal Serial Bus specification rev. 2.0. Complies with ATA/ATAPI-6 specification rev 1.0. Complies with USB Storage Class specification ver.1.0. (Bulk only protocol) Operating system supported: Win XP/ 2000/ ME/ 98/ 98SE; Mac OS 9.X/ X. Supports 4 endpoints: Control (0) / Bulk Read (1) / Bulk Write (2) / Interrupt (3). 64 / 512 bytes Data Payload for full / high speed Bulk Endpoint. Supports 8-bit/16-bit Standard PIO mode interface. Supports 16-bit Multiword DMA mode and Ultra DMA mode interface (Ultra 33 / 66 / 100). Embedded USB 2.0 UTMI transceiver. Embedded 7.5 MIPS RISC CPU. ROM size: 4k words; RAM size: 128 bytes. Supports Power Down mode and USB suspend indicator. Supports USB 2.0 TEST mode features. 12MHz external clock to provide better EMI3.3V power input. 5V tolerance pad for IDE interface. Supports Wakeup ability. Available in 48-pin LQFP (9 mm * 9mm) package.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
3. Function Block
3.1 Block Diagram
DMACK_ DIOR_ DIOW_ CS1_, CS0_ DA2 DA1 DA0 IODD15-0 INTRQ CBLID_ DMARQ IORDY
CLK15
GPIO1
CPU
Control Register
GPIO7 RPU
8 CONTROL FIFO CLK30
DPF
8/16-Bit IDE
4
TXFIFO0
RXSTS DPH
SIE
TXFIFO1
TXCTL
UTMI
USB2.0
DMF DMH
Engine
LOGIC TXCVR
16
RXFIFO0 12-96MHz RXFIFO1 DATA
RREF
X10
Clkgen
12MHz
X40
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
3.2 Functional Overview
3.2.1 USB 2.0 TXCVR The USB 2.0 Transceiver is the analog circuitry to handle the USB HS/FS signaling. 3.2.2 UTMI (USB 2.0 Transceiver Macrocell Interface) Logic The UTMI Logic is compliant to Intel's UTMI specification 1.01. This block handles the low level USB protocol and signaling. The major jobs of UTMI Logic is data and clock recovery, NRZI encoding/decoding, Bit Stuffing/De-stuffing, USB2.0 test modes supporting and serial / parallel conversion. 3.2.3 SIE (Serial Interface Engine) The SIE contains the USB packet ID and address recognition logic, and other sequencing and state machine logic to handle USB packets and transactions. 3.2.4 PLL 10XPLL provides the 120MHz clock output for UTMI Logic block. UTMI operates in 120MHz for USB HS data processing. 40XPLL block will provide 480MHz for USB HS data transmission. 3.2.5 CLKGEN CLKGEN is the clock generator block for the logic blocks. It generates 15MHz clock for micro controller, 12MHz for PIO mode, 48MHz for MDMA mode, 96MHz for UDMA mode, and 30MHz clock for UTMI, SIE, and FIFO. 3.2.6 CPU The CPU is the control center of GL811USB. It's an 8-bit micro controller operating in 15MHz, 7.5 MIPS. After receiving a USB command, it decodes the host command, then it re-assigns tasks to the IDE engine, GPIO, FIFO, and response proper data/status to USB host. 3.2.7 IDE Engine The IDE engine is extended from standard ATA / ATAPI protocol. It supports PIO mode, multiword DMA mode, and ultra DMA mode data transfers.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
3.2.8 FIFOs Control FIFO is used as Control Read / Write FIFO. TXFIFO0 / TXFIFO1 are two sets of 512-byte ping-pong FIFO for Bulk Read endpoint. It buffers data from IDE engine, and re-direct to USB SIE logic. RXFIFO0 / RXFIFO1 are two sets of 512-byte ping-pong FIFO for Bulk Write endpoint. It buffers data from USB SIE logic, and re-direct to IDE engine. 3.2.9 Control Registers Control Register configures GL811USB to proper operation. For example, CPU can set register to generate wakeup event, enter suspend, transmits proper USB packet to host.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
4. Pinning Information
4.1 Pin Assignment
48
47
46
45
44
43
42
41
40
39
38
GPIO7 IODD[8] IODD[9] IODD[10] IODD[11] DVCC1 DGND1 IODD[12] IODD[13] IODD[14] IODD[15] CBLID_
37 AVCC1 24
DMARQ
IODD[7]
IODD[6]
IODD[5]
IODD[4]
IODD[3]
IODD[2]
IODD[1]
IODD[0]
DGND2
DVCC2
GPIO1
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33
DIOW_ DIOR_ IORDY DMACK_ INTRQ DA1 DA0 CS0_ TEST AGND1 X1 X2
GL811USB 48 LQFP
32 31 30 29 28 27 26 25
13
14
15
16
17
18
19
20
21
22 AGND0
DMF
DPF
RESET#
(c)2000-2002 Genesys Logic Inc.--All rights reserved.
DA2/ SK
AVCC0
RREF
RPU
DPH
CS1_
DMH
23
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
4.2 Pin Description
Pin # 1 2~5 6 7 8~11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Name GPIO7 IODD [8:11] DVCC1 DGND1 IODD [12:15] CBLID_ CS1_ DA2 RESET# RPU AVCC0 DPF DPH DMF DMH AGND0 RREF AVCC1 X2 X1 AGND1 TEST CS0_ DA0 DA1 INTRQ DMACK_ IORDY DIOR_ DIOW_ DMARQ
I/O B B P P B I O O I A P B B B B P A P B I P I O O O I O I O O I
Pad Type I/O 8(*) I/O 16(*) Power Power I/O 16 I/O 8 I/O 16 I/O 16 I/O 8 U20mia Power U20mia U20mia U20mia U20mia Power U20mia Power Clock Clock Power I/O 8 I/O 16 I/O 16 I/O 16 I/O 8 I/O 16 I/O 16 I/O 16 I/O 16 I/O 8
Description GPIO7 (**) IDE data bus 8~11 Digital VCC Digital ground IDE data bus 12~15 Cable select input Chip select 1 IDE address 2 Reset pin (***) 3.3v output Analog VCC Full speed DP High speed DP Full speed DM High speed DM Analog ground Reference resister connect (****) Analog VCC Crystal output Crystal input, 12Mhz Analog ground TEST mode input Chip select 0 IDE address 0 IDE address 1 IDE interrupt input IDE acknowledge IDE ready IDE read signal IDE write signal IDE request
Note
tri tri
tri tri tri tri pu
pd tri tri tri tri tri pu tri tri pd
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
Pin # 38~41 42 43 44~47 48
Name IODD[0:3] DGND2 DVCC2 IODD[4:7] GPIO1
I/O B P P B B
Pad Type I/O 16 Power Power I/O 16 I/O 8
Description IDE data bus 0~3 Digital ground Digital VCC IDE data bus 4~7 GPIO1
Note
tri
tri pd
(*) The different of I/O 8 type from I/O 16 type is the typical drive current. The typical drive current of I/O 8 type is 8 mA, and for I/O pad 16 is 16 mA. (**) When operating in default mode: GPIO7 is the ATA/ ATAPI reset input, (***) When Reset pin is pulled low, the IDE bus will be in tri-state. (****) RREF must be connected with a 510 ohm resister to ground.
Notation: Description O I B P A pu pd tri Output Input Bi-directional Power Analog Internal pull up Internal pull down Tri-state
Note
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
5. Functional Description
5.1 ATA/ ATAPI
The GL811USB complies with ATA/ATAPI-6 specification rev. 1.0. Please refer to the specifications for more information.
5.2 USB 2.0
The GL811USB complies with Universal Serial Bus specification rev. 2.0, and it integrates Genesys Logic own design UTMI transceiver that fully complies with the USB 2.0 Transceiver Macercell Interface (UTMI) specification rev. 1.01. Please refer to the specifications for more information.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6. Electrical Characteristics
6.1 Absolute Maximum Ratings
Symbol VCC VI VI/O VAI/O VESD TA Description DC supply voltage DC input voltage DC input voltage range for I/O DC input voltage for USB D+/D- pins Static discharge voltage Ambient Temperature Min +3.0 -0.3 -0.3 -0.3 4000 0 100 Max +3.6 VCC + 0.3 VCC + 0.3 VCC + 0.3 Unit V V V V V
o
C
6.2 Temperature Conditions
Item Storage Temperature Operating Temperature Value -50oC ~ 150 oC 0 oC ~ 70 oC
6.3 DC Characteristics
6.3.1 I/O 8 Type digital pins (For pad type I/O 8 @ VCC=3.6V)
Parameter Current sink @ VOL = 0.4V Current output @ VOH = 2.4V (TTL high) Falling slew rate at 30 pF loading capacitance Rising slew rate at 30 pF loading capacitance Input high threshold voltage Input low threshold voltage
Min 7.79 16.36 0.26 0.30
Typ 10.83 19.87 0.50 0.57
Max 14.09 23.39 0.80 0.91 1.64
Unit mA mA V/ns V/ns V V
1.36
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
Parameter Hysteresis voltage Leakage current for pads with internal pull up or pull
Min -
Typ 0
Max 46
Unit V A Ohms Ohms mA
down resistor Pad internal pull down resister Pad internal pull up resister Supply current 51K 85K 105K 168K 152K 251K 109
6.3.2 I/O 16 Type digital pins (For pad type I/O 16 @ VCC=3.6V)
Parameter Current sink @ VOL = 0.4V Current output @ VOH = 2.4V (TTL high) Falling slew rate at 30 pF loading capacitance Rising slew rate at 30 pF loading capacitance Input high threshold voltage Input low threshold voltage Pad internal pull down resister
Min 16.20 24.13 0.51 0.46
Typ 21.90 29.46 0.93 0.83
Max 27.68 34.80 1.35 1.27 2.15
Unit mA mA V/ns V/ns V V
0.89 51K 105K 152K
Ohms
6.3.3 D+/ D- (For pad type u20mia @ VCC=3.6V)
Parameter D+/D- static output LOW (RL of 1.5K to VCC ) D+/D- static output HIGH (RL of 15K to GND ) Differential input sensitivity Single-ended receiver threshold Transceiver capacitance Hi-Z state data line leakage Driver output resistance
Min 0 2.8 0.2 0.8
Typ
Max 0.3 3.6
Unit V V V
2.0 20
V pF A Ohms
-10 28
+10 43
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.3.4 Switching Characteristics
Parameter X1 crystal frequency X1 cycle time D+/D- rise time with 50pF loading D+/D- fall time with 50pF loading
Min 11.97
Typ 12 83.3
Max 12.03
Unit MHz ns
4 4
20 20
ns ns
6.4 AC Characteristics- ATA/ ATAPI
The GL811USB complies with ATA / ATAPI-6 specification rev 1.0, which supports following data transfer modes: 1. PIO (Programmed Input/ Output) data transfer: PIO data transfers are performed by the host processor utilizing PIO register accesses to the Data register. 2. DMA (Direct Memory Access) data transfer: DMA data transfer means of data transfer between device and host memory without host processor intervention. - Multiword DMA: Multiword DMA is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When a Multiword DMA transfer is enabled as indicated by IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data, this data transfer protocol shall be used for the data transfers associated with these commends. (Please refer to the ATA / ATAPI-6 specification rev 1.0 for more information.) - Ultra DMA: Ultra DMA Is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When this protocol is enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. (Please refer to the ATA / ATAPI-6 specification rev 1.0 for more information.) Following listed the symbols and their respective definitions that are used in the timing diagram:
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
-
Signal transition (asserted or negated) Data transition (asserted or negated) Data valid Undefined but not necessarily released Asserted, negated or released Released The "other" condition if a signal is shown with no change
All signals are shown with the asserted condition facing to the top of the page. The negated condition is shown towards the bottom of the page relative to the asserted condition. The interface uses a mixture of negative and positive signals for control and data. The terms asserted and negated are used for consistency and are independent of electrical characteristics. In all timing diagrams, the lower line indicates negated, and the upper line indicates asserted. The following illustrates the representation of a signal named Test going from negated to asserted and back to negated, based on the polarity of the signal.
Test
> VIH < VIL
Assert
Negate
Test_
< VIL > VIH
Assert
Negate
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.4.1 Register transfers
t0 ADDR valid (Note1) t1 t2 t9 t2i DIOR_/DIOW_ WRITE IODD(7:0) (Note2) t3 Read IODD(7:0) (Note2) t5 IORDY (Note3.1) tA IORDY (Note3.2) tC IORDY (Note3.3) tB tC tRD t6 t6z t4
Notes: 1. Device address consists of signals CS0_, CS1_ and DA(2:0). 2. Data consists of IODD(7:0). 3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is to be extended is made by the host after tA from the assertion of DIOR_ or DIOW_. The assertion and negation of IORDY are described as following:
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
3.1 Device never negates IORDY, devices keeps IORDY released: no wait is generated. 3.2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released prior to negation and may be asserted for no more than 5 ns before release: no wait generated. 3.3 Device negates IORDY before tA, IORDY is released prior to negation and may be asserted for no more than 5 ns before release: wait generated. The cycle completes after IORDY is released. For cycles where a wait is generated and DIOR_ is asserted, the device shall read data on IODD(0:7) for tRD before asserting IORDY. 4. DMACK_ shall remain negated during a register transfer.
Register transfer timing parameters t0 t1 t2 t2i t3 t4 t5 t6 t6Z t9 Cycle time Address valid to DIOR_/ DIOW_ setup DIOR_/ DIOW_ pulse width 8-bit DIOR_/ DIOW_ recovery time DIOW_ data setup DIOW_ data hold DIOR_ data setup DIOR_ data hold DIOR_ data tristate DIOR_/ DIOW_ to address valid hold Read Data Valid to IORDY active tRD (if IORDY initially low after tA) tA tB tC IORDY Setup time IORDY Pulse Width IORDY assertion to release (max)
Timing (ns) 2000 1000 300 900 80 40 900
-
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.4.2 Multiword DMA data transfer
Multiword DMA timing parameters t0 tD tE tF tG tH tI tJ tKR tKW tLR tLW tM tN tZ Cycle time DIOR_/ DIOW_ asserted pulse width DIOR_ data access DIOR_ data hold DIOR_/ DIOW_ data setup DIOW_ data hold DMACK to DIOR_/ DIOW_ setup DIOR_/ DIOW_ to DMACK hold DIOR_ negated pulse width DIOW_ negated pulse width DIOR_ to DMARQ delay DIOW_ to DMARQ delay CS(1:0) (max) valid to DIOR_/ DIOW_ CS(1:0) hold DMACK_ to read data released
Timing (ns) 120 80 40 18 18 20 36 36 36 18 -
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.4.2.1 Initiating a Multiword DMA data burst
CS0_/ CS1_ (Note) tM
DMARQ (Note)
DMACK_ tI DIOR_/DIOW_ tE Read DD(15:0) tG tF tD
Write DD(15:0) tG tH
Note: The host shall not assert DMACK_ or negate both CS0_ and CS1_ until the assertion of DMARQ is detected. The maximum time from the assertion of DMARQ to the assertion of DMACK_ or the negation of both CS0_ and CS1_ is not defined.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.4.2.2 Sustaining a Multiword DMA data burst
CS0_/ CS1_ t0 DMARQ DMACK_ tD DIOR_/DIOW_ tE Read DD(15:0) tG Write DD(15:0) tG tH tG tH tF tG tF tE tK
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.4.2.3 Device terminating a Multiword DMA data burst
CS0_/ CS1_ tN t0 DMARQ (Note) tL DMACK_ tK DIOR_/DIOW_ tE Read DD(15:0) tG Write DD(15:0) tG tH tF tZ tD tJ
Note: To terminate the data burst, the Device shall negate DMARQ within the tL of the assertion of the current DIOR_ or DIOW_ pulse. The last data word for the burst shall then be transferred by the negation of the current DIOR_ or DIOW_ pulse. If all data for the command has not been transferred, the device shall reassert DMARQ again at any later time to resume the DMA operation.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.4.2.4 Host terminating a Multiword DMA data burst
CS0_/ CS1_ tN DMARQ (Note2) DMACK_ (Note1) tK DIOR_/DIOW_ tE Read DD(15:0) tG Write DD(15:0) tG tH tF tZ tD tJ t0
Note: 1. To terminate the transmission of a data burst, the Host shall negate DMACK_ within the specified time after a DIOR_ or DIOW_ pulse. No further DIOR_ or DIOW_ pulses shall be asserted for this burst.
2.If the device is able to continue the transfer of data, the device may leave DMARQ asserted
and wait for the host to reassert DMACK_ or may negate DMARQ at any time after detecting that DMACK_ has been negated.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.4.3 Ultra DMA data transfer
6.4.3.1 Ultra DMA data burst timing requirements
Name
Mode 0 (in ns)
min max 240 112 230 15 5 70 6 0 0 20 0 10 20 0 20 70 50 75 160 20 0 20 230 150
Mode 1 (in ns)
min 160 73 154 10 5 48 6 0 0 20 0 10 20 0 20 70 30 70 125 20 0 20 200 150 max
Mode 2 (in ns)
min 120 54 115 7 5 30 6 0 0 20 0 10 20 0 20 70 20 60 100 20 0 20 170 150 max
Mode 3 (in ns)
min 90 39 86 7 5 20 6 0 0 20 0 10 20 0 20 55 NA 60 100 20 0 20 130 100 max
Mode 4 (in ns)
Min 60 25 57 5 5 6 6 0 0 20 0 10 20 0 20 55 NA 60 100 20 0 20 120 100 max
Comment
Typical sustained average two cycle time Cycle time allowing for asymmetry and clock variations Two cycle time allowing for clock variations Data setup time at recipient Data hold time at recipient Data valid setup time at sender Data valid hold time at sender First STORBE time Limited interlock time Interlock time with minimum Unlimited interlock time Maximum time allowed for output drivers to release Minimum delay time required for output Drivers to assert or negate Envelope time STROBE to DMARDY_ time Ready to final STROBE time Minimum time to assert STOP or negate DMARQ Maximum time before releasing IORDY Minimum time before driving STROBE Setup and hold times for DMACK_ Time from STROBE edge to negation of DMARQ or assertion of STOP
t2CYCTYP tCYC t2CYC tDS tDH tDVS tDVH tFS tLI tMLI tUI tAZ tZAH tZAD tENV tSR tRFS tRP tIORDYZ tZIORDY tACK
tSS
50
50
50
50
50
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.4.3.2 Initiating an Ultra DMA data-in burst
DMARQ (device) tUI DMACK_ (host) tACK STOP (host) tACK HDMARDY_ (host) DSTROBE (device) tAZ IODD (15:0) DA0, DA1, DA2, CS0_, CS1_ tACK tDVS tDVH tZIORDY tENV tZAD tFS tENV tZAD tFS
Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are not in efficient until DMARQ and DMACK are asserted.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.4.3.3 Sustained Ultra DMA data-in burst
t2CYC tCYC DSTROBE at device tDVH IODD(15:0) at device DSTROBE at host IODD(15:0) at host tDH tDS tDH tDS tDH tDVS tDVH tDVS tDVH tCYC t2CYC
Notes: IODD(15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.4.3.4 Host pausing an Ultra DMA data-in burst
DMARQ (device) DMACK_ (host) STOP (host) HDMARDY_ (host) DSTROBE (device) IODD(15:0) (device) tRFS tSR tRP
Notes: 1. The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY_ is negated.
2.If the tSR timing is not satisfied, the host may receive zero, one, or two more data words from
the device.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.4.3.5 Device terminating an Ultra DMA data-in burst
DMARQ (device) DMACK_ (host) tLI STOP (host) tLI HDMARDY_ (host) DSTROBE (device) tZAH tAZ IODD(15:0) tACK DA0, DA1, DA2, CS0_, CS1_ tDVS tDVH tSS tIORDYZ tACK tLI tACK tMLI
Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.4.3.6 Host terminating an Ultra DMA data-in burst
DMARQ (device) tLI DMACK_ (host) STOP (host) tACK HDMARDY_ (host) tRFS DSTROBE (device) tDVS IODD(15:0) tACK DA0, DA1, DA2, CS0_, CS1_ tDVH tLI tMLI tIORDYZ tRP tAZ tZAH tACK tMLI
Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.4.3.7 Initiating an Ultra DMA data-out burst
DMARQ (device) DMACK_ (host) tACK STOP (host) DDMARDY_ (device) tACK HSTROBE (host) IODD (15:0) (host) tACK DA0, DA1, DA2, CS0_, CS1_ tDVS tDVH tZIORDY tENV tLI tUI tENV tUI
Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.4.3.8 Sustained Ultra DMA data-out burst
t2CYC tCYC HSTROBE at host tDVH IODD(15:0) at host HSTROBE at device IODD(15:0) at device tDH tDS tDH tDS tDH tDVS tDVH tDVS tDVH tCYC t2CYC
Notes: IODD(15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the devicet until some time after they are driven by the host.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.4.3.9 Device pausing an Ultra DMA data-out burst
DMARQ (device) DMACK_ (host) STOP (host) DDMARDY_ (device) HSTROBE (host) IODD(15:0) (host) tRFS tSR
tRP
Notes: 1.The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY_ is negated. 2.If the tSR timing is not satisfied, the device may receive zero, one, or two more data words from the host.
(c)2000-2002 Genesys Logic Inc.--All rights reserved.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.4.3.10 Host terminating an Ultra DMA data-out burst
DMARQ (device) DMACK_ (host) tSS STOP (host) DDMARDY_ (device)
tLI
tMLI
tLI
tACK
tLI
tIORDYZ
tACK HSTROBE (host) tDVS IODD(15:0) (host) tACK DA0, DA1, DA2, CS0_, CS1_ tDVH
Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.
(c)2000-2002 Genesys Logic Inc.--All rights reserved.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.4.3.11 Device terminating an Ultra DMA data-out burst
DMARQ (device) DMACK_ (host) STOP (host) tRP DDMARDY_ (device) tRFS HSTROBE (host) tDVS IODD(15:0) (host) tACK DA0, DA1, DA2, CS0_, CS1_ tDVH tLI tMLI tACK tIORDYZ tLI tMLI tACK
Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.
(c)2000-2002 Genesys Logic Inc.--All rights reserved.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
6.5 AC Characteristics- USB 2.0
The GL811USB conforms to all timing diagrams and specifications for Universal Serial Bus specification rev. 2.0. Please refer to this specification for more information.
(c)2000-2002 Genesys Logic Inc.--All rights reserved.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
7. Package Dimension
SYMBOL
A A1 A2 C1 D D1 E E1 e b L L1
MIN
MAX
1.6
0.05 1.35 0.09 9.00BSC 7.00BSC 9.00BSC 7.00BSC 0.5BSC 0.17 0.45 1 REF
0.15 1.45 0.16
0.27 0.75
(c)2000-2002 Genesys Logic Inc.--All rights reserved.
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GL811USB - USB 2.0 to ATA / ATAPI Bridge Controller
8. Revision History
Version 1.0 1.1 1.2 1.3 First draft Correct the pin assignment GPIO1/ CPIO7 for 48-pin package Electrical Characteristics data supplement, and eliminate the 100-pin LQFP package. Description Date 2001/08/31 2002/02/06 2002/04/12
AC Characteristics (ATA/ ATAPI) data supplement in Chapter 6. 2002/05/10
(c)2000-2002 Genesys Logic Inc.--All rights reserved.
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