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BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
GENERAL DESCRIPTION
The samsung analog front end(AFE) for CCD/CIS image signal is an integrated analog signal processor for color image signal. The AFE converts CCD/CIS output signal to digital data. The AFE includes three-channel CDS(Correlated Double Sampling) circuit, PGA(Programmable Gain Amplifier), and 12-bit analog to digital converter with reference generator. A parallel data bus provides a simple interface to 8-bit microcontroller.
APPLICATIONS
* * * * Color and B/W Scanner Digital Copiers Facsimile General Purpose CCD/CIS imager
FETURES
* * * * * * * * * * 12-bit 6MSPS A/D Converter Integrated Triple Correlated Double Sampler 3-Channel 2 MSPS Color Mode Analog Programmble Gain Amplifier Internal Voltage Reference Wide clamp level controllability for CIS sensor No Missing Code Guaranteed Microcontroller-Compatible Control Interface Operation by Single 5V Supply CMOS Low Power Dissipation
KEY SPECIFICATION
* * * * Resolution: 12-bit Conversion Rate: 6 MHz(2 MHz*3) Supply Voltage: 5 V 5% Power Dissipation: 375 mW(Typical)
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AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
FUNCTIONAL BLOCK DIAGRAM
RED CDS PGA REF GREEN INPUT OFFSET REGISTER CDS PGA MUX ADC D[11:0]
MPU PORT BLUE CDS PGA GAIN REGISTER
Ver 2.0 (Apr. 2002) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice.
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BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
CORE PIN DESCRIPTION
Name VDDA1 VSSA1 VDDA2 VSSA2 VBB VDDD VSSD REFT REFB VCOM BGR R_VIN G_VIN B_VIN STRTLN CDS1_CLK CDS2_CLK ADCCLK CSB WRB RDB OEB D[11:0]/MPU[7:0] AD[2:0] MCTL1, MCTL2 EXT_MCTL I/O Type AP AG AP AG AG DP DG AB AB AB AB AI AI AI DI DI DI DI DI DI DI DI DB DI DI DI I/O Pad vdda vssa vdda vssa vbba vddd vssd piar50_bb piar50_bb piar50_bb piar50_bb piar10_bb piar10_bb piar10_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb pia_bb picc_bb picc_bb picc_bb Pin Description 5 V Analog Supply Analog Ground 5 V Analog Supply(for ADC) Analog Ground(for ADC) Substarte Ground 5 V Digital Supply Digital Ground Reference Decoupling Reference Decoupling Analog Common Voltage Bandgap Refernce Voltage Analog Input; Red Analog Input; Green Analog Input; Blue STRTLN indicates beginning of line CDS Reset Clock Pulse Input CDS Data Clock Pulse Input A/D Converter Sample Clock Input Chip Select; Active Low Write Strobe; Active Low Read Strobe; Active Low Output Enable; Active Low Data Inputs/Outputs Register Select Channel Select in External MUX Control External MUX Control; Active Low
I/O TYPE ABBR. * * * * * AI : Analog Input AO : Analog Output AP : Analog Power DP : Digital Power * DI : Digital Input * DO : Analog Output * AG : Analog Ground * DG : Digital Ground
AB : Analog Bidirectional Port * DB : Digital Bidirectional Port
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AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
CORE PIN CONFIGURATION
BGR VSSA2 VDDA2 VSSA1 VDDA1
REFT
VCOM REFB
EXT_MCTL MCTL1,MCTL2
R_VIN G_VIN B_VIN VDDD VSSD VBB STRTLN CDS1_CLK CDS2_CLK ADCCLK D[11:0]/MPU[7:0]
BL8531H
AD[2:0] CSB WRB RDB OEB
ABSOLUTE MAXIMUM RATINGS
Charateritics Supply Voltage Analog Input Voltage Digital Input Voltage Digital Output Voltage Reference Voltage Storage Temperature Range Operating Temperature Range Symbol VDD AIN CLK VOH, VOL VRT/VRB Tstg Topr Value 6.5 VSS to VDD VSS to VDD VSS to VDD VSS to VDD -45 to 150 0 to 70 Units V V V V V C C
NOTES: 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5k resistor (Human body model)
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BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
ANALOG SPECIFICATIONS
(VDDA = 5V, VDDD = 5V, ADCCLK = 6MHz, CDS1_CLK = 2MHz, CDS2_CLK = 2MHz, PGA Gain = 1 unless otherwise noted) Characteristics Resolution Signal-to-Noise & Distortion Ratio Conversion Rate 3-Channel with CDS 1-Channel with CDS Differential Nonlinearity Integral Nonlinearity Unipolar Offset Error Gain Error Anlog Input Full-Scale Input Input Capacitance Reference Top Reference Bottom Power Supply Analog Voltage Digital Voltage Analog Current Digital Current Power Consumption Temperature Range 0 VDDA VDDD IDDA IDDD 5 5 65 10 375 70 V V mA mA mW C 0.06 8 3.5 1.5 4.0 Vp-p Pf V V 5V 5% 5V 5% DNL INL 6 6 1 2 1.0 2.0 MSPS MSPS LSB LSB %FSR %FSR SNDR Symbol Min 12 60 Typ Max Unit Bits dB Comment
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AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
DIGITAL SPECIFICATIONS
(VDDA = 5V, VDDD = 5V, ADCCLK = 6MHz, CDS1_CLK = 2MHz, CDS2_CLK = 2MHz, CL = 20pF unless otherwise noted) Characteristics High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Symbol VIH VIL IIH IIL VOH VOL 4.5 0.5 10 10 Min 3.0 0.8 Typ Max Unit V V mA mA V V IOH = 0.5mA IOL = -0.5mA Comment
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BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
TIMING SPECIFICATIONS
(VDDA = 5V, VDDD = 5V unless otherwise noted) Characteristics 3-Channel Conversion Rate 1-Channel Conversion Rate CDSCLK1 Pulse Width CDSCLK2 Pulse Width CDSCLK2B Pulse Width CDSCLK1 Falling to CDSCLK2 Rising CDSCLK2 Falling to CDSCLK1 Rising ADCCLK Pulse Width CDSCLK2 Rising to ADCCLK Rising CDSCLK2 Falling to ADCCLK Falling ADCCLK Rising to CDS2CLK Falling STRTLN Rising, Falling Setup & Hold ADC Output Delay Register Address Setup Time Register Address Hold Time Data Hold Time Register Chip Select Setup Time Register Chip Select Hold Time Register Read Pulse Width Write Pulse Width Register Read To Data Valid Output Enable High to Tri-State Tri-State to Data Valid Aperture Delay Latency for 1 Channel mode tC1CLK tC2CLK tC2CLKB tC1C2A tC2C1A tADCLK tC2ADA tC2ADB tADC2A tS, tH tADDT tAS tAH tDH tCSS tCSH tPWR tPWW tDD tHZ tDEV tAD Symbol Min 500 166 60 70 70 5 5 70 70 5 5 15 20 15 15 15 15 15 50 25 40 10 15 2 4 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ADCCL K Cycles
* Aperture delay is a timing measurement between the sampling clocks and CDS. It is measured from the falling edge of the CDS2_CLK input to when the input signal is held for data conversion
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AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
TIMING DIAGRAM
3-Channel CDS Mode
Analog Input
R0,G0,B0 tC1C2A tC2C1A
R1,G1,B1 tC1CLK
R2,G2,B2
CDS1_CLK tC2ADA CDS2_CLK tADCLK ADCCLK tH STRTLN tS tADC2A tC2CLKB
3-Channel SHA Mode
Analog Input R0,G0,B0 tC2ADA CDS2_CLK tADCLK ADCCLK tH STRTLN tS tADC2A R1,G1,B1 tC2CLKB R2,G2,B2
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BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
1-Channel CDS Mode
Analog Input tC1CLK CDS1_CLK tC2CLK CDS2_CLK tC2ADA ADCCLK tC2ADB tADCLK tC1C2A tC2C1A
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AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
TIMING DIGRAM
1-Channel SHA Mode
Analog Input
R0,G0,B0 tC2CLK
R1,G1,B1
R2,G2,B2
CDS2_CLK tC2ADA tC2ADB ADCCLK tADCLK
ADC Timing
ADC Input
A(n)
A(n+1)
ADCCLK tADDT ADCOUT A(n-3)[11:0] A(n-2)[11:0] A(n-1)[11:0] A(n)[11:0]
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BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
Write Timing
OEB
CSB tAS AD[2:0] tCSS WRB tPWW tDH tDD MPU[7:0] tCSH
tAH
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AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
TIMING DIGRAM
Read (1) Timing
CSB tAS AD[2:0] tCSS RDB tDD MPU[7:0] tPWR tCSH tDH tAH
'Read(1)' means microcontroller reads MPU[7:0] CSB should keep 'High' to read. Read (2) Timing
ADCCLK tADDT D[11:0] tHZ OEB tDEV
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BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
FUNCTIONAL DESCRIPTION
1) 3-Channel Operation with CDS This mode enables simultaneous sampling of a triple output CCD. The CCD waveforms are ac coupled to the VINR, VING and VINB pins where they are automatically biased at an appropriate voltage using the on-chip clamp. The internal CDSs take two samples of the incoming pixel data; the first samples are taken during the reset time while the second samples are taken during data portion of the input pixels. When STRTLN is low, the internal circuitry is reset on the next rising edge of ADCCLK; the multiplexer is switched to red channel. 2) 3-Channel SHA Operation This mode enables simultaneous sampling of a triple output CIS or something like that. The CDS functions are replaced with the sample and hold amplifiers. The input waveforms are either dc coupled or dc restored to the VINR, VING and VINB pins. The input reference voltage in this mode will be defined by clamp level control register. When STRTLN is low, the internal circuitry is reset on the next rising edge of ADCCLK; the multiplexer is switched to red channel. 3) 1-Channel Operation with CDS This mode enables single channel or monochrome sampling. The CCD waveforms are ac coupled to the analog input pin where they are automatically biased at an appropriate voltage using the on-chip clamp. Bit2 and bit3 in configuration register select the desired input among red, green and blue. 4) 1-Channel SHA Operation This mode enables single-channel or monochrome sampling. The CDS function is replaced with the sample and hold amplifier. The input waveforms are either dc coupled or dc restored to the analog input pin. The input reference voltage in this mode will be defined by clamp level control register. Bit2 and bit2 in configuration register select the desired input among red, green and blue.
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AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
MAIN BLOCK DESCRIPTION
1) Programmable Gain Amplifier The analog programmable gain can accommodate a wide range of input voltage spans. The transfer function of the PGA is as follows. H(X) = 1/6*X + 5/6, where the range of X is 0 to 31. Thus, the minimum gain value is equal to 5/6, and the maximum gain value is equal to 6. The transfer function has linearity in linear scale. The overall gain is equal to analog gain multiplied by digital gain. So, the multiplier should be required in back end of AFE.
16 14
6
5 12
8 3 6 4 2 1 0 10 12 14 16 18 20 22 24 26 28 30 -2 0 2 4 6 8 0 2
PGA Gain Setting
There is a gain boosting block before 12-bit ADC, which can muliply PGA's output signal by 1.5 (3.5dB) or pass it. This is controled by gain mode of configuration register.
14
GAIN [Liner]
10
4
GAIN [dB]
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
BLOCK DIAGRAM
VDDA1 VSSA1
VDDA2
VSSA2
VDDD
VSSD
VBB
BGR
REFT VCOM
REFB MCTL2
RED R_VIN CDS CLAMP R_OFFSET[7:0] R_CLAMP[3:0]; For only SHA mode R_GAIN[4:0] REF GREEN CDS CLAMP G_OFFSET[7:0] G_CLAMP[3:0]; For only SHA mode G_GAIN[4:0] GAIN MODE B_VIN CLAMP B_OFFSET[7:0] B_CLAMP[3:0]; For only SHA mode B_GAIN[4:0] BLUE CDS PGA R_OFFSET[7:0] Configuration Register PGA MUX & G1.5 ADC 12 12 PGA
MCTL1 EXT_MCTL
G_VIN
8
D[11:0] /MPU[7:0]
CSB OEB RDB
R_OFFSET[7:0] G_OFFSET[7:0] B_OFFSET[7:0]
Input Offset Register (R,G,B)
8
MPU PORT
WRB AD[2] AD[1]
R_CLAMP[3:0], R_GAIN[4:0] G_CLAMP[3:0], G_GAIN[4:0] B_CLAMP[3:0], B_GAIN[4:0]
Gain & Clamp Level Register (R,G,B)
AD[0]
CDS1_CLK
CDS2_CLK
STRTLN
ADCCLK
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AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
Table: MPU Port Map Format A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Register Configuration Register Input Offset register PGA Gain Control Register CIS Clamp Control Register Reserved Reserved Reserved Reserved
2) Register Overview The MPU port map is accessed through pins A0, A1 and A2. See MPU port map format.(previous page) Configuration Register Bit 7 Clamp mode select1 Bit 6 Clamp mode select0 Bit 5 PGA Gain mode Bit 4 External Reference Bit 3 Color1 Bit 2 Color0 Bit 1 Single Channel Bit 0 CDS Enable
Single Channel Color Pointer Bit3 0 0 1 1 Bit2 0 1 0 1 Color Red Green Blue Reserved
Clamp Mode Selection Bit7 0 0 1 1 Bit6 0 1 0 1 Clamp Mode Line Clamp Pixel Clamp No Clamp Reserved
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BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
Input Offset Register MSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit 0
PGA Gain Control Register MSB Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 PGA4 Bit 3 PGA3 Bit 2 PGA2 Bit 1 PGA1 LSB Bit 0 PGA0
CIS Clamp Control Register MSB Bit 7 Bit 6 Bit 5 Bit 4 Reserved Bit 3 CCC3 Bit 2 CCC2 Bit 1 CCC1 Reserved Reserved Reserved * CCCn: CIS Clamp Control n MULTIPLEXER CONTROL MODE EXT_MCTL = "LOW" MCTL2 0 0 1 1 MCTL1 0 1 0 1 Color Red Green Blue Reserved LSB Bit 0 CCC0
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AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
OVERRALL TRANSFER FUNCTION
The overall transfer function can be calculated as follows. if gain mode = 0, ADCout = [(Vin+Input_Offset)* PGA_Gain]/(2*REF)*4096, if gain mode = 1, ADCout = [(Vin+Input_Offset)* PGA_Gain * 1.5]/(2*REF)*4096, where REF is equal to (REFT-REFB) and Input _Offset means the DAC value of the input offset register. The analog offset range of the input offset register is varied between 150mV and -150 mV. The 8-bit data format for the input offset register is straight binary coding. Thus, an all 'zeros' data word corresponds to -150 mV. An all 'ones' data word corresponds to 150 mV. To maximize the dynamic range of the ADC input, it is necessary to program the input offset register code to move the ADC code corresponding to the black level towards 'zero'. In case of processing CIS signal, 4-bit of the gain & clamp control register are allocated to control CIS clamp level. Like the input offset register, the 4-bit data format is straight binary coding. An all 'zeros' data word corresponds to 0.1 V and an all 'ones' data word corresponds to 1.5 V.
INPUT COUPLING CAPACITOR
Because of the DC offset present at the output of CCD, some kind of DC restoration is required. In case of CDS enable mode, to simplify input level shifting, a DC decoupling capacitor is used in conjuction with the internal input circuitry. The capacitor charging or discharging depends on the clamping time, the analog input resistance of the AFE and the output resistance of the circuit driving the coupling capacitor. The clamping time is typically (n*T), where n is the number of periods CDSCLK1 is asserted and T is the period of assertion. CDSCLK2 should not be asserted during clamping time. And, STRTLN must be low in line clamp mode for clamping operation. The analog input resistance of the AFE is equal to 1 k. The recommended input coupling capacitor is more than 0.01uF. Thus, to extend the clamping time, the time a transport motor moves the scanner carriage can be available, for example.
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BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
POWER-ON INITIALIZATION
CALIBRATION Decide clamp level for SHA mode (Refer to next page) Set PGA gain (Input offset = 0mV)
Write to configuration register Set CDS or SHA operation Set 3 or 1 channel mode Set color pointer Set clamp mode
Scan dark line
Write to PGA gain register Set to gain of one(00001)
Compute pixel offsets
Set input offset Write to input offset register Set to 0mV(10000000)
Set odd/even offset in back end
YES YES Set another color
Set another color NO
NO
Set gain/offset bus size in back end
Set external pixel offset in back end
Scan white line
Compute pixel gains in back end
YES
Adjust PGA gain
NO
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AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
CLAMP LEVEL DECISION FOR EACH INPUT
* * Assume that PGA gain = 1 This flow chart is not fixed, but recommended. User can modify this algorithm.
Write CIS clamp control register Set to (111)
Decrease CIS clamp control register by 1
Scan clamp level input
[Repeatedly, scan clamp level. Average ADC output]
NO
ADC output > 0 YES Scan dark line [MIN(ADC output) = Minimum value of all pixels]
YES
MIN(ADC output) > 204 NO
YES
[(100mV)/(4V) * 4096 - 1 = 102] MIN(ADC output) > 102 NO MIN(ADC output) >0 YES NO
Increase CIS clamp control register by 1
Decrease CIS clamp control register by 1 Scan dark line
Increase CIS clamp control register by 1
NO
MIN(ADC output) > 102 YES Increase CIS clamp control register by 1
Go to calibration
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BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
CORE EVALUATION GUIDE
0.1u
0.1u
0.1u
0.1u
BGR VSSA2 VDDA2 R_VIN G_VIN B_VIN VDDD VSSD VBB VSSA1 VDDA1
REFT
VCOM REFB EXT_MCTL MCTL1,MCTL2 D[11:0]
BL8531H
AD[2:0] CSB WRB RDB CDS1_CLK CDS2_CLK OEB ADCCLK
STRTLN
TIMING GENERATOR
MPU INTERFACE
MUX
DSP ASIC
MUX
Externally forced digital input/output
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AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
PACKAGE CONFIGURATION
The digital pins should be well decoupled to the analog ground plane.
50 0.1u 0.1u 0.1u 0.1u 0.01u BGR REFT VCOM 10u 0.1u
50
50
OEB
VDDD
STRTLN
VSSD
CDS1_CLK
50
REFB R_VIN 0.01u G_VIN
CDS2_CLK
ADCCLK
WRB
RDB D[6]
CSB AD[2] AD[1] AD[0]
50 B_VIN 0.01u 50 VDDA1 10u 0.1u VSSA1 VBB NC SPEEDUP STBY VDDA2 VSSA2 VDDO VSSO D[0] D[1] D[2] D[3] D[4] D[5] NC ITEST IBIAS
BL8531H AFE85 48 QFP
MCTL2 EXT_MCTL MCTL1 D[11] D[10] D[9] D[8] D[7]
0.1u 10u
:Analog Ground :Digital Ground
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BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
PACKAGE PIN DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Pin Name NC VDDA2 VSSA2 VSSO VDDO D[0]/MPU[0] D[1]/MPU[1] D[2]/MPU[2] D[3]/MPU[3] D[4]/MPU[4] D[5]/MPU[5] D[6]/MPU[6] D[7]/MPU[7] D[8] D[9] D[10] D[11] MCTL1 EXT_MUX I/O Type AP AG DG DP DB DB DB DB DB DB DB DB DB DB DB DB DI DI Not Connected Analog Power for A/D Converter Analog Ground for A/D Converter Output Buffer Ground Output Buffer Power Digital Output LSB/Register Input LSB Digital Output/Register Input Digital Output/Register Input Digital Output/Register Input Digital Output/Register Input Digital Output/Register Input Digital Output/Register Input Digital Output/Register Input MSB Digital Output Digital Output Digital Output Digital Output MSB Color Pointer for MUX Control MUX Control Mode Selection Low : by MCTL1, MCTL2 High : by Configuration Register Color Pointer for MUX Control Register Selection Pin Register Selection Pin Register Selection Pin Chip Selection (Active Low) Description
20 21 22 23 24
MCTL2 AD[0] AD[1] AD[2] CSB
DI DI DI DI DI
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AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
PACKAGE PIN DESCRIPTION (Continued)
Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Pin Name RDB WRB OEB ADCCLK CDS2_CLK CDS1_CLK STRTLN VDDD VSSD BGR VCOM REFT REFB R_VIN G_VIN B_VIN IBIAS VDDA1 VSSA1 VBB NC SPEEDUP STBY I/O Type DI DI DI DI DI DI DI DP DG AB AB AB AB AI AI AI AB AP AG AG DI DI Description Read Strobe (Active Low) Write Strobe (Active Low) Output Enable (Active Low) A/D Converter Clock Input CDS Data Clock Input CDS Reset Clock Input Start Line (Active Low) Digital Power Digital Ground Bandgap Reference Voltage Reference Middle Voltage Reference Top Voltage Reference Bottom Voltage Red Analog Input Green Analog Input Blue Analog Input Analog Test Pin (Floating) Analog Power Analog Ground Analog Ground Not Connected Test Pin ( Set to Low) Stand By (Power Down) Low = Normal High = Power Save Analog Test Pin (Floating)
48
ITEST
AB
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BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
USER GUIDE
CONFIGURATION It is necessary that output signal of analog front end be shading-compensated by back end logic block including subtracter and multiplier. Shading-Compensation Block
Memory
CCD/CIS
AFE
Subtracter Multiplier
Controller
Output Bus Controls CSB WRB RDB OEB 0 0 1 1 0 1 x 0 0 1 0 x MPU Output 0 1 x 1 Z 1 x x 0 ADC Output 1 x x 1 Z
DOUT MPU Input X x: Don't Care X: Unknown (Not recommended) Z: High Impedance
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AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
PHANTOM CELL INFORMATION
Pins of the core can be assigned externally (Package pins) or internally (internal ports) depending on design methods. The term "External" implies that the pins should be assigned externally like power pins. The term "External/internal" implies that the applications of these pins depend on the user.
VCOM
VDDA1
VDDA1
G MIN
VSSA1
VSSA1
R MIN
B MIN
BGR
REFB
REFT
IBIAS
VBB
VBB
CDS2_CLK CDS1_CLK
VSSD VSSD VDDD VDDD BL8531H 12-bit 6 MSPS AFE for Image Processor
VDDA2 VSSA2
ADCCLK STRTLN ITEST STBY SPEEDUP
VDDO VSSO MCTL2 MCTL1 EXT_MCTL
DO[10]
DO[11]
DO[0]
DO[1]
DO[2]
DO[3]
DO[4]
DO[5]
DO[6]
DO[7]
DO[8]
DO[9]
AD[0]
AD[1]
AD[2]
WRB
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OEB
RDB
CSB
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
Pin Name VDDA1 VSSA1 VDDA2 VSSA2 VDDD VSSD VDDO VSSO VBB R_VIN G_VIN B_VIN ADCCLK CDS1_CLK CDS2_CLK REFT REFB VCOM BGR IBIAS ITEST STBY SPEEDUP STRTLN EXT_MCTL MCTL1,2 OEB WRB RDB CSB AD[2:0] D[11:0]
Pin Usage External External External External External External External External External External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal - Test pins
Pin Layout Guide - Maintain the large width of lines as far as the pads. - Place the port positions to minimize the length of power lines. - Do not merge the analog powers with other power from other blocks. - Use good power and ground source on board.
- Do not overlap with digital lines. - Maintain the shortest path to pads. - Separate from all other analog signals
- Maintain the larger width and the shorter length as far as the pads. - Separate from all other digital lines.
- SPEEDUP = set to "LOW"
- Separated from the analog clean signals if possible. - Do not exceed the length by 1,000um.
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AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
FEEDBACK REQUEST
It should be quite helpful to our AFE core development if you specify your system requirements on AFE in the following characteristic checking table and fill out the additional questions. We appreciate your interest in our products. Thank you very much. Characteristics Resolution Signal-to-Noise & Distortion Ratio Conversion Rate 3-Channel with CDS 1-Channel with CDS Differential Nonlinearity Integral Nonlinearity Unipolar Offset Error Gain Error Anlog Input Full-Scale Input Power Supply Analog Voltage Digital Voltage Power Consumption Temperature Range DNL INL MSPS MSPS LSB LSB %FSR %FSR Vp-p SNDR Symbol Min Typ Max Unit Bits dB Comment
VDDA VDDD
V V
mW C
What do you want to choose as power supply voltages? For example, the analog VDD needs to be 5V. The digital VDD can be 3.3V/5V. Which modes of AFE do you use for overall system ? (Refer to page 9) For example: 3channel operation with CDS / 3channel SHI(CIS) operation 1channel operation with CDS / 1channel SHI(CIS) operation Would you define the gain range and input offset range ? Could you explain external/internal pin configurations as required? Should the bus interface be compatible with TTL ? When STRTLN is low, the internal circuit is reset on the rising edge of ADCCLK. Which channel is multiplexer switched to on the next rising edge of ADCCLK, after STRTLN goes high? If possible, present other requirements below.
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BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
HISTORY CARD
Version ver 1.0 ver 1.1 ver 2.0 Date 98.11 99.1 02.4.16 Modified Items Original version published (preliminary) Release the formal data sheet Change the data sheet format, phantom information added Comments
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AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
NOTES
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