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54ACT573 Octal Latch with TRI-STATE Outputs
August 1998
54ACT573 Octal Latch with TRI-STATE (R) Outputs
General Description
The 'ACT573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The 'ACT573 is functionally identical to the 'ACT373 but has inputs and outputs on opposite sides.
Features
n ICC and IOZ reduced by 50% n Inputs and outputs on opposite sides of package allowing easy interface with microprocessors n Useful as input or output port for microprocessors n Functionally identical to 'ACT373 n TRI-STATE outputs for bus interfacing n Outputs source/sink 24 mA n 'ACT573 has TTL-compatible inputs n Standard Military Drawing (SMD) -- 'ACT573: 5962-87664
Logic Symbols
IEEE/IEC
DS100332-1
DS100332-2
Pin Names D0-D7 LE OE O0-O7 Data Inputs
Description Latch Enable Input TRI-STATE Output Enable Input TRI-STATE Latch Outputs
TRI-STATE (R) is a registered trademark of National Semiconductor Corporation. FACT (R) is a registered trademark of Fairchild Semiconductor Corporation.
(c) 1998 National Semiconductor Corporation
DS100332
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Connection Diagrams
Pin Assignment for DIP and Flatpak
Pin Assignment for LCC
DS100332-4
DS100332-3
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Functional Description
The 'ACT573 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.
Truth Table
Inputs OE L L L H LE H H L X D H L X X Outputs On H L O0 Z
H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
Logic Diagram
DS100332-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) -0.5V to +7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V
Junction Temperature (TJ) CDIP
175C
Recommended Operating Conditions
Supply Voltage (VCC) 'ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACT Minimum Input Edge Rate (V/t) 'ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 4.5V to 5.5V 0V to VCC 0V to VCC -55C to +125C
50 mA 50 mA -65C to +150C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT (R) circuits outside databook specifications.
DC Characteristics for 'ACT Family Devices
Symbol Parameter VCC (V) 54ACT TA = -55C to +125C Guaranteed Limits VIH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 2.0 2.0 0.8 0.8 4.4 5.4 (Note 2) VIN = VIL or VIH 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 3.70 4.70 0.1 0.1 (Note 2) VIN = VIL or VIH 4.5 5.5 IIN IOZ ICCT IOLD IOHD Maximum Input Leakage Current Maximum TRI-STATE Leakage Current Maximum ICC/Input (Note 3) Minimum Dynamic Output Current 5.5 5.5 50 -50 mA mA VOLD = 1.65V Max VOHD = 3.85V Min 5.5 1.6 mA 5.5 5.5 0.50 0.50 V A A IOL 24 mA 24 mA VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC - 2.1V V V IOH -24 mA -24 mA IOUT = 50 A V or VCC - 0.1V V IOUT = -50 A V VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V Units Conditions
VIL
VOH
1.0 5.0
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DC Characteristics for 'ACT Family Devices
Symbol Parameter VCC (V)
(Continued)
54ACT TA = -55C to +125C Guaranteed Limits
Units
Conditions
ICC
Maximum Quiescent Supply Current
5.5
80.0
A
VIN = VCC or GND
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: ICC for 54ACT @ 25C is identical to 74ACT @ 25C.
AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 5) tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Dm to On Propagation Delay Dn to On Propagation Delay LE to On Propagation Delay LE to On Output Enable Time Output Enable Time Output Disable Time Output Disable Time 5.0 5.0 5.0 5.0 1.5 1.5 1.5 1.5 11.5 11.0 13.5 10.5 ns ns ns ns 5.0 1.5 12.0 ns 5.0 1.5 13.0 ns 5.0 1.5 13.5 ns 5.0 1.5 54ACT TA = -55C to +125C CL = 50 pF Min Max 13.5 ns Units Fig. No.
Note 5: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
VCC Symbol Parameter (V) (Note 6) 54ACT TA = -55C to +125C CL = 50 pF Guaranteed Minimum ts th tw Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE LE Pulse Width, HIGH 5.0 5.0 ns
Note 6: Voltage Range 5.0 is 5.0V 0.5V
Fig. Units No.
5.0 5.0
4.5 1.0
ns ns
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Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 5.0 25.0 Units pF pF Conditions VCC = OPEN VCC = 5.0V
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Physical Dimensions
inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A
20-Lead Ceramic Flatpak (F) NS Package Number W20A
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54ACT573 Octal Latch with TRI-STATE Outputs
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