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| CXP858P56A CMOS 8-bit Single Chip Microcomputer Description The CXP858P56A is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time-base timer, closed caption decoder, data slicer, on-screen display function, I2C bus interface, PWM output, remote control reception circuit, HSYNC counter and watchdog timer as well as basic configuration like 8-bit CPU, PROM, RAM and I/O port. Also this IC provides a power-on reset function and sleep function that enables to lower power consumption. The CXP858P56A is the PROM-incorporated version of the CXP85856A with built-in mask ROM. This provides the additional feature of being able to write directly into the program (also into the OSD character ROM or caption character ROM possible). Thus, it is most suitable for evaluation use during system development and for small-quantity production. 64 pin SDIP (PIastic) 64 pin QFP (PIastic) Structure Silicon gate CMOS IC Features * A wide instruction set (213 instructions) which covers various types of data - 16-bit operation/multiplication and division/Boolean bit operation instructions * Minimum instruction cycle 333ns at 12MHz operation * Incorporated PROM 56K bytes (Programming) 4.5K bytes (OSD) 3K bytes (Caption) * Incorporated RAM 2176 bytes (Excludes the closed caption decoder and on-screen display VRAM) * Peripheral functions - A/D converter 8-bit 6-channel successive approximation method (Conversion time of 26.7s at 12MHz) - Serial interface 8-bit clock sync type, 1 channel - Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer - Closed caption decoder Incorporated data slicer, conforming to FCC (EDS supported), 8 x 13 dots, 192 character types, 15 character colors, 4 lines x 34 characters, italic, underline, vertical scrolling, 15 frame background colors/half blanking - On-screen display (OSD) function 12 x 16 dots, 192 character types, 15 character colors, 2 lines x 24 characters, 8 frame background colors/half blanking, 15 background colors on full screen/half blanking, edging and vertical scrolling for every line, jitter elimination circuit, sprite OSD, 12 x 16 dots, 1 screen, 8 colors for every dot - I2C bus interface - PWM output 8 bits, 8 channels - Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO - HSYNC counter 2 channels - Watchdog timer * Interruption 15 factors, 15 vectors, multi-interruption possible * Standby mode Sleep * Package 64-pin plastic SDIP/QFP urchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conform to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E97738-PS Block Diagram N I T0 N I T1 N I T2 XTAL MP VDD Vss Vpp R ST LFC 1 VI N SPC 700 C PU C O R E 8 LFC 2 C ap D ATA SLI ER C C LO C K G EN ER ATO R ^ SYSTEM C O N TR O L PA0`PA7 PO R T A 7 C C D EC O D ER C VDD C Vss 2 EXTAL PR O M 56K BYTES R AM 2176 BYTES 2 N I TER R U PT C O N TR O LLER O N SC R EEN D I SPLAY PO R T B 3 PB0`PB6 YM H SYN C VSYN C PR ESC ALER ^ TI E BASE TI ER M M PO R T C XLC EXLC R G B I YS 8 PC 0`PC 7 RM C R EM O C O N FI FO PO R T E H SC 0 H SYN C C O U N TER 0 H SC 1 H SYN C C O U N TER 1 2 I C BU S I TER FAC E U N I N T 8BI PW M T AN 0`AN 5 6 A^D C O N VER TER 8 SD A0 SD A1 SC L0 SC L1 PW M 0`PW M 7 PO R T F -2- W ATC H D O G TI ER M SI SO SC K SER I I TER FAC E U N I AL N T EC 8BI TI ER ^C O U N TER 0 TM PO R T D 8 PD 0`PD 7 3 PE0`PE2 TO 8BI TI ER 1 TM 8 PF0`PF7 CXP858P56A CXP858P56A Pin Assignment (Top View) 64-pin SDIP PC3 PC2 PC1 PC0 EC/PD7 RMC/PD6 HS1/PD5 HS0/PD4 SI/PD3 SO/PD2 SCK/PD1 INT2/PD0 HSYNC/PA7 VSYNC/PA6 RST Vss XTAL EXTAL PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 CVss LFC2 LFC1 VIN CVDD Cap INT1/PB6 PB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PC4 PC5 PC6 PC7 PF0/PWM0 PF1/PWM1 PF2/PWM2 PF3/PWM3 PF4/SCL0/PWM4 PF5/SCL1/PWM5 PF6/SDA0/PWM6 PF7/SDA1/PWM7 PE0/TO PE1 PE2/INT0 MP Vss VDD Vpp EXLC XLC YM YS I B G R PB0 PB1 PB2 PB3 PB4 Note) 1. Vpp (Pin 46) must be connected to VDD. 2. Vss (Pins 16 and 48) must be connected to GND. 3. MP (Pin 49) must be connected to GND. -3- CXP858P56A Pin Assignment (Top View) 64-pin QFP PD6/RMC PC0 PC2 64 63 62 61 60 59 58 57 56 55 54 53 52 HS1/PD5 HS0/PD4 SI/PD3 SO/PD2 SCK/PD1 INT2/PD0 HSYNC/PA7 VSYNC/PA6 RST Vss XTAL EXTAL PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 CVss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PF3/PWM3 PF4/SCL0/PWM4 PF5/SCL1/PWM5 PF6/SDA0/PWM6 PF7/SDA1/PWM7 PE0//TO PE1 PE2/INT0 MP Vss VDD Vpp EXLC XLC YM YS I B G PC3 PC4 LFC2 CVDD INT1/PB6 PB5 PB4 PB2 VIN PF0/PWM0 LFC1 PB0 PF1/PWM1 PD7/EC PC5 PC6 PC7 Note) 1. Vpp (Pin 40) must be connected to VDD. 2. Vss (Pins 10 and 42) must be connected to GND. 3. MP (Pin 43) must be connected to GND. -4- PB3 PB1 Cap R PF2/PWM2 PC1 CXP858P56A Pin Description Symbol PA0/AN0 to PA5/AN5 PA6/VSYNC PA7/HSYNC PB0 to PB5 PB6/INT1 I/O I/O/Analog input I/O/Input I/O/Input I/O I/O/Input (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) Description Analog inputs to A/D converter. (6 pins) OSD display vertical sync signal input. OSD display horizontal sync signal input. (Port B) 7-bit I/O port. I/O can be set in a unit of single bits. (7 pins) External interruption request input. Active at the falling edge. (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) External interruption request input. Active at the falling edge. (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA synk current. (8 pins) Serial clock I/O. Serial data output. Serial data input. HSYNC counter (CH0) input. HSYNC counter (CH1) input. Remote control reception circuit input. External event input for timer/counter. (Port E) 3-bit I/O port. I/O can be set in a unit of single bits. (3 pins) (Port F) 8-bit output port and large current (12mA) N-ch open drain output. Lower 4 bits are medium drive voltage (12V);upper 4 bits are 5V drive. (8 pins) Rectangular wave output for timer/counter. PC0 to PC7 I/O PD0/INT2 PD1/SCK PD2/SO PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC PE0/TO PE1 PE2/INT0 PF0/PWM0 to PF3/PWM3 PF4/SCL0/PWM4 PF5/SCL1/PWM5 PF6/SDA0/PWM6 PF7/SDA1/PWM7 R, G, B, I, YS, YM I/O/Input I/O/I/O I/O/Output I/O/Input I/O/Input I/O/Input I/O/Input I/O/Input I/O/Output I/O I/O/Input Input for external interruption request. Active at the falling edge. 8-bit PWM outputs. (8 pins) Transfer clock I/O for I2C bus interface. (2 pins) Transfer data I/O for I2C bus interface. (2 pins) Output/Output Output/I/O Output/I/O Output 6-bit OSD display outputs. (6 pins) -5- CXP858P56A Symbol EXLC XLC VIN Cap LFC1, LFC2 CVDD CVSS EXTAL XTAL RST MP Vpp VDD Vss Input Input I/O Description OSD display clock oscillation I/O. Oscillator frequency is determined by the external L and C. External composite video signal input. Input a 2Vp-p signal via a capacitor. Output Input -- -- Connects a capacitor for the data slicer between Cap and CVSS. Connects a capacitor for the PLL circuit LPF between LFC1 and LFC2. Positive power supply for data slicer. GND for data slicer. Connects a crystal for system clock oscillation. When an external clock is supplied, input it to EXTAL and leave XTAL open. System reset; active at Low level. I/O pin. Outputs a Low level when the power is turned on and the power-on reset function operates. Test mode input. Must be connected to GND. Positive power supply for internal PROM writing. Under normal conditions, connect to VDD. Positive power supply. GND. Connect two VSS pins to GND. Output I/O Input -6- CXP858P56A Input/Output Circuit Format for Pins Pin Port A Port A data Circuit format When reset Port A direction IP PA0/AN0 to PA5/AN5 "0" when reset Data bus RD (Port A) Port A function selection "0" when reset A/D converter Input protection circuit Hi-Z 6 pins Port A Input multiplexer Port A data Port A direction "0" when reset IP PA6/VSYNC PA7/HSYNC Data bus RD (Port A) Hi-Z Schmitt input VSYNC, HSYNC 2 pins Port B Port C Ports B, C data Input polarity "0" when reset PB0 to PB5 PB6/INT1 PC0 to PC7 Data bus Ports B, C direction "0" when reset IP Hi-Z RD (Ports B, C) INT1 Schmitt input 15 pins -7- CXP858P56A Pin Port D Circuit format When reset Port D data PD0/INT2 PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC Port D direction "0" when reset Schmitt input Data bus RD (Port D) IP Hi-Z 6 pins INT2, SI, HS0, HS1, RMC, EC Large current 12mA Port D SCK, SO Serial output enable Port D data PD1/SCK PD2/SO Port D direction "0" when reset Data bus Schmitt input IP Hi-Z RD (Port D) SCK only 2 pins Port E Large current 12mA TO Port E function selection "1" when reset PE0/TO PE1 PE2/INT0 Port E data "1" when reset for PE0, 1 Port E direction "1" when reset for PE0, 1 "0" when reset for PE2 Data bus RD (Port E) INT0 Schmitt input only for PE2 IP PE0, PE1: High level PE2: Hi-Z 3 pins -8- CXP858P56A Pin Port F PWM0 to PWM3 Circuit format When reset PF0/PWM0 to PF3/PWM3 Port F data "1" when reset Port F function selection 12V drive Large current 12mA Hi-Z 4 pins Port F "0" when reset SCL, SDA I2C output enable PF4/SCL0/PWM4 PF5/SCL1/PWM5 PF6/SDA0/PWM6 PF7/SDA1/PWM7 PWM4 to PWM7 Port F data "1" when reset Port F function selection "0" when reset SCL, SDA (I2C circuit) Schmitt input IP Hi-Z BUS SW To internal I2C pins (SCL1 for SCL0) Large current 12mA 4 pins R G B I YS YM 6 pins R, G, B, I, YS, YM Output polarity "0" when reset Output becomes active by data writing to output polarity register. Hi-Z EXLC XLC EXLC IP Oscillator control Oscillation halted XLC IP OSD display clock 2 pins -9- CXP858P56A Pin Circuit format When reset EXTAL XTAL * Diagram shows the circuit composition during oscillation. EXTAL IP * Feedback resistor is removed during stop mode. (This device does not enter the stop mode.) Oscillation XTAL 2 pins Pull-up resistor RST Schmitt input Low level From power-on reset circuit 1 pin - 10 - CXP858P56A Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Medium drive output voltage High level output current High level total output current Symbol VDD Vpp VIN VOUT VOUTP IOH IOH IOL Low level output current IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation IOL Topr Tstg PD 20 100 -10 to +75 -55 to +150 1000 600 mA mA C C mW mW Ratings -0.3 to +7.0 -0.3 to +13.0 -0.3 to +7.01 -0.3 to +7.01 -0.3 to +15.0 -5 -50 15 Unit V V V V V mA mA mA (Vss = 0V reference) Remarks Incorporated PROM PF0 to PF3 pins Total of all output pins Ports excluding large current outputs (value per pin) Large current output port (value per pin)2 Total of all output pins SDIP-64P-01 QFP-64P-L01 1 VIN and VOUT should not exceed VDD + 0.3V. 2 The large current output port is Port D (PD) and Port F (PF). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Symbol Min. 4.5 VDD Supply voltage 3.5 2.5 Vpp Data slicer supply voltage High level input voltage CVDD VIH VIHS VIHEX VIL Low level input voltage Operating temperature VILS VILEX Topr Max. 5.5 5.5 5.5 Unit V V V V V V V V V V V C (Vss = 0V reference) Remarks Guaranteed operation range for 1/2 and 1/4 frequency dividing clocks Guaranteed operation range for 1/16 frequency dividing clock or sleep mode Guaranteed data hold range for stop mode1 6 5 2 3 EXTAL pin4 2 3 EXTAL pin4 Vpp = VDD 4.5 0.7VDD 0.8VDD VDD - 0.4 0 0 -0.3 -10 5.5 VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.4 +75 1 This device does not enter the stop mode. 2 PA, PB, PC, PE0 to PE1, SCL0 to SCL1, SDA0 to SDA1 pins. 3 INT2, SCK, SO, SI, HS0, HS1, RMC, EC, INT1, HSYNC, VSYNC, RST pins. 4 Specifies only during external clock input. 5 CVDD and VDD should be set to the same voltage. 6 Vpp and VDD should be set to the same voltage. - 11 - CXP858P56A DC Characteristics Item High level output voltage Symbol (Ta = -10 to +75C, Vss = 0V reference) Pin PA to PD, PE, R, G, B, I, YS, YM PA to PD, PE, R, G, B, I, YS, YM, PF0 to PF3, RST1 Condition VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 4.5V, IOL = 3.0mA VDD = 4.5V, IOL = 4.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V RST2 PA to PE, HSYNC, VSYNC, R, G, B, I, YS, YM, RST2 PF0 to PF3 PF4 to PF7 SCL0: SCL1 SDA0: SDA1 VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VI = 0, 5.5V VDD = 5.5V, VOH = 12.0V VDD = 5.5V, VOH = 5.5V VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V 1/2 frequency dividing clock operation VDD = 5.5V 12MHz crystal oscillation (C1 = C2 = 15pF) VDD3 Sleep mode VDD = 5.5V 12MHz crystal oscillation (C1 = C2 = 15pF) Stop mode4 VDD = 5.5V Termination of 12MHz crystal oscillation VDD = 5.5V 0.5 -0.5 -1.5 Min. 4.0 3.5 0.4 0.6 1.5 0.4 0.6 40 -40 -400 10 50 10 120 Typ. Max. Unit V V V V V V V A A A A A A VOH Low level output voltage VOL PD, PF PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) IIHE Input current IIHL IILR I/O leakage current IIZ EXTAL Open drain output ILOH leakage current (in N-ch Tr OFF state) I2C bus switch connection impedance RBS (in output Tr OFF state) IDD 43 55 mA Supply current IDDSL 2.5 5.5 mA IDDST -- -- -- A ICVDD Input capacitance CIN CVDD -- 5.0 10 10.0 20 mA pF PA to PE, SCL, SDA, 1MHz clock EXLC, EXTAL, VIN, 0V for no-measured pins RST 1 Specifies RST pin only when the power-on reset circuit is selected with mask option. 2 For RST pin, specifies the input current when pull-up resistance is selected, and specifies the leakage current when non-resistance is selected. 3 When all output pins are left open. Specifies only when the OSD oscillation is halted. 4 This device does not enter the stop mode. - 12 - CXP858P56A AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall times Event counter input clock pulse widtth Event counter input clock rise and fall times Symbol fC Pin XTAL EXTAL EXTAL EXTAL EC EC (Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig 1, Fig 2 External clock drive Fig. 3 Fig. 3 Min. Typ. 12.0 Max. Unit MHz ns ns ns 20 ms tXL, tXH tCR, tCF tEH, tEL tER, tEF 37.5 200 tsys1 + 50 1 Indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Fig. 1. Clock timing 1/fc VDD - 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 2. Clock applied condition Crystal oscillation Ceramic oscillation External clock EXTAL XTAL EXTAL XTAL C1 C2 OPEN Fig. 3. Event count clock timing 0.8VDD EC 0.2VDD tEH tEF tEL tER - 13 - CXP858P56A (2) Serial transfer Item SCK cycle time SCK High and Low level widths SI input setup time (for SCK ) SI hold time (for SCK ) SCK SO delay time Symbol Pin SCK (Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Output mode SCK SCK input mode SCK output mode SI SCK input mode SCK output mode SI SCK input mode SCK output mode SO SCK input mode SCK output mode Min. 1000 8000/fc 400 4000/fc - 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL. Fig. 4. Serial transfer timing tKCY tKL tKH 0.8VDD SCK 0.2VDD tSIK tKSI 0.8VDD SI Input data 0.2VDD tKSO 0.8VDD SO 0.2VDD Output data - 14 - CXP858P56A (3) A/D converter characteristics Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog input voltage VZT1 VFT2 Symbol Pin (Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Min. Typ. Max. 8 3 Ta = 25C VDD = 5.0V Vss = 0V -10 4910 160/fADC3 12/fADC3 10 4970 70 5030 Unit Bits LSB mV mV s s VDD V tCONV tSAMP VIAN AN0 to AN5 0 Fig. 5. Definitions of A/D converter terms FFh FEh Digital conversion value 1 Value at which the digital conversion value changes from 00h to 01h and vice versa. 2 Value at which the digital conversion value changes from Linearity error FEh to FFh and vice versa. 3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F9h) and bits 7 (PCK1) and 6 (PCK0) of the clock control register (CLC: 00FEh). 01h 00h VZT Analog input VFT CKS PCK1, 0 00 ( = fEX/2) 01 ( = fEX/4) 11 ( = fEX/16) 0 (/2 selection) fADC = fC/2 fADC = fC/4 fADC = fC/16 1 ( selection) fADC = fC fADC = fC/2 fADC = fC/8 - 15 - CXP858P56A (4) Interruption, reset input Item External interruption High and Low level widths Reset input Low level width (Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin INT0 INT1 INT2 RST Condition Min. 1 32/fc Max. Unit s s tIH tIL tRSL Fig. 6. Interruption input timing tIH INT0 INT1 INT2 (falling edge) tIL 0.8VDD 0.2VDD Fig. 7. RST input timing tRSL RST 0.2VDD (5) Power-on reset Item Power supply rise time Power supply cutt-off time Symbol Pin VDD (Ta = -10 to +75C, Vss = 0V reference) Condition Power-on reset Repeated power-on reset Min. 0.05 1 Max. 50 Unit ms ms tR tOFF Fig. 8. Power-on reset VDD 4.5V 0.2V 0.2V tR Take care when turning the power on. tOFF - 16 - CXP858P56A (6) I2C bus timing Item SCL clock frequency Bus-free time before starting transfer Hold time for starting transfer Clock Low level width Clock High level width Setup time for repeated transfers Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion (Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol fSLC Pin SCL SDA, SCL SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL 4.7 Condition Min. 0 4.7 4.0 4.7 4.0 4.7 01 250 1 300 Max. 100 Unit kHz s s s s s s ns s ns s tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO 1 The data hold time should be 300ns or more because the SCL rise time (300ns Max.) is not included in it. Fig. 9. I2C bus transfer timing SDA tBUF tR SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH tSU; DAT St tSU; STO P tF tHD; STA Fig. 10. I2C device recommended circuit I2C device RS SDA0 (or SDA1) SCL0 (or SCL1) RS RS I2C device RS RP RP * A pull-up resistor (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). * The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300 or less) can be used to reduce spike noise caused by CRT flashover. - 17 - CXP858P56A (7) OSD timing Item OSD clock frequency HSYNC pulse width HSYNC after-write rise and fall times VSYNC before-write rise and fall times (Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol fOSC Pin EXLC XLC HSYNC HSYNC VSYNC Condiiton Fig. 12 Fig. 11 Fig. 11 Fig. 11 Min. 4 1.2 200 1.0 Max. 16.5 Unit MHz s ns s tHWD tHCG tVCG Fig. 11. OSD timing tHWD tHCG HSYNC For OSD I/O polarity register (OPOL: 01FDh) bit 7 at "0" 0.8VDD 0.2VDD tVCG VSYNC For OSD I/O polarity register (OPOL: 01FDh) bit 6 at "0" 0.8VDD 0.2VDD Fig. 12. LC oscillation circuit connection EXLC XLC R1 L C1 C2 1 The XLC series resistor can reduce the frequency of occurrence of the undersired radiation. - 18 - CXP858P56A (8) Data slicer external circuit Item Symbol Pin VIN (Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Min. Typ. 0.1 Max. Unit F Remarks The B characteristic or more of temperature characteristics is recommended. The B characteristic or more of temperature characteristics is recommended. The B characteristic or more of temperature characteristics is recommended. VIN pin coupling capacitance CVIN Cap pin capacitance Ccap Cap 4700 pF PLL low-pass filter capacitance CLPF LFC1, LFC2 0.47 2.0 F Vp-p Composite video signal input Video In VIN Fig. 13. Data slicer external recommeded circuit 5.0V CVDD LFC2 CLPF LFC1 R1 CVIN VIN Video In C1 R2 Cap Ccap CVss [Recommended Constant] R1 = 220 (error: 5%; allowable power dissipation: 1/8W or more) R2 = 1M (error: 5%; allowable power dissipation: 1/8W or more) C1 = 1200pF (ceramic), the B characteristic or more of temperature characteristics is recommended. - 19 - CXP858P56A Appendix Fig. 14. SPC700 Series recommended oscillation circuit (i) EXTAL XTAL Rd C1 C2 Manufacturer RIVER ELETEC CO., LTD. KINSEKI LTD. Model HC-49/U03 HC-19/U (-S) fc (MHz) 12.0 12.0 C1 (pF) 5 15 C2 (pF) 5 15 Rd () 01 01 Circuit example (i) (i) 1 The XTAL series resistor can reduce the effect of electrostatic discharge noise. Products List Option item Package Program ROM capacity Reset-pin pull-up resistor Power-on reset circuit Font data Mask 64-pin plastic SDIP/QFP 40/48/56K bytes Existent/Non-existent Existent/Non-existent User specified CXP858P56AS-1CXP858P56AQ-164-pin plastic SDIP/QFP PROM 56K bytes Existent Existent User specified (PROM)2 2 The font data for the one-time PROM version can be written in the same way as for the program. - 20 - CXP858P56A Fig. 15. Characteristics curves IDD vs. VDD (fc = 12MHz, Ta = 25C, Typical) 100 1/2 frequency dividing mode 1/4 frequency dividing mode 1/16 frequency dividing mode 50 IDD vs. fc (VDD = 5V, Ta = 25C, Typical) 45 1/2 frequency dividing mode 40 35 IDD - Supply current [mA] IDD - Supply current [mA] 10 30 1/4 frequency dividing mode 25 Sleep mode 20 1/16 frequency dividing mode 1 15 10 5 Sleep mode 0 0.1 3 4 5 6 VDD - Supply voltage [V] 4 8 fc - System clock [MHz] 12 16 Parameter curve for OSD oscillation L vs. C (Theoretically calculated value) 100 L - Inductance [H] 10 10MHz 12MHz 14MHz 16MHz fOSC = 0 50 C1, C2 - Capacitance [pF] 100 1 2 LC C = C1//C2 - 21 - CXP858P56A Package Outline Unit: mm 64PIN SDIP (PLASTIC) 750mil + 0.4 57.6 - 0.1 64 33 19.05 + 0.3 17.1 - 0.1 + 0.1 0.05 0.25 - 0 to 15 32 0.5 0.1 0.9 0.15 1 1.778 PACKAGE STRUCTURE MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-64P-01 SDIP064-P-0750-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 8.6g 64PIN QFP(PLASTIC) 23.9 0.4 + 0.4 20.0 - 0.1 51 33 3 MIN 0.5 MIN + 0.4 4.75 - 0.1 + 0.1 0.15 - 0.05 0.15 52 32 17.9 0.4 + 0.4 14.0 - 0.1 64 20 + 0.2 0.1 - 0.05 1 1.0 + 0.15 0.4 - 0.1 + 0.35 2.75 - 0.15 0.12 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 1.5g - 22 - 0.8 0.2 19 16.3 |
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