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ZILOG
SERIAL COMMUNICATION CONTROLLER
PRODUCT BRIEF
Z85C30
CMOS SCC SERIAL COMMUNICATION CONTROLLER
FEATURES
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Low Power CMOS Two Independent, 0 to 4.0 Mbit/sec, Full-Duplex Channels, each with a Separate Crystal Oscillator, Baud Rate Generator, and Digital Phase-Locked Loop for Clock Recovery. Multi-Protocol Operation under Program Control; Programmable for NRZ, NRZI, or FM Data Encoding. Asynchronous Mode with Five to Eight Bits and One, One and One-Half, or Two Stop Bits Per Character; Programmable Clock Factor; Break Detection and Generation; Parity, Overrun, and Framing Error Detection. Supports T1 Digital Trunk Clock Speeds: 8, 10 and 16 MHz
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New programmable WR' (write register 7 prime) to enable new features Improvements to support SDLC mode of synchronous communication: - Improve functionality to ease sending back-to-back frames - Automatic SDLC opening Flag transmission* - Automatic Tx Underrun/EOM Latch reset in SDLC mode* - Automatic /RTS deactivation* - TxD pin forced "H" in SDLC NRZI mode after closing flag* - Complete CRC reception* - Improved response to Abort sequence in status FIFO - Automatic Tx CRC generator preset/reset - Extended read for write registers* - Write data set-up timing improvement Improved AC Timing - Three to 3.6 PCLK access recovery time - Programmable /DTR//REQ timing* - Write data to falling edge of /WR set-up time requirement is now eliminated - Reduced /INT timing Other features include: - Extended read function to read back the written value to the write registers* - Latching RR0 during read - RR0, bit D7 and RR 10, bit D6 now has reset default value.
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Synchronous Mode with Internal or External Character Synchronization on One or Two Synchronous Characters and CRC Generation and Checking with CRC-16 or CRC-CCITT Preset to Either 1s or 0s. SDLC/HDLC Mode with Comprehensive Frame-Level Control, Automatic Zero Insertion and Deletion, I-Field Residue Handling, Abort Generation and Detection, CRC Generation and Checking, SDLC Loop Mode Operation. Local Loopback and Auto Echo Modes Enhanced DMA Support: - 10 x 19-Bit Status FIFO - 14-Bit Byte Counter Available in 40-Pin PDIP and 44-Pin PLCC Packages.
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Some of the features listed above are available by default, and some of them (features with "*") are disabled on default to maintain compatibility with the existing SCC design, and "program to enable" through WR7'.
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ZILOG
SERIAL COMMUNICATION CONTROLLER
GENERAL DESCRIPTION
The Zilog Serial Communications Controller, Z85C30 SCC, is a pin and software compatible CMOS member of the SCC family introduced by Zilog in 1981. It is a dual channel, multi-protocol data communications peripheral that easily interfaces to CPU's non-multiplexed address/ data buses. The advanced CMOS process offers lower power consumption, higher performance, and superior noise immunity. The programming flexibility of the internal registers allows the SCC to be configured to satisfy a wide variety of serial communications applications. The many on-chip features such as baud rate generators, digital phase locked loops, and crystal oscillators dramatically reduce the need for external logic. Additional features including a 10x19-bit status FIFO and 14-bit byte counter were added to support high speed SDLC transfers using DMA controllers. The SCC handles asynchronous formats, synchronous byte-oriented protocols such as IBM Bisync, and synchronous bit-oriented protocols such as HDLC and IBM SDLC. This versatile device supports virtually any serial data transfer application (cassette, diskette, tape drives, etc.) The device can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The SCC also has facilities for modem controls in both channels. In applications where these controls are not needed, the modem controls can be used for general-purpose I/O. The daisy-chain interrupt hierarchy is also supported as is standard for Zilog peripheral components.
Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
The description on Z85C30 is applicable to the following parts: Z85C3008PSC Z85C3010PSC Z85C3016PSC Z85C3008VSC Z85C3010VSC Z85C3016VSC
(c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY, IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com
ZILOG
SERIAL COMMUNICATION CONTROLLER
GENERAL DESCRIPTION (Continued)
Transmit Logic Transmit Buffer Transmit MUX Data Encoding & CRC Generation TxDA
Channel A
Exploded View Receive and Transmit Clock Multipexer Digital Phase-Locked Loop Baud Rate Generator Crystal Oscillator Amplifier /CTSA /DCDA /SYNCA /RTSA /DTRA//REQA /TRxCA /RTxCA
Modem/Control Logic
Receive Logic Rec. Status Rec. Data Receive MUX FIFO 3 Byte FIFO 3 Byte CRC Checker, Data Decode & Sync Character Detection
RxDA
SDLC Frame Status FIFO 10 x 19
Internal Control Logic Databus Control
Channel A Register
Channel A
CPU & DMA Bus Interface /INT /INTACK Interrupt IEI Control IEO
Interrupt Control Logic
Channel B Register
Channel B
SCC Functional Block Diagram

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