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TEA7533
MONITOR AMPLIFIER
7 DIGITALLY PROGRAMMABLE GAINS IN STEPS OF 4.5dB ON/OFF POSITION LOW VOLTAGE (3.5V to 6.5V) POWER: >140mW at 5V; >250mW at 6.5V DESCRIPTION This 20 pins IC is designed for monitoring and loudspeaker telephone set and provides: a) signal amplification for monitoring (loudspeaker). b) antiacoustic feedback (antilarsen). c) antidistortion by automatic level adaptation. d) antilarsen adjustment (full duplex). e) antidistortion by automatic gain adaptation in current supply mode. f) service audio inputs with internal dedicated switches. FUNCTIONAL DESCRIPTION TEA7533 performs the following functions: The circuit amplifies the incoming signal and BLOCK DIAGRAM
IN2 3 GCTRL2 GCTRL1 EARPHONE IN1 2 0 dB TO -20 Vth = 0.6V ctrl R19 CAGC C19 VREF R7 C7 19 ctrl 10 A + VREF, 0.8V, 1.2V VOLTAGE & CURRENT REFERENCE 11 LOUT R10 C13
D93TL008
SO20 ORDERING NUMBER: TEA7533FP
feeds it to the loudspeaker. PG0, PG1 and PG2 inputs are used to set the loudspeaker gain in a range of 32dB to 5dB in 7 steps of 4.5dB. The TEA7533 inputs (PG0, PG1, PG2) allows also the loudspeaker to be cut-off, thus ensuring privacy of communication. The antilarsen (antiacoustic feedback) system is incorporated. The maximum power available on a 50 impedance loudspeaker is 140mW at 5V and 250mW at 6.5V.
IN3 20
SW 1
G0 18
G1 17
G2 16
PROG. LEVEL 0 dB TO -15 +
12 dB MAX
4
CL1 C4
5 12
CL2 LS1 C14 R14 C12
LS AMP 20 dB
14 6 13
LS2 VCC REF
HP 5V Supply VREF
MIC1
7
+ + -
VREF
C8 R8
MIC2
8 9 FAL C9 C10 R9 TC1 10
15 GND
TEA7533
September 1993
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TEA7533
PIN DESCRIPTION
N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol SW IN1 IN2 CL1 CL2 VCC MIC1 MIC2 FAL TC1 LOUT LS1 REF LS2 GND PG2 PG1 PG0 CAGC IN3 Switch control: IN2 or IN3 Audio Input AVG Controlled 2nd Audio input; No Anti-distortion Control Intermediate Receive Output (Decoupling capacitor) Intermediate Receive Input (Decoupling capacitor) Supply Voltage Microphone input 1 Microphone input 2 Antilarsen Filter Antilarsen Gain Set up Status Output, Digital Output. Loudspeaker Output1 Reference Voltage; (VCC - 0.7V/2) Loudspeaker Output2 Ground Digital Input; Loudspeaker Level Control Digital Input; Loudspeaker Level Control Digital Input; Loudspeaker Level Control Gain Control Filter Capacitor 3rd Audio Input Description
ABSOLUTE MAXIMUM RATINGS
Symbol VCC ICC VLOGIC Top Tstg Max. Supply Voltage Max Supply Current at t > 300ms Max Supply Current at t 300ms Voltage Level (logic pins) Operative Temperature Range Storage Temperature Range Parameter Test Conditions 7 100 150 -0.6/VCC+0.6 -20 to +70 -55 to +125 Unit V mA mA V C C
PIN CONNECTION (Top view)
SW1 IN1 IN2 CL1 CL2 Vcc MIC1 MIC2 FAL TC1
1 2 3 4 5 6 7 8 9 10
D93TL033
20 19 18 17 16 15 14 13 12 11
IN3 CAGC PG0 PG1 PG2 GND LS2 REF LS1 LOUT
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TEA7533
ELECTRICAL CHARACTERISTICS (Tamb = 25C, R BIAS = 60K; VG0 = VG1 = VG2 = H; Vin = 0Vrms; VTG1 = 0V; unless otherwise specified)
Symbol VCC ICC Vref Parameter Supply Voltage Supply Current Voltage Reference VCC = 5V Iref Current Available at Vref Source Sink - 1.72 - - 19 VTC1 = 0V; VIN = 60mVrms VCAGL = 0V PG2, H H H H L L L L PG1, PG0 H H H L L H L L H H H L L H L L VCC = 5V; PG0 = PG1 = PG2 = L VCC = 5V; PG0 = PG1 = PG2 = H Test Condition Min. 3.5 - - Typ. 5 0.75 1.6 (VCC 0.7)/2 2.15 30 400 20 Max. 6.5 1 2.1 - 2.6 - - 21 Unit V mA mA V A A dB
IN2 & IN3 AMPLIFIER SECTIONS GO G Final Stage Gain (VLS1 - VLS2)/VCL2 Loudspeaker Amplifier Gain (VLS1 - VLS2)/IN3 (or IN2)
G111 G110 G101 G100 G011 G010 G001 G000 VOFF LS DIN
Gain max Gain 1st step Gain 2nd step Gain 3rd step Gain 4th step Gain 5th step Gain 6th step Off step Output Offset
30 25.5 21 16.5 12.0 7.5 3 -50 4.5 6.5 29.5 - -17 -
31.5 27 22.5 18 13.5 9 4.5 -40 5 6.7 31.5 1 -15 4.5 - -
33 28.5 24 19.5 15 10.5 6 -30 50 2 2 34.5 2 -13 6.0 3 10
dB dB dB dB dB dB dB dB mV Vpp Vpp % % dB % dB % % %
G = G111; RLOAD = 50
Loudspeaker Dinamic (VLS1- VLS2) RLOAD = 50 VCC = 3.5V; THD = 4% VCC = 5V; THD = 4% Output Distortion VCC = 5V G = G111(32dB) SW = L; VOUT = 2Vrms SW = H; VOUT = 2Vrms VCAG (19) = VREF; VTC1 = 0V VIN1 = 45mVrms VIN = 45mVrms VCAGC = VREF; VTC1 = 0.8V
THD
IN1 AMPLIFIER SECTION G1 THD1 ALG1 ALTHD Loudspeaker Amplifier Gain (VLS1 - VLS2) / IN1 Distortion Antilarsen Attenuation on IN1 Chain Distortion with Antilarsen Active VIN1 = 80mV VIN1 = 560mV
IN1 ANTIDISTORTION SECTION
CAGC THD Distortion with AGC Control Active PG PGH Logic Interface PG0, PG1, PG2, SW= L, IN3 = ON Logical Input High
- -
0
-
0.4 x (VCC 0.7) VCC
V V
PGL
Logical Input Low
0.6 x (VCC 0.7) VIN = 0V VIN = VCC IN1, IN2, IN3, MIC1,MIC2 -1 -1 -
-
IPGL IPGH IBIAS
Input Current Low state Input Current High State Biasing Current Analog Inputs
17
+1 +1 100
A A mA
ANALOG INTERFACE
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TEA7533
ELECTRICAL CHARACTERISTICS (Continued)
Symbol ANTILARSEN SECTION GMIC VTC1 TH VTC1 LOW TC1 H TC1 L ILOUT L ILOUT H VLOUT L VLOUT H Microphone Amplifier Gain = VFAL/(VMIC1 - VMIC2) TC1 Threshold for -3dB attenuation on IN1 chain TC1 Level with Vmic = 0 Vrms High Thereshold of LOUT Comparator Low Thereshold of LOUT Comparator Output Current of Comparator LOUT Output Voltage of Comparator LOUT VLOUT < 0.4V VLOUT > 4.1V VTC1 = 1.5V; VLOUT = 0.5V VTC1 = 0.6V; VLOUT = 3.5V VTC1 = 1.5V VTC1 = 0.6V VIN = 4.5mVrms; f = 5KHz 19.5 0.55 0 1.1 - 5 - - 4.1 21 0.68 0.07 1.2 0.8 20 -1 0.08 4.33 22.5 0.75 0.2 - 0.9 - -0.5 0.4 - dB V V V V A A V V Parameter Test Condition Min. Typ. Max. Unit
TEST CIRCUIT
VREF 22nF VIN3 C20 20 V19 C19 150nF 19 R19 1M
R3 100K VIN2 I1 C1 22nF 1 V1 V4 C4 470nF ICC 15 4 3
R2 100K
22nF
R20 100K VIN1
C2 2
5 6
TEA7533
VCC
C6 1000F 9 R9 2K 10
13 C13 22F 8 C8 22nF 7 100K R7 R8
C9 33nF C10 220nF
R10 150K V10
11
12 C12 R14
14
16
17
18
C7 22nF VMIC1
100K
I11 470pF V12-V14
D93TL039
R12 50
VCC
VCC
VCC
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TEA7533
Figure 1: IN1 Channel - AGC Gain (Typical)
GAIN VLS1-VLS2 IN1 30 (dB) 28 26 24 22 20 18 16 60 14 12 10 8 6 0.05 0.15 0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95 V IN1(VRMS) 45 30 15 0 0.05 0.15 0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95 VIN1(VRMS)
D93TL034A
Figure 2: IN1 Channel (VCAGC - VREF)
VCAGCV REF 150 (mV) 135 120 105 90 75
D93TL035A
Figure 3: IN1 Channel - Distortion (Typical)
THD (%) 9 8 7 300Hz
D93TL036A
Figure 4: IN3 and IN2 Channels - Distortion
THD (%) 4.5 4.0 3.5
D93TL037A
6 3.0 5 1KHz 4 3 2 1 0 0.05 0.15 0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95 VIN1(V RMS) 2.0 1.5 1.0 0.5
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00
VLS1-VLS2(VRMS)
2.5 RLOAD=50
R LOAD=100
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TEA7533
Figure 5: Time Diagram for TC1 (Antilarsen) and LOUT.
TX PATH
ANTILARSEN OUTPUT (TC1)
1.2V 0.8V 0.6V LOUT HYSTERESIS ANTILARSEN THRESHOLD ANTILARSEN ON ANTILARSEN OFF
ANTILARSEN OFF
LOGIC OUTPUT (LOUT)
(*) SQUELCH ON
(*) SQUELCH OFF
(*) SQUELCH ON D93TL038
(*) SQUELCH FUNCTION CAN BE ACTIVATED EXTERNALLY BASED ON LOUT COMMAND
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TEA7533
SO20 PACKAGE MECHANICAL DATA
DIM. Min. A a1 a2 b b1 C c1 D E e e3 F L M S 7.4 0.5 12.6 10 1.27 11.43 7.6 1.27 0.75 8 (max.)
o
mm Typ. Max. 2.65 0.1 0.2 2.45 0.35 0.23 0.5 45 (typ.) 13.0 10.65 0.496 0.394
o
inch Min. Typ. Max. 0.104 0.004 0.008 0.096 0.014 0.009 0.020 0.019 0.013
0.49 0.32
0.510 0.419 0.050 0.450
0.291 0.020
0.300 0.050 0.030
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TEA7533
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support dev ices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.
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