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6-Bit Programmable 2-/3-/4-Phase Synchronous Buck Controller ADP3188
FEATURES
Selectable 2-, 3- or 4-phase operation at up to 1 MHz per phase 9.5 mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Active current balancing between all output phases Built-in power good/crowbar blanking supports on-the-fly VID code changes 6-bit digitally programmable 0.8375 V to 1.6 V output Programmable short-circuit protection with programmable latch-off delay
FUNCTIONAL BLOCK DIAGRAM
VCC 28 RAMPADJ 14 RT 13
ADP3188
EN 11 UVLO SHUTDOWN AND BIAS OSCILLATOR SET RESET EN 27 PWM1
GND 19
CMP DAC+150mV CSREF CURRENT BALANCING CIRCUIT CMP
CMP
RESET 2-/3-/4-PHASE DRIVER LOGIC RESET
26 PWM2
25 PWM3
DAC-250mV CMP PWRGD 10 DELAY RESET 24 PWM4 CURRENT LIMIT 23 SW1 ILIMIT 15 EN 22 SW2 21 SW3 20 SW4 CURRENT LIMIT CIRCUIT SOFT START 17 CSSUM 16 CSREF 18 CSCOMP
CROWBAR
APPLICATIONS
Desktop PC power supplies for Next-generation Intel(R) processors VRM modules
DELAY 12
GENERAL DESCRIPTION
The ADP3188 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. The part uses an internal 6-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.8375 V and 1.6 V. It uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing the construction of up to four complementary buck switching stages. The ADP3188 also includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current, so it is always optimally positioned for a system transient. The ADP3188 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power good output that accommodates on-the-fly output voltage changes requested by the CPU. The ADP3188 is specified over the commercial temperature range of 0C to 85C and is available in 28-lead, TSSOP and QSOP packages.
COMP 9
8 FB
PRECISION REFERENCE 7 FBRTN 1 2 3
VID DAC 4 5 6
04835-001
VID4 VID3 VID2 VID1 VID0 VID5
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADP3188
TABLE OF CONTENTS
Specifications..................................................................................... 3 Test Circuits....................................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function DescriptionS ............................ 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ........................................................................ 9 Start-Up Sequence........................................................................ 9 Master Clock Frequency.............................................................. 9 Output Voltage Differential Sensing .......................................... 9 Output Current Sensing .............................................................. 9 Active Impedance Control Mode............................................. 10 Current-Control Mode and Thermal Balance........................ 10 Voltage Control Mode................................................................ 10 Soft Start ...................................................................................... 10 Current-Limit, Short-Circuit, and Latch-Off Protection...... 11 Dynamic VID.............................................................................. 11 Power Good Monitoring ........................................................... 12 Output Crowbar ......................................................................... 13 Output Enable and UVLO ........................................................ 13 Application Information................................................................ 15 Setting the Clock Frequency ..................................................... 15 Soft Start and Current-Limit Latch-Off Delay Times ........... 15 Inductor Selection ...................................................................... 15 Designing an Inductor............................................................... 16 Selecting a Standard Inductor .............................................. 16 Output Droop Resistance.......................................................... 16 Inductor DCR Temperature Correction ................................. 17 Output Offset .............................................................................. 17 COUT Selection ............................................................................. 18 Power MOSFETs......................................................................... 18 Ramp Resistor Selection............................................................ 20 COMP Pin Ramp ....................................................................... 20 Current-Limit Setpoint.............................................................. 20 Feedback Loop Compensation Design.................................... 20 CIN Selection and Input Current di/dt Reduction.................. 22 Tuning the ADP3188 ................................................................. 23 DC Loadline Setting .............................................................. 23 AC Loadline Setting............................................................... 24 Layout and Component Placement.............................................. 26 General Recommendations....................................................... 26 Power Circuitry Recommendations ........................................ 26 Signal Circuitry Recommendations......................................... 26 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27
REVISION HISTORY
4/05--Rev. 0 to Rev. A Changes to Figure 10.........................................................................14 Changes to Ordering Guide .............................................................27 4/04--Revision 0: Initial Version
Rev. A | Page 2 of 28
ADP3188
SPECIFICATIONS
VCC = 12 V, FBRTN = GND, TA = 0C to 85C, unless otherwise noted.1 Table 1.
Parameter ERROR AMPLIFIER Output Voltage Range2 Accuracy Symbol VCOMP VFB Conditions Min 0.7 -9.5 Typ Max 3.1 +9.5 Unit V mV
Line Regulation Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate VID INPUTS Input Low Voltage Input High Voltage Input Current, Input Voltage Low Input Current, Input Voltage High Pull-Up Resistance Internal Pull-Up Voltage VID Transition Delay Time No CPU Detection Turn-Off Delay Time2 OSCILLATOR Frequency Range Frequency Variation
2 2
VFB IFB IFBRTN IO(ERR) GBW(ERR)
Relative to nominal DAC output, referenced to FBRTN, CSSUM = CSCOMP, Figure 2 VCC = 10 V to 14 V
14 FB forced to VOUT - 3% COMP = FB CCOMP = 10 pF
0.05 15.5 100 500 20 25
% 17 140 A A A MHz V/s V V A A k V ns ns
VIL(VID) VIH(VID) IIL(VID) IIH(VID) RVID
0.4 0.8 VID(X) = 0 V VID(X) = 1.25 V 35 0.9 400 400 -25 5 60 1.1 -35 15 85
VID code change to FB change VID code change to 11111 to PWM going low fOSC fPHASE
Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT-SENSE AMPLIFIER Offset Voltage
VRT VRAMPADJ IRAMPADJ VOS(CSA)
TA = 25C, RT = 250 k, 4-phase TA = 25C, RT = 115 k, 4-phase TA = 25C, RT = 75 k, 4-phase RT = 100 k to GND RAMPADJ - FB
0.25 155
1.9 -50 0 -1.75 -1.5 -50
200 400 600 2.0
4 245
2.1 +50 100 +1.75 +1.5 +50
MHz kHz kHz kHz V mV A mV mV nA MHz V/s V mV V A mV k A %
CSSUM - CSREF, Figure 3 TA = 25C to 85C, CSSUM - CSREF, Figure 3
Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Positioning Accuracy Output Voltage Range Output Current CURRENT-BALANCE CIRCUIT Common-Mode Range Input Resistance Input Current Input Current Matching
IBIAS(CSSUM) GBW(CSA) CCSCOMP = 10 pF CSSUM and CSREF Figure 4
10 10 0 -77 0.05 -80 500 -600 20 4 -5 +200 40 10 +5 2.7 -83 2.7
VFB ICSCOMP VSW(X)CM RSW(X) ISW(X) ISW(X)
SW(X) = 0 V SW(X) = 0 V SW(X) = 0 V
30 7
Rev. A | Page 3 of 28
ADP3188
Parameter CURRENT-LIMIT COMPARATOR Output Voltage Normal Mode Shutdown Mode Output Current, Normal Mode Maximum Output Current Current-Limit Threshold Voltage Current-Limit Setting Ratio DELAY Normal Mode Voltage DELAY Overcurrent Threshold Latch-Off Delay Time
2
Symbol
Conditions
Min
Typ
Max
Unit
VILIMIT(NM) VILIMIT(SD) IILIMIT(NM) VCL VDELAY(NM) VDELAY(OC) tDELAY IDELAY(SS) tDELAY(SS)
EN > 0.8 V, RILIMIT = 250 k EN < 0.4 V, IILIMIT = -100 A EN > 0.8 V, RILIMIT = 250 k VCSREF - VCSCOMP, RILIMIT = 250 k VCL/IILIMIT RDELAY = 250 k RDELAY = 250 k RDELAY = 250 k, CDELAY = 12 nF During startup, DELAY < 2.4 V RDELAY = 250 k, CDELAY = 12 nF, VID code= 011111
2.9
3 12
3.1 400
V mV A A mV mV/A V V ms A ms
60 105 2.9 1.7
125 10.4 3 1.8 1.5 20 1
145 3.1 1.9
SOFT START Output Current, Soft-Start Mode Soft-Start Delay Time ENABLE INPUT Input Low Voltage Input High Voltage Input Current, Input Voltage Low Input Current, Input Voltage High POWER GOOD COMPARATOR Undervoltage Threshold Overvoltage Threshold Output Low Voltage Power Good Delay Time During Soft Start2 VID Code Changing VID Code Static Crowbar Trip Point Crowbar Reset Point Crowbar Delay Time VID Code Changing VID Code Static PWM OUTPUTS Output Low Voltage Output High Voltage SUPPLY DC Supply Current UVLO Threshold Voltage UVLO Hysteresis
1 2
15
25
VIL(EN) VIH(EN) IIL(EN) IIH(EN) VPWRGD(UV) VPWRGD(OV) VOL(PWRGD)
0.4 EN = 0 V EN = 1.25 V Relative to nominal DAC output Relative to nominal DAC output IPWRGD(SINK) = 4 mA RDELAY = 250 k, CDELAY = 12 nF, VID code = 011111 0.8 -1 10 -180 90 -250 150 225 +1 25 -300 200 400
V V A A mV mV mV ms
1 100 250 200 150 550 250 400 160 5 5 6.9 0.9 500
VCROWBAR tCROWBAR
Relative to nominal DAC output Relative to FBRTN Overvoltage to PWM going low
90 450 100
200 650
s ns mV mV s ns mV V mA V V
VOL(PWM) VOH(PWM)
IPWM(SINK) = -400 A IPWM(SOURCE) = 400 A
4.0
VUVLO
VCC rising
6.5 0.7
10 7.3 1.1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design or bench characterization, not tested in production.
Rev. A | Page 4 of 28
ADP3188
TEST CIRCUITS
ADP3188
1 2 3
ADP3188
+ 12V
1F 100n F
VID4 VID3 VID2 VID1 VID0 VID5 FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ
VCC 28 PWM1 27 PWM2 26
VCC 12V
28
CSCOMP
18
6-BIT CODE
4 5 6 7 8 9 1k 10
PWM3
25
39k
100nF CSSUM
17
PWM4 24 SW1 23 SW2 22 SW3 21 SW4 20 GND 19
1.0V
19
1k
16
CSREF
GND
VOS =
CSCOMP - 1V 40
Figure 3. Current-Sense Amplifier VOS
1.25V
11 12
CSCOMP 18 20k CSSUM 17 CSREF 16 ILIMIT 15 250k
04835-002
100nF
12nF
250k
13 14
ADP3188
VCC 12V
28
FB
8
Figure 2. Closed-Loop Output Voltage Accuracy
10k
9
COMP CSCOMP
18
200k 100nF
200k
CSSUM
17
V
16
CSREF
1.0V
19
GND
04835-004
VFB = FBV = 80mV - FBV = 0mV
Figure 4. Positioning Voltage
Rev. A | Page 5 of 28
04835-003
ADP3188
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VCC FBRTN VID0 to VID5, EN, DELAY, ILIMIT, CSCOMP, RT, PWM1 to PWM4, COMP SW1 - SW4 All Other Inputs and Outputs Storage Temperature Operating Ambient Temperature Range Operating Junction Temperature Thermal Impedance (JA) Lead Temperature Soldering (10 sec) Infrared (15 sec) Rating -0.3 V to +15 V -0.3 V to +0.3 V -0.3 V to +5.5 V -5 V to +25 V -0.3 V to VCC + 0.3 V -65C to +150C 0C to 85C 125C 100C/W 300C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 6 of 28
ADP3188
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VID4 1 VID3 2 VID2 3 VID1 4 VID0
5 28 27 26 25 24
VCC PWM1 PWM2 PWM3 PWM4 SW1 SW2 SW3 SW4 GND CSCOMP CSSUM CSREF ILIMIT
04835-005
VID5 6 FBRTN 7 FB 8 COMP 9 PWRGD 10 EN 11 DELAY 12 RT 13 RAMPADJ 14
ADP3188
TOP VIEW (Not to Scale)
23 22 21 20 19 18 17 16 15
Figure 5. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 to 6 Mnemonic VID4 to VID0, VID5 Description Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing a Logic 1 if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.8375 V to 1.6 V (see Table 4). Leaving all the VID pins open results in the ADP3188 going into No CPU mode, shutting off its PWM outputs and pulling the PWRGD output low. Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin and the output voltage sets the no-load offset point. Error Amplifier Output and Compensation Point. Power Good Output. Open-drain output that signals when the output voltage is outside the proper operating range. Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. Soft-Start Delay and Current-Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected between this pin and GND sets the soft-start ramp-up time and the overcurrent latch-off delay time. Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. Current-Limit Setpoint/Enable Output. An external resistor from this pin to GND sets the current-limit threshold of the converter. This pin is actively pulled low when the ADP3188 EN input is low, or when VCC is below its UVLO threshold, to signal to the driver IC that the driver high-side and low-side outputs should go low. Current-Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current-sense amplifier and the power good and crowbar functions. This pin should be connected to the common point of the output inductors. Current-Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. Current-Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determine the slope of the load line and the positioning loop response time. Ground. All internal biasing and the logic output signals of the device are referenced to this ground. Current-Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3418. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off, allowing the ADP3188 to operate as a 2-, 3-, or 4-phase controller. Supply Voltage for the Device.
Rev. A | Page 7 of 28
7 8 9 10 11 12 13 14 15
FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ ILIMIT
16
CSREF
17 18 19 20 to 23 24 to 27
CSSUM CSCOMP GND SW4 to SW1 PWM4 to PMW1 VCC
28
ADP3188
TYPICAL PERFORMANCE CHARACTERISTICS
4
5.3 TA = 25C 4-PHASE OPERATION
MASTER CLOCK FREQUENCY (MHz)
5.2
SUPPLY CURRENT (mA)
04835-006
3
5.1
5.0
2
4.9 4.8
1
4.7
0
50
100
150 200 RT VALUE (k)
250
300
0
0.5
1 1.5 2 2.5 3 OSCILLATOR FREQUENCY (MHz)
3.5
4
Figure 6. Master Clock Frequency vs. RT
Figure 7. Supply Current vs. Oscillator Frequency
Rev. A | Page 8 of 28
04835-007
0
4.6
ADP3188
THEORY OF OPERATION
The ADP3188 combines a mulitmode, fixed frequency PWM control with mulitphase logic outputs for use in 2-, 3-, and 4 - phase synchronous buck CPU core supply power converters. The internal VID DAC is designed to interface with the Intel 6-bit VRD/VRM 10-and 10.1-compatible CPUs. Multiphase operation is important for producing the high currents and low voltages demanded by today's microprocessors. Handling the high currents in a single-phase converter places high thermal demands on the components in the system, such as the inductors and MOSFETs. The multimode control of the ADP3188 ensures a stable, high performance topology for * * * * * * * * * Balancing currents and thermals between phases High speed response at the lowest possible switching frequency and output decoupling Minimizing thermal switching losses due to lower frequency operation Tight load line regulation and accuracy High current output for up to 4-phase operation Reduced output ripple due to multiphase cancellation PC board layout noise immunity Ease of use and design due to independent component selection Flexibility in operation for tailoring design to low cost or high performance The PWM outputs are logic-level devices intended for driving external gate drivers such as the ADP3418. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. Also, more than one output can be on at the same time for overlapping phases.
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3188 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 6. To determine the frequency per phase, the clock is divided by the number of phases in use. If PWM4 is grounded, divide the master clock by 3 for the frequency of the remaining phases. If PWM3 and 4 are grounded, divide by 2. If all phases are in use, divide by 4.
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3188 combines differential sensing with a high accuracy VID DAC and reference and a low offset error amplifier. This maintains a worst-case specification of 9.5 mV differential sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB and FBRTN pins. FB should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. FBRTN should be connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 100 A to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage.
START-UP SEQUENCE
During start-up, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the ADP3188 operates as a 4-phase PWM controller. Grounding the PWM4 pin programs 3-phase operation, and grounding the PWM3 and PWM4 pins programs 2-phase operation. When the ADP3188 is enabled, the controller outputs a voltage on PWM3 and PWM4, which is approximately 675 mV. An internal comparator checks each pin's voltage vs. a threshold of 300 mV. If the pin is grounded, it is below the threshold, and the phase is disabled. The output resistance of the PWM pin is approximately 5 k during this detection time. Any external pull-down resistance connected to the PWM pin should not be less than 25 k to ensure proper operation. PWM1 and PWM2 are disabled during the phase detection interval, which occurs during the first two clock cycles of the internal oscillator. After this time, if the PWM output is not grounded, the 5 k resistance is removed, and it switches between 0 V and 5 V. If the PWM output is grounded, it remains off.
OUTPUT CURRENT SENSING
The ADP3188 provides a dedicated current-sense amplifier (CSA) to monitor the total output current for proper voltage positioning vs. load current and for current-limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element, such as the low-side MOSFET. This amplifier can be configured several ways depending on the objectives of the system: * * * Output inductor DCR sensing without a thermistor for lowest cost Output inductor DCR sensing with a thermistor for improved accuracy with tracking of inductor temperature Sense resistors for highest accuracy measurements
Rev. A | Page 9 of 28
ADP3188
The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the amplifier are summed together through resistors from the sensing element (such as the switch node side of the output inductors) to the inverting input, CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor to set the load line required by the microprocessor. The current information is then given as the difference of CSREF - CSCOMP. This difference signal is used internally to offset the VID DAC for voltage positioning and as a differential input for the current-limit comparator. To provide the best accuracy for sensing current, the CSA is designed to have a low offset input voltage. Also, the sensing gain is determined by external resistors, so that it can be made extremely accurate. External resistors can be placed in series with individual phases to create, if desired, an intentional current imbalance such as when one phase may have better cooling and can support higher currents. Resistors RSW1 through RSW4 (see the typical application circuit in Figure 10) can be used for adjusting thermal balance. It is best to have the ability to add these resistors during the initial design, so make sure that placeholders are provided in the layout. To increase the current in any given phase, make RSW for this phase larger (make RSW = 0 for the hottest phase, and do not change during balancing). Increasing RSW to only 500 makes a substantial increase in phase current. Increase each RSW value by small amounts to achieve balance, starting with the coolest phase first.
VOLTAGE CONTROL MODE
A high gain bandwidth voltage mode error amplifier is used for the voltage-mode control loop. The control input voltage to the positive input is set via the VID logic according to the voltages listed in Table 4. This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with a resistor (RB) and is used for sensing and controlling the output voltage at this point. A current source from the FB pin flowing through RB is used for setting the no-load offset voltage from the VID voltage. The no-load voltage is negative with respect to the VID DAC. The main loop compensation is incorporated into the feedback network between FB and COMP.
ACTIVE IMPEDANCE CONTROL MODE
For controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the CSCOMP pin can be scaled to equal the droop impedance of the regulator multiplied by the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be. This differs from previous implementations and allows enhanced feed-forward response.
CURRENT-CONTROL MODE AND THERMAL BALANCE
The ADP3188 has individual inputs for each phase, which are used for monitoring the current in each phase. This information is combined with an internal ramp to create a current balancing feedback system, which has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current-balance information is independent of the average output current information used for positioning described previously. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feed-forward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. Detailed information about programming the ramp is given in the Application Information section.
SOFT START
The power-on ramp-up time of the output voltage is set with a capacitor and resistor in parallel from the DELAY pin to ground. The RC time constant also determines the current-limit latchoff time as explained in the following section. In UVLO, or when EN is a logic low, the DELAY pin is held at ground. After the UVLO threshold is reached and EN is a logic high, the DELAY capacitor is charged with an internal 20 A current source. The output voltage follows the ramping voltage on the DELAY pin, limiting the inrush current. The soft-start time depends on the value of the VID DAC and CDLY, with a secondary effect from RDLY. Refer to the Application Information section for detailed information on setting CDLY. If either EN is taken low, or VCC drops below UVLO, the DELAY capacitor is reset to ground to be ready for another soft-start cycle. Figure 8 shows a typical soft-start sequence for the ADP3188.
Rev. A | Page 10 of 28
ADP3188
DELAY to VCC. This prevents the DELAY capacitor from discharging, so the 1.8 V threshold is never reached. The resistor has an impact on the soft-start time because the current through it adds to the internal 20 A current source. During start-up when the output voltage is below 200 mV, a secondary current limit is active. This is necessary because the voltage swing of CSCOMP cannot go below ground. This secondary current limit controls the internal COMP voltage to the PWM comparators to 2 V. This limits the voltage drop across the low-side MOSFETs through the current balance circuitry. An inherent per phase current limit protects individual phases, if one or more phases stops functioning because of a faulty component. This limit is based on the maximum normal mode COMP voltage.
04835-008
Figure 8. Typical Start-Up Waveforms Channel 1: PWRGD, Channel 2: CSREF, Channel 3: DELAY, Channel 4: COMP
CURRENT-LIMIT, SHORT-CIRCUIT, AND LATCH-OFF PROTECTION
The ADP3188 compares a programmable current-limit setpoint to the voltage from the output of the current-sense amplifier. The level of current limit is set with the resistor from the ILIMIT pin to ground. During normal operation, the voltage on ILIMIT is 3 V. The current through the external resistor is internally scaled to give a current-limit threshold of 10.4 mV/A. If the difference in voltage between CSREF and CSCOMP rises above the current-limit threshold, the internal current-limit amplifier controls the internal COMP voltage to maintain the average output current at the limit. After the limit is reached, the 3 V pull-up on the DELAY pin is disconnected, and the external delay capacitor is discharged through the external resistor. A comparator monitors the DELAY voltage and shuts off the controller when the voltage drops below 1.8 V. The current-limit latch-off delay time is therefore set by the RC time constant discharging from 3 V to 1.8 V. The Application Information section discusses the selection of CDLY and RDLY. Because the controller continues to cycle the phases during the latch-off delay time, if the short is removed before the 1.8 V threshold is reached, the controller returns to normal operation. The recovery characteristic depends on the state of PWRGD. If the output voltage is within the PWRGD window, the controller resumes normal operation. However, if a short circuit has caused the output voltage to drop below the PWRGD threshold, a soft-start cycle is initiated. The latch-off function can be reset by either removing and reapplying VCC to the ADP3188, or by pulling the EN pin low for a short time. To disable the short-circuit latch-off function, the external resistor to ground should be left open, and a high value (>1 M) resistor should be connected from
Figure 9. Overcurrent Latch-Off Waveforms Channel 1: CSREF, Channel 2: DELAY, Channel 3: COMP, Channel 4: Phase 1 Switch Node
DYNAMIC VID
The ADP3188 has the ability to dynamically change the VID input while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as VID onthe-fly (OTF). A VID OTF can occur under either light or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. When a VID input changes state, the ADP3188 detects the change and ignores the DAC inputs for a minimum of 400 ns. This time prevents a false code due to logic skew while the six VID inputs are changing. Additionally, the first VID change initiates the PWRGD and crowbar blanking functions for a minimum of 100 s to prevent a false PWRGD or crowbar event. Each VID change resets the internal timer.
Rev. A | Page 11 of 28
04835-0-009
ADP3188
Table 4. VID Codes for the ADP3188
VID4 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 VID2 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 VID1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 VID0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 VID5 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output No CPU No CPU 0.8375 V 0.8500 V 0.8625 V 0.8750 V 0.8875 V 0.9000 V 0.9125 V 0.9250 V 0.9375 V 0.9500 V 0.9625 V 0.9750 V 0.9875 V 1.0000 V 1.0125 V 1.0250 V 1.0375 V 1.0500 V 1.0625 V 1.0750 V 1.0875 V 1.1000 V 1.1125 V 1.1250 V 1.1375 V 1.1500 V 1.1625 V 1.1750 V 1.1875 V 1.2000 V VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output 1.2125 V 1.2250 V 1.2375 V 1.2500 V 1.2625 V 1.2750 V 1.2875 V 1.3000 V 1.3125 V 1.3250 V 1.3375 V 1.3500 V 1.3625 V 1.3750 V 1.3875 V 1.4000 V 1.4125 V 1.4250 V 1.4375 V 1.4500 V 1.4625 V 1.4750 V 1.4875 V 1.5000 V 1.5125 V 1.5250 V 1.5375 V 1.5500 V 1.5625 V 1.5750 V 1.5875 V 1.6000 V
POWER GOOD MONITORING
The power good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specified in Table 4. These limits are based on the VID voltage setting. PWRGD goes low if the output voltage is outside of this specified range, if all of the VID DAC inputs are high, or whenever the EN pin is pulled low. PWRGD is blanked during a VID OTF event for a period of 250 s to prevent false signals during the time the output is changing.
The PWRGD circuitry also incorporates an initial turn-on delay time based on the DELAY ramp. The PWRGD pin is held low until the DELAY pin reaches 2.6 V. The time between when the PWRGD undervoltage threshold is reached and when the DELAY pin reaches 2.6 V provides the turn-on delay time. This time is incorporated into the soft-start ramp. To ensure a 1 ms delay time on PWRGD, the soft-start ramp must also be >1 ms. Refer to the Application Information section for detailed information on setting CDLY.
Rev. A | Page 12 of 28
ADP3188
OUTPUT CROWBAR
As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the low-side MOSFETs) when the output voltage exceeds the upper crowbar threshold. This crowbar action stops once the output voltage falls below the release threshold of approximately 550 mV. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short in the high-side MOSFET, this action current-limits the input supply or blows its fuse, protecting the microprocessor from being destroyed.
OUTPUT ENABLE AND UVLO
For the ADP3188 to begin switching, the input supply (VCC) to the controller must be higher than the UVLO threshold, and the EN pin must be higher than its logic threshold. If UVLO is less than the threshold or the EN pin is a logic low, the ADP3188 is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and holds the ILIMIT pin at ground. In the application circuit, the ILIMIT pin should be connected to the OD pins of the ADP3418 drivers. The ILIMIT being grounded disables the drivers such that both DRVH and DRVL are grounded. This feature is important in preventing the discharge of the output capacitors when the controller is shut off. If the driver outputs were not disabled, a negative voltage could be generated during output due to the high current discharge of the output capacitors through the inductors.
Rev. A | Page 13 of 28
ADP3188
L1 370nH 18A R3 2.2 + D2 1N4148 C7 4.7F +
VIN 12V
2700F/16V/3.3 A x 2 SANYO MV-WX SERIES
C8 15nF
VIN RTN C2 C1
1 2 3
U2 ADP3418
C6 10nF
8 7 6
BST DRVH SW PGND + DRVL
5
Q2 NTD40N03 L2 320nH/1.4m
IN OD VCC Q3 NTD110N02 Q4 NTD110N02 C22 Q1 NTD40N03
560F/4V x 8 SANYO SEPC SERIES 5m EACH +
VCC(CORE) 0.8375V - 1.6V 95A TDC, 119A PK VCC(CORE) RTN
4
C5 4.7F R4 2.2 C12 15nF
C31
D3 1N4148 D1 1N4148
1 2 3 4
U3 ADP3418
C10 10nF
8 7 6 5
C11 4.7F
10F x 18 MLCC IN SOCKET Q6 NTD40N03 L3 320nH/1.4m
BST IN OD VCC DRVL PGND Q5 NTD40N03 SW
DRVH
R1 10 C9 4.7F + C4 1F R2 357k 1% R5 2.2 C16 15nF
*FOR A DESCRIPTION OF OPTIONAL RSW RESISTORS, SEE THE THEORY OF OPERATION SECTION.
Q7 Q8 NTD110N02 NTD110N02
C3 100F
U1 ADP3188
VCC
28 27
1 2
VID4 VID3 PWM1 PWM2
26 25 1 2 3
D4 1N4148 BST IN OD
4
U4 ADP3418
C14 10nF DRVH SW PGND
8 7 6
C15 4.7F Q10 NTD40N03 Q9 NTD40N03
FROM CPU
Figure 10. Typical VR 10.1 Application Circuit
3 4
Rev. A | Page 14 of 28
VID2 VID1 PWM3 PWM4
24 5
L4 320nH/1.4m
VID0 RSW1 * VID5 SW1
23
6
VCC C13 4.7F
DRVL
5
RSW2 *
7
FBRTN SW2
22
C22 1000pF
8
CB 470pF RSW3 * FB SW3
21
R6 2.2 RSW4 *
CFB 22pF
9
C20 15nF
Q11 NTD110N02
Q12 NTD110N02
POWER GOOD
10
RB 1.21k PWRGD GND
19
CA RA 470pF 12.1k CCS2 1.5nF RCS2 84.5k CCS1 560pF R7 10 RPH3 158k 1% RPH1 158k 1% RCS1 35.7k R PH4 158k 1% RPH2 158k 1%
11 18
COMP SW4
20
ENABLE EN CSCOMP CSSUM
17 12 13 16
D5 1N4148
U5 ADP3418
1 2 3 4
C18 10nF BST IN OD VCC C17 4.7F DRVH SW PGND DRVL
8 7 6 5
C19 4.7F
DELAY RT CSREF ILIMIT
15
Q14 NTD40N03 Q13 NTD40N03
CDLY 39nF RT 137k 1%
14
RDLY 470k RAMPADJ C23 0.01F
L5 320nH/1.4m RTH1 100k , 5% NTC Q15 NTD110N02 Q16 NTD110N02
RLIM 150k 1%
C21 100pF
04835-010
ADP3188
APPLICATION INFORMATION
The design parameters for a typical Intel VRD 10.1-compliant CPU application are as follows: * * * * * * Input voltage (VIN) = 12 V VID setting voltage (VVID) = 1.300 V Duty cycle (D) = 0.108 Nominal output voltage at no load (VONL) = 1.281 V Nominal output voltage at 101 A load (VOFL) = 1.180 V Static output voltage drop based on a 1.0 m load line (RO) from no load to full load (VD) = VONL - VOFL = 1.281 V - 1.180 V = 101 mV Maximum output current (IO) = 119 A Maximum output current step (IO) = 95 A Number of phases (n) = 4 Switching frequency per phase (fSW) = 330 kHz However, as long as RDLY is kept greater than 200 k, this effect is minor. The value for CDLY can be approximated using
VVID C DLY = 20 A - 2 x RDLY t SS x V VID
(2)
where tSS is the desired soft-start time. Assuming an RDLY of 390 k and a desired soft-start time of 3 ms, CDLY is 36 nF. The closest standard value for CDLY is 39 nF. Once CDLY is chosen, RDLY can be calculated for the current-limit latch-off time using
RDLY = 1.96 x t DELAY C DLY
* * * *
(3)
SETTING THE CLOCK FREQUENCY
The ADP3188 uses a fixed-frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and/or the input and output capacitors. With n = 4 for four phases, a clock frequency of 1.32 MHz sets the switching frequency (fSW) of each phase to 330 kHz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. Equation 1 shows that to achieve an 1.32 MHz oscillator frequency, the correct value for RT is 137 k. Alternatively, the value for RT can be calculated using
RT = 1 - 27 k n x f SW x 4.7 pF
If the result for RDLY is less than 200 k, a smaller soft-start time should be considered by recalculating the equation for CDLY, or a longer latch-off time should be used. RDLY should never be less than 200 k. In this example, a delay time of 9 ms results in RDLY = 452 k. The closest standard 5% value is 470 k.
INDUCTOR SELECTION
The choice of inductance for the inductor determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs, but allows using smaller inductors and, for a specified peak-to-peak transient deviation, less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger inductors and more output capacitance for the same peak-topeak transient deviation. In any multiphase converter, a practical value for the peak-to-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 4 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current in the inductor.
IR = VVID x (1 - D ) f SW x L
(1)
where 4.7 pF and 27 k are internal IC component values. For good initial accuracy and frequency stability, a 1% resistor is recommended.
(4)
SOFT START AND CURRENT-LIMIT LATCH-OFF DELAY TIMES
Because the soft start and current-limit latch-off delay functions share the DELAY pin, these two parameters must be considered together. The first step is to set CDLY for the soft-start ramp. This ramp is generated with a 20 A internal current source. The value of RDLY has a second-order impact on the soft-start time because it sinks part of the current source to ground.
Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage.
L VVID x RO x (1 - (n x D )) f SW x VRIPPLE
(5)
Solving Equation 5 for a 10 mV p-p output ripple voltage yields
L 1.3 V x 1.0 m x (1 - 0.432) = 224 nH 330 kHz x 10 mV
If the resulting ripple voltage is less than it was designed for, make the inductor smaller until the ripple value is met. This allows optimal transient response and minimum output decoupling.
Rev. A | Page 15 of 28
ADP3188
The smallest possible inductor should be used to minimize the number of output capacitors. For this example, choosing a 320 nH inductor is a good starting point and gives a calculated ripple current of 11 A. The inductor should not saturate at the peak current of 35.5 A and should be able to handle the sum of the power dissipation caused by the average current of 30 A in the winding and core loss. Another important factor in the inductor design is the DCR, which is used for measuring the phase currents. A large DCR can cause excessive power losses, while too small a value can lead to increased measurement error. A good rule is to have the DCR be about 1 to 11/2 times the droop resistance (RO). For this design, an inductor with a DCR of 1.4 m is used. * Coiltronics (561) 752-5000 www.coiltronics.com Sumida Electric Company (847) 545-6700 www.sumida.com Vishay Intertechnology (402) 563-6866 www.vishay.com
*
*
OUTPUT DROOP RESISTANCE
The design requires the regulator output voltage measured at the CPU pins to drop when the output current increases. The specified voltage drop corresponds to a dc output resistance (RO). The output current is measured by summing the voltage across each inductor and passing the signal through a low-pass filter. This summer filter is the CS amplifier configured with resistors RPH(X) (summers), and RCS and CCS (filter). The output resistance of the regulator is set by the following equations, where RL is the DCR of the output inductors:
RO = RCS x RL RPH ( x )
L RL x RCS
DESIGNING AN INDUCTOR
Once the inductance and DCR are known, the next step is to either design an inductor, or to find a standard inductor that comes as close as possible to meeting the overall design goals. It is also important to have the inductance and DCR tolerance specified to control the accuracy of the system. 15% inductance and 8% DCR (at room temperature) are reasonable tolerances that most manufacturers can meet. The first decision in designing the inductor is to choose the core material. Several possibilities for providing low core loss at high frequencies include the powder cores (for example, KoolM(R) from Magnetics, Inc. or from Micrometals) and the gapped soft ferrite cores (for example, 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low, and the ripple current is high. The best choice for a core geometry is a closed-loop type such as a potentiometer core, PQ, U, or E core or toroid. A good compromise between price and performance is a core with a toroidal shape. Many useful magnetics design references are available for quickly designing a power inductor, such as * * Magnetic Designer Software Intusoft (www.intusoft.com) Designing Magnetic Components for High-Frequency DCDC Converters, by William T. McLyman, K G Magnetics, Inc., ISBN 1883107008
(6)
CCS =
(7)
The user has the flexibility of choosing either RCS or RPH(X). It is best to select RCS equal to 100 k, and then solve for RPH(X) by rearranging Equation 6.
RPH ( x ) = RL x RCS RO 1.4 m x 100 k = 140 k 1.0 m
RPH ( x ) =
Next, use Equation 6 to solve for CCS.
CCS = 320 nH = 2.28 nF 1.4 m x 100 k
Selecting a Standard Inductor
The following power inductor manufacturers can provide design consultation and deliver power inductors optimized for high power applications upon request: * Coilcraft (847) 639-6400 www.coilcraft.com
It is best to have a dual location for CCS in the layout, so that standard values can be used in parallel to get as close to the value desired. For accuracy, CCS should be a 5% or 10% NPO capacitor. This example uses a 5% combination for CCS of 1.5 nF and 560 pF in parallel. Recalculating RCS and RPH(X) using this capacitor combination yields 110 k and 154 k. The closest standard 1% value for RPH(X) is 158 k.
Rev. A | Page 16 of 28
ADP3188
INDUCTOR DCR TEMPERATURE CORRECTION
With the inductor's DCR being used as the sense element and copper wire being the source of the DCR, compensation is needed for temperature changes of the inductor's winding. Fortunately, copper has a well-known temperature coefficient (TC) of 0.39%/C. If RCS is designed to have an opposite and equal percentage change in resistance to that of the wire, it cancels the temperature variation of the inductor's DCR. Due to the nonlinear nature of NTC thermistors, resistors RCS1 and RCS2 are needed. See Figure 11 to linearize the NTC and produce the desired temperature tracking.
PLACE AS CLOSE AS POSSIBLE TO NEAREST INDUCTOR OR LOW-SIDE MOSFET
R TH
4.
Compute the relative values for RCS1, RCS2, and RTH using
rCS2 =
( A - B ) x r1 x r2 - A x (1 - B ) x r2 + B x (1 - A) x r1 A x (1 - B ) x r1 - B x (1 - A) x r2 - ( A - B )
rCS1 =
(1 - A) 1 A - 1 - rCS2 r1 - rCS2
1 1 1 - 1 - rCS2 rCS1
rTH =
(8)
5.
TO SWITCH NODES TO V OUT SENSE
Calculate RTH = rTH x RCS, then select the closest value of thermistor available. Also compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one:
k= RTH ( ACTUAL ) RTH (CALCULATED )
R PH1
R PH2
R PH3
(9)
ADP3188
CSCOMP
18 C CS1 C CS2 R CS1 R CS2
6.
KEEP THIS PATH AS SHORT AS POSSIBLE AND WELL AWAY FROM SWITCH NODE LINES
Calculate values for RCS1 and RCS2 using Equation 10:
RCS1 = RCS x k x rCS1 RCS2 = RCS x ((1 - k ) + (k x rCS2 ))
CSSUM
17
(10)
CSREF
04835-011
16
Figure 11. Temperature Compensation Circuit Values
The following procedure and expressions yield values to use for RCS1, RCS2, and RTH (the thermistor value at 25C) for a given RCS value. 1. Select an NTC based on type and value. Because there isn't a value yet, start with a thermistor with a value close to RCS. The NTC should also have an initial tolerance of better than 5%. Based on the type of NTC, find its relative resistance value at two temperatures. The temperatures that work well are 50C and 90C. These resistance values are called A (RTH(50C)/RTH(25C)) and B (RTH(90C)/RTH(25C)). Note: the NTC's relative value is always 1 at 25C. Find the relative values of RCS required for each of these temperatures. This is based on the percentage change needed, which in this example is initially 0.39%/C. The relative values are called r1 (1/(1 + TC x (T1 - 25))) and r2 (1/(1 + TC x (T2 - 25))), where TC = 0.0039 for copper. T1 = 50C and T2 = 90C are chosen. From this, calculate that r1 = 0.9112 and r2 = 0.7978.
For this example, RCS has been calculated to be 110 k. Start with a thermistor value of 100 k. Next, look through the available 0603-size thermistors, and find a Vishay NTHS0603N01N1003JR NTC thermistor with A = 0.3602 and B = 0.09174. From these, compute rCS1 = 0.3795, rCS2 = 0.7195, and rTH = 1.075. Solve for RTH, which yields118.28 k. Then, choose 100 k, which makes k = 0.8455. Finally, RCS1 and RCS2 are 35.3 k and 83.9 k. Choose the closest 1% resistor values, which yields a choice of 35.7 k or 84.5 k.
OUTPUT OFFSET
The Intel specification requires that at no load the nominal output voltage of the regulator be offset to a value lower than the nominal voltage corresponding to the VID code. The offset is set by a constant current source flowing out of the FB pin (IFB) and flowing through RB. The value of RB can be found using Equation 11:
RB = VVID - VONL I FB
2.
3.
RB =
1.3 V - 1.281 V = 1.22 k 15.5 A
(11)
The closest standard 1% resistor value is 1.21 k.
Rev. A | Page 17 of 28
ADP3188
COUT SELECTION
The required output decoupling for the regulator is typically recommended by Intel for various processors and platforms. Also, to determine what is required, use some simple design guidelines. These guidelines are based on having both bulk and ceramic capacitors in the system. The first thing is to select the total amount of ceramic capacitance. This is based on the number and type of capacitor to be used. The best location for ceramic capacitors is inside the socket, with 12 to 18 of size 1206 being the physical limit. Others can be placed along the outer edge of the socket as well. Combined ceramic values of 200 F to 300 F are recommended, usually made up of multiple 10 F or 22 F capacitors. Select the number of ceramic capacitors and find the total ceramic capacitance (CZ). Next, there is an upper limit imposed on the total amount of bulk capacitance (CX) when considering the VID on-the-fly voltage stepping of the output (voltage step VV in time tV with error of VERR). A lower limit is based on meeting the capacitance for load release for a given maximum load step IO and a maximum allowable overshoot. The total amount of load release voltage is given as VO = IO x RO + Vrl, where Vrl is the maximum allowable overshoot voltage.
L x IO C x (MIN ) - Cz n x R + Vrl x V VID O I O
C x ( MAX )
This example uses 18, 10 F 1206 MLC capacitors (CZ = 180 F). The VID on-the-fly step change is 450 mV in 230 s with a setting error of 2.5 mV. The maximum allowable load release overshoot for this example is 50 mV, so solving for the bulk capacitance yields
320 nH x 95 A C x (MIN ) - 180 F = 3.65 mF 50 mV 4 x 1.0 m + x 1. 3 V 95 A
320 nH x 450 mV
C x (MAX )
4 x 4.6 2 x (1.0 m )2 x 1.3 V
x
2 230 s x 1.3 V x 4 x 4.6 x 1.0 m - 1 - 180 F 1+ 450 mV x 320 nH = 48.5 mF
where K = 4.6. Using eight 560 F Al-Poly capacitors with a typical ESR of 5 m each yields CX = 4.48 mF with an RX = 0.63 m. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit the high frequency ringing during a load change. This is tested using
(12)
Lx C z x R O xQ 2 Lx 180 F x (1 m ) x 2 = 360 pH
2
2
(14)
2 VVID nKRO VV tv - 1 - C z x x 1+ x 22 VVID VV L nK RO L
V where K = 1n ERR V V
(13)
where Q is limited to the square root of 2 to ensure a critically damped system. In this example, LX is approximately 350 pH for the eight A1-Polys capacitors, which satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased if there is excessive ringing. Note for this multimode control technique, all ceramic designs can be used as long as the conditions of Equations 11, 12, and 13 are satisfied.
To meet the conditions of these expressions and transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance (RO). If the CX(MIN) is larger than CX(MAX), the system cannot meet the VID on-the-fly specification and may require the use of a smaller inductor or more phases (and may need the switching frequency to increase to keep the output ripple the same).
POWER MOSFETS
For this example, the N-channel power MOSFETs have been selected for one high-side switch and two low-side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3418) dictates whether standard threshold or logic-level threshold MOSFETs must be used. With VGATE ~10 V, logic-level threshold MOSFETs (VGS(TH)< 2.5 V) are recommended.
Rev. A | Page 18 of 28
ADP3188
The maximum output current (IO) determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. With the ADP3188, currents are balanced between phases, thus the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, the following expression shows the total power being dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and average total output current (IO):
I PSF = (1 - D ) x O nSF nI + 1 x R 12 n SF
2
Note that adding more main MOSFETs (nMF) does not really help the switching loss per MOSFET because the additional gate capacitance slows switching. The best way to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by the following, where RDS(MF) is the on resistance of the MOSFET:
I PC ( MF ) = D x O n MF 1 n x IR + x 12 n MF
2

2
x RDS (SF )
(15)

2
x R DS ( MF )
(17)
Knowing the maximum output current being designed for and the maximum allowed power dissipation, it is possible to find the required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to an ambient temperature of 50C, a safe limit for PSF is 1 W to 1.5 W at 120C junction temperature. Thus, for this example (119 A maximum), RDS(SF) (per MOSFET) < 7.5 m. This RDS(SF) is also at a junction temperature of about 120C, so be certain to account for this temperature when making this selection. This example uses two lower-side MOSFETs at 4.8 m each at 120C. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to input needs to be small (less than 10% is recommended) to prevent accidental turn-on of the synchronous MOSFETs when the switch node goes high. Also, the time to switch the synchronous MOSFETs off should not exceed the nonoverlap dead time of the MOSFET driver (40 ns typical for the ADP3418). The output impedance of the driver is approximately 2 , and the typical MOSFET input gate resistances are about 1 to 2 , so a total gate capacitance of less than 6000 pF should be adhered to. Because there are two MOSFETs in parallel, the input capacitance for each synchronous MOSFET should be limited to 3000 pF. The high-side (main) MOSFET has to be able to handle two main power dissipation components: conduction and switching losses. The switching loss is related to the amount of time it takes for the main MOSFET to turn on and off, and to the current and voltage that are being switched. Basing the switching speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance, the following expression provides an approximate value for the switching loss per main MOSFET, where nMF is the total number of main MOSFETs:
PS ( MF ) = 2 x f SW x VCC x I O nMF x RG x nMF x C ISS n
Typically, for main MOSFETs, the highest speed (low CISS) device is preferred, but these usually have higher on resistance. Select a device that meets the total power dissipation (about 1.5 W for a single D-PAK) when combining the switching and conduction losses. For this example, an NTD40N03L was selected as the main MOSFET (eight total; nMF = 8), with a CISS = 584 pF (max) and RDS(MF) = 19 m (max at TJ = 120C), and an NTD110N02L was selected as the synchronous MOSFET (eight total; nSF = 8), with CISS = 2710 pF (max) and RDS(SF) = 4.8 m (max at TJ = 120C). The synchronous MOSFET CISS is less than 3000 pF, satisfying that requirement. Solving for the power dissipation per MOSFET at IO = 119 A and IR = 11 A yields 958 mW for each synchronous MOSFET and 872 mW for each main MOSFET. These numbers comply with the guideline to limit the power dissipation to 1 W per MOSFET. One last thing to consider is the power dissipation in the driver for each phase. This is best described in terms of the QG for the MOSFETs and is given by the following equation, where QGMF is the total gate charge for each main MOSFET, and QGSF is the total gate charge for each synchronous MOSFET:
f PDRV = SW x (nMF x QGMF + nSF x QGSF ) + I CC x VCC 2 xn
(18)
Also shown is the standby dissipation factor (ICC x VCC) for the driver. For the ADP3418, the maximum dissipation should be less than 400 mW. In this example, with ICC = 7 mA, QGMF = 5.8 nC, and QGSF = 48 nC, 297 mW is found in each driver, which is below the 400 mW dissipation limit. See the ADP3418 data sheet for more details.
(16)
where RG is the total gate resistance (2 for the ADP3418 and about 1 for typical high speed switching MOSFETs, making RG = 3 ), and CISS is the input capacitance of the main MOSFET.
Rev. A | Page 19 of 28
ADP3188
RAMP RESISTOR SELECTION
The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. The following expression is used for determining the optimum value:
AR x L RR = 3 x AD x RDS x C R RR = 0.2 x 320 nH = 356 k 3 x 5 x 2.4 m x 5 pF
For values of RLIM greater than 500 k, the current limit may be lower than expected, so some adjustment of RLIM may be needed. Here, ILIM is the average current limit for the output of the supply. In this example, choosing a peak current limit of 200 A for ILIM, results in RLIM = 156 k, for which 150 k is chosen as the nearest 1% value. The limit of the per-phase current limit described earlier is determined by
(19)
I PHLIM
VCOMP (MAX ) - V R - V BIAS AD x R DS (MAX )
+
IR 2
(23)
where AR is the internal ramp amplifier gain, AD is the current balancing amplifier gain, RDS is the total low-side MOSFET on resistance, and CR is the internal ramp capacitor value. The closest standard 1% resistor value is 357 k. The internal ramp voltage magnitude can be calculated by using
VR = AR x (1 - D ) x VVID R R x C R x f SW
0.2 x (1 - 0.108 ) x 1.3 V = 390 m V 357 k x 5 pF x 330 kHz
For the ADP3188, the maximum COMP voltage (VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.2 V, and the current-balancing amplifier gain (AD) is 5. Using VR of 0.49 V and RDS(MAX) of 3 m (low-side on resistance at 150C), calculate a per-phase peak current limit of 100 A. Although this number may seem high, this current level can be reached only with an absolute short at the output, and the current-limit latch-off function shuts down the regulator before overheating can occur. This limit can be adjusted by changing the ramp voltage (VR), but make sure not to set the per-phase limit lower than the average per-phase current (ILIM/n). The per-phase initial duty cycle limit is determined by
D MAX = D x VCOMP ( MAX ) - VBIAS VRT
(20)
VR =
The size of the internal ramp can be made larger or smaller. If it is made larger, stability and transient response improve, but thermal balance degrades. Likewise, if the ramp is made smaller, thermal balance improves at the sacrifice of transient response and stability. The factor of three in the denominator of Equation 19 sets a ramp size that gives an optimal balance for good stability, transient response, and thermal balance.
(24)
In this example, the maximum duty cycle is 0.46.
FEEDBACK LOOP COMPENSATION DESIGN
Optimized compensation of the ADP3188 allows the best possible response of the regulator's output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (RO). With the resistive output impedance, the output voltage droops in proportion to the load current at any load current-slew rate. This ensures the optimal positioning and allows the minimization of the output decoupling. With the multimode feedback structure of the ADP3188, the feedback compensation must be set to make the converter's output impedance, working in parallel with the output decoupling, to meet this goal. Several poles and zeros created by the output inductor and decoupling capacitors (output filter) need to be compensated for.
COMP PIN RAMP
A ramp signal on the COMP pin is due to the droop voltage and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input:
VRT = VR 2 x (1 - n x D ) 1 - nx f xC x R X SW O
(21)
In this example, the overall ramp signal is 0.49 V.
CURRENT-LIMIT SETPOINT
To select the current-limit setpoint, first find the resistor value for RLIM. The current-limit threshold for the ADP3188 is set with a 3 V source (VLIM) across RLIM with a gain of 10.4 mV/A (ALIM). RLIM can be found using
RLIM = ALIM x VLIM I LIM x RO
(22)
Rev. A | Page 20 of 28
ADP3188
A type-three compensator on the voltage feedback is adequate for proper compensation of the output filter. Equations 25 to 29 yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (see the section). The first step is to compute the time constants for all of the poles and zeros in the system
RE = n x RO + AD x RDS + RL x VRT 2 x L x (1 - n x D ) x VRT + VVID n x C X x RO x VVID 1.4 m x 0.49 V 2 x 320 nH x (1 - 0.432 ) x 0.49 V + = 24.2 m 1.3 V 4 x 4.45 mF x 1 m x 1.3 V
RE = 4 x 1 m + 5 x 2.4 m + T A = C X x (RO - R ) +
(25)
L X RO - R 350 pH 1 m - 0.65 m = 4.45 mF x (1 m - 0.5 m ) + x = 2.50 s x 1 m 10.63 m RO RX
(26) (27)
TB = (RX + R - RO ) x C X = (0.63 m + 0.5 m - 1 m) x 4.45 mF = 580 ns
A x R DS V RT x L - D 2 x f SW TC = VVID x R E
TD =
5 x 2.4 m 0.49 V x 320 nH - 2 x 330 kHz = = 4.7 s 1.3 V x 24.2 m
(28)
CX
2 C X x C Z x RO 4.45 mF x 180 F x (1 m )2 = = 333 ns x (RO - R ') + C Z x RO 4.45 mF x (1 m - 0.5 m ) + 180 F x 1 m
(29)
where, for the ADP3188, R' is the PCB resistance from the bulk capacitors to the ceramics and where RDS is the total lowside MOSFET on resistance per phase. In this example, AD is 5, VRT equals 0.49 V, R' is approximately 0.5 m (assuming a 4-layer, 1 ounce motherboard), and LX is 350 pH for the eight Al-Poly capacitors. The compensation values can then be solved using the following:
CA = n x RO x T A RE x R B
CB =
TB 580 ns = = 479 nF RB 1.21 k TD 333 ns = = 24.3 p F R A 13.7 k
(32)
C FB =
(33)
These are the starting values, prior to tuning the design, to account for layout and other parasitic effects (see the section). The final values selected after tuning are
C A = 470 pF R A = 12.1 k C B = 470 pF C FB = 22 pF
(30)
4 x 1 m x 2.50 s CA = = 342 pF 24.2 m x 1.21 k
RA =
TC 4.7 s = = 13.7 k C A 342 pF
(31)
Rev. A | Page 21 of 28
ADP3188
Figure 12 and Figure 13 show the typical transient response using these compensation values.
CIN SELECTION AND INPUT CURRENT DI/DT REDUCTION
In continuous inductor current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to n x VOUT/VIN and an amplitude of one-nth the maximum output current. To prevent large voltage transients, a low ESR input capacitor, sized for the maximum rms current, must be used. The maximum rms capacitor current is given by
I CRMS = D x I O x 1 -1 NxD
(34)
04835-0-012
I CRMS = 0.108 x 119 A x
1 - 1 = 14.7 A 4 x 0.108
Figure 12. Typical Transient Response for Design Example Load Step
Note that the capacitor manufacturer's ripple current ratings are often based on only 2,000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be placed in parallel to meet size or height requirements in the design. In this example, the input capacitor bank is formed by two 2,700 F, 16 V aluminum electrolytic capacitors and eight 4.7 F ceramic capacitors. To reduce the input current di/dt to a level below the recommended maximum of 0.1 A/s, an additional small inductor (L > 370 nH at 18 A) should be inserted between the converter and the supply bus. That inductor also acts as a filter between the converter and the primary power source.
04835-0-013
100
Figure 13. Typical Transient Response for Design Example Load Release
EFFICIENCY (%)
80
60
40
20 VOUT = 1.3 V TA = 25C 0 20 40 60 80 OUTPUT CURRENT (A) 100 120
04835-014
0
Figure 14. Efficiency of the Circuit of Figure 10 vs. Output Current
Rev. A | Page 22 of 28
ADP3188
TUNING THE ADP3188
1. 2. Build a circuit based on the compensation values computed from the design spreadsheet. Hook up the dc load to circuit, turn it on, and verify its operation. Also, check for jitter at no load and full load. Measure the output voltage at no load (VNL). Verify that it is within tolerance. Measure the output voltage at full load cold (VFLCOLD). Let the board sit for ~10 minutes at full load, and then measure the output (VFLHOT). If there is a change of more than a few millivolts, adjust RCS1 and RCS2 using Equations 35 and 36.
RCS2 ( NEW ) = RCS2(OLD ) x V NL - VFLCOLD V NL - VFLHOT
6.
Measure the output voltage from no-load to full-load using 5 A steps. Compute the loadline slope for each change, and then average to get the overall loadline slope (ROMEAS). If ROMEAS is off from RO by more than 0.05 m, use the following to adjust the RPH values:
RPH ( NEW ) = RPH (OLD ) x ROMEAS RO
7.
DC Loadline Setting
3. 4.
(36)
8. 9.
Repeat Steps 6 and 7 to check the loadline, and repeat adjustments if necessary. Once dc loadline adjustment is complete, do not change RPH, RCS1, RCS2, or RTH for remainder of procedure.
(35)
10. Measure the output ripple at no load and full load with a scope, and make sure it is within specifications.
5.
Repeat Step 4 until the cold and hot voltage measurements remain the same.
RCS1( NEW ) =
1 RCS1(OLD ) x RTH (25C ) + (RCS1(OLD ) - RCS2 ( NEW ) ) x (RCS1(OLD ) - RTH (25 C ) ) RCS1(OLD ) + RTH (25C ) - 1 RTH (25 C )
(37)
Rev. A | Page 23 of 28
ADP3188
AC Loadline Setting
11. Remove the dc load from the circuit and hook up the dynamic load. 12. Hook up the scope to the output voltage and set it to dc coupling, with the time scale at 100 s/div. 13. Set the dynamic load for a transient step of about 40 A at 1 kHz with a 50% duty cycle. 14. Measure the output waveform (if not visible, use dc offset on scope to view). Try to use a vertical scale of 100 mV/div or finer. This waveform should look similar to Figure 15.
VDROOP
Initial Transient Setting 19. With the dynamic load still set at the maximum step size, expand the scope time scale to see 2 s/div to 5 s/div. The waveform may have two overshoots and one minor undershoot (see Figure 16). Here, VDROOP is the final desired value.
VTRAN1
VACDRP
Figure 16. Transient Setting Waveform
VDCDRP
20. If both overshoots are larger than desired, try making these adjustments: Note that if these adjustments do not change the response, the output decoupling is the limiting factor. Check the output response every time a change is made, or nodes are switched, to make sure the response remains stable. * * * Make the ramp resistor larger by 25% (RRAMP). For VTRAN1, increase CB, or increase the switching frequency. For VTRAN2, increase RA, and decrease CA by 25%.
04835-015
Figure 15. AC Loadline Waveform
15. Use the horizontal cursors to measure VACDRP and VDCDRP as shown. Do not measure the undershoot or overshoot that happens immediately after this step. 16. If VACDRP and VDCDRP are different by more than a few millivolts, use Equation 38 to adjust CCS. It may be necessary to parallel different values to get the correct one as there are limited standard capacitor values available. It is a good idea to have locations for two capacitors in the layout for this.
C CS ( NEW ) = C CS (OLD ) x V ACDRP V DCDRP
(38)
21. For load release (see Figure 17), if VTRANREL is larger than VTRAN1 (see Figure 16), there is not enough output capacitance. Either more capacitance is needed, or the inductor values need to be smaller. (If inductors are changed, start the design again using the spreadsheet and this tuning procedure.)
17. Repeat Steps 11 to 13, and repeat the adjustments if necessary. Once complete, do not change CCS for the remainder of the procedure.
VTRANREL
18. Set the dynamic load step to maximum step size (do not use a step size larger than needed) and verify that the output waveform is square, which means that VACDRP and VDCDRP are equal.
VDROOP
Figure 17. Transient Setting Waveform
Rev. A | Page 24 of 28
04835-0-017
04835-0-016
VTRAN2
ADP3188
Because the ADP3188 turns off all of the phases (switches inductors to ground), there is no ripple voltage present during load release. Thus, headroom does not need to be added for ripple, allowing load release VTRANREL to be larger than VTRAN1 by the amount of ripple, and still meet specifications. If VTRAN1 and VTRANREL are less than the desired final droop, this implies that capacitors can be removed. When removing capacitors, also check the output ripple voltage to make sure it is still within specifications.
Rev. A | Page 25 of 28
ADP3188
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal performance of a switching regulator in a PC system.
POWER CIRCUITRY RECOMMENDATIONS
The switching power path should be routed on the PCB to encompass the shortest possible length in order to minimize radiated switching noise energy (EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. Whenever a power dissipating component, for example, a power MOSFET, is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. This improves current rating through the vias and also improves thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heat-sink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation to the air around the board. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components.
GENERAL RECOMMENDATIONS
For good results, a PCB with at least four layers is recommended. This allows the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the remainder of the power delivery current paths. Keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53 m at room temperature. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths. Then, the resistance and inductance introduced by these current paths is minimized, and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3188) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground noisier. An analog ground plane should be used around and under the ADP3188 as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and not tied to any other power circuitry to prevent power currents from flowing in it. The components around the ADP3188 should be located close to the controller with short traces. The most important traces to keep short, and away from other traces, are the FB and CSSUM pins. The output capacitors should be connected as close as possible to the load (or connector), for example, a microprocessor core, that receives the power. If the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic. Avoid crossing any signal lines over the switching power path loop, as described next.
SIGNAL CIRCUITRY RECOMMENDATIONS
The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential-mode noise pickup in the sensed signal, the loop area should be small. Thus, the FB and FBRTN traces should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller.
Rev. A | Page 26 of 28
ADP3188
OUTLINE DIMENSIONS
9.80 9.70 9.60
28
15
4.50 4.40 4.30 6.40 BSC
1 14
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 8 0 0.75 0.60 0.45
SEATING PLANE
0.20 0.09
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 18. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters
0.390 BSC
28
15
0.154 BSC
1 14
0.236 BSC
PIN 1 0.065 0.049 0.069 0.053 8 0
0.010 0.004 COPLANARITY 0.004
0.025 BSC
0.012 0.008
SEATING PLANE
0.010 0.006
0.050 0.016
COMPLIANT TO JEDEC STANDARDS MO-137AF
Figure 19. 28-Lead Shrink Small Outline Package [QSOP] (RQ-28) Dimensions shown in inches
ORDERING GUIDE
Model ADP3188JRUZ-REEL1 ADP3188JRQZ-REEL1
1
Temperature Range 0C to 85C 0C to 85C
Package Description Thin Shrink Small Outline Package 13" Reel Shrink Small Outline Package 13" Reel
Package Option RU-28 RQ-28
Quantity per Reel 2500 2500
Z = Pb-free part.
Rev. A | Page 27 of 28
ADP3188
NOTES
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04835-0-4/05(A)
Rev. A | Page 28 of 28

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