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256K
X28HC256
5 Volt, Byte Alterable EEPROM
DESCRIPTION
32K x 8 Bit
FEATURES * Access time: 70ns * Simple byte and page write --Single 5V supply --No external high voltages or VPP control circuits --Self-timed --No erase before write --No complex programming algorithms --No overerase problem * Low power CMOS --Active: 60mA --Standby: 500A * Software data protection --Protects data against system level inadvertent writes * High speed page write capability * Highly reliable Direct WriteTM cell --Endurance: 1,000,000 cycles --Data retention: 100 years * Early end of write detection --DATA polling --Toggle bit polling
The X28HC256 is a second generation high performance CMOS 32K x 8 EEPROM. It is fabricated with Xicor's proprietary, textured poly floating gate technology, providing a highly reliable 5 Volt only nonvolatile memory. The X28HC256 supports a 128-byte page write operation, effectively providing a 24s/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0.8 seconds. The X28HC256 also features DATA Polling and Toggle Bit Polling, two methods of providing early end of write detection. The X28HC256 also supports the JEDEC standard Software Data Protection feature for protecting against inadvertent writes during power-up and power-down. Endurance for the X28HC256 is specified as a minimum 1,000,000 write cycles per byte and an inherent data retention of 100 years.
BLOCK DIAGRAM
256Kbit EEPROM Array
X Buffers Latches and Decoder A0-A14 Address Inputs Y Buffers Latches and DECODER
I/O Buffers and Latches
CE OE WE VCC VSS
Control Logic and Timing
I/O0-I/O7 Data Inputs/Outputs
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X28HC256
PIN CONFIGURATION
Plastic DIP CERDIP Flat Plastic SOIC
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 X28HC256 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 10 11 12 29 28 27 26 A8 A9 A11 NC OE A10 CE I/O7 I/O6
I/O1 12 I/O0 11 A1 9 A3 7 A5 I/O 2 13 A0 10
TSOP LCC PLCC
VCC A12 A14 A13 WE NC A7
A2 A1 A0 I/O 0 I/O 1 I/O 2 NC VSS NC I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CE A10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A3 A4 A5 A6 A7 A 12 A 14 NC VCC NC WE A13 A8 A9 A 11 OE
4
3
2
1 32 31 30
X28HC256
X28HC256 (Top View)
25 24 23 22
13 21 14 15 16 17 18 19 20 I/O1 I/O2 I/O3 I/O4 VSS I/O5 NC
PGA
I/O3 15 VSS 14 I/O5 17 I/O4 16 I/O 6 18 I/O 7 19 A 10 21 A11 23 A8 25 A13 26
A2 CE 8 20 X28HC256 A4 OE 6 22 A12 2 A7 3 VCC 28 A14 A9 24 WE 27
5
A6 4
1
(Bottom View)
PIN DESCRIPTIONS Addresses (A0-A14) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers, and is used to initiate read operations. Data In/Data Out (I/O0-I/O7) Data is written to or read from the X28HC256 through the I/O pins.
Write Enable (WE) The Write Enable input controls the writing of data to the X28HC256. PIN NAMES Symbol
A0-A14 I/O0-I/O7 WE CE OE VCC VSS NC
Description
Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect
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X28HC256
DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28HC256 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 3ms. Page Write Operation The page write feature of the X28HC256 allows the entire memory to be written in typically 0.8 seconds. Page write allows up to one hundred twenty-eight bytes of data to be consecutively written to the X28HC256, prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A7 through A14) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twentyseven bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100s, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100s. Write Operation Status Bits The X28HC256 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. Figure 1. Status Bit Assignment
I/O
DP
TB
5
4
3
2
1
0
Reserved Toggle Bit DATA Polling
DATA Polling (I/O7) The X28HC256 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28HC256. This eliminates additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Toggle Bit (I/O6) The X28HC256 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease, and the device will be accessible for additional read and write operations.
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X28HC256
DATA POLLING I/O7 Figure 2. DATA Polling Bus Sequence
WE Last Write
CE
OE VIH I/O7 HIGH Z VOL A0-A14 An An An An An An An
VOH X28HC256 Ready
Figure 3. DATA Polling Software Flow
Write Data
DATA Polling can effectively halve the time for writing to the X28HC256. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method of implementing the routine.
Writes Complete? Yes Save Last Data and Address
No
Read Last Address
IO7 Compare? Yes
No
X28HC256 Ready
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X28HC256
THE TOGGLE BIT I/O6 Figure 4. Toggle Bit Bus Sequence
Last WE Write
CE
OE
I/O6
VOH * VOL
HIGH Z
*
X28C512/513 Ready
* I/O6 Beginning and ending state of I/O6 will vary.
Figure 5. Toggle Bit Software Flow
HARDWARE DATA PROTECTION The X28HC256 provides two hardware features that protect nonvolatile data from inadvertent writes. - Default VCC Sense--All write functions are inhibited when VCC is 3.5V typically. - Write Inhibit--Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. SOFTWARE DATA PROTECTION
Last Write Yes
Load Accum From Addr n
Compare Accum with Addr n
Compare ok? Yes
No
The X28HC256 offers a software-controlled data protection feature. The X28HC256 is shipped from Xicor with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/ down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable. The X28HC256 can be automatically protected during power-up and power-down (without the need for external circuits) by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation, utilizing the software algorithm. This circuit is nonvolatile, and will remain set for the life of the device unless the reset command is issued. Once the software protection is enabled, the X28HC256 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device.
Characteristics subject to change without notice.
X28C256 Ready
The Toggle Bit can eliminate the chore of saving and fetching the last address and data in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28HC256 memories that is frequently updated. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit.
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X28HC256
SOFTWARE ALGORITHM Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. SOFTWARE DATA PROTECTION Figure 6. Timing Sequence--Byte or Page Write
VCC 0V Data Address CE tBLC MAX WE Byte or Age AAA 5555 55 2AAA A0 5555 Writes ok (VCC)
The three-byte sequence opens the page write window, enabling the host to write from one to one hundred twenty-eight bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state.
tWC
Write Protected
Figure 7. Write Sequence for Software Data Protection
Write Data AA to Address 5555
Write Data 55 to Address 2AAA
Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the X28HC256 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the X28HC256 will be write protected during power-down and after any subsequent power-up. Note: Once initiated, the sequence of write operations should not be interrupted.
Write Data A0 to Address 5555 Write Data XX to Any Address Byte/Page Load Enabled
Write Last Byte to Last Address
Optional Byte/Page Load Operation
After tWC Re-Enters Data Protected State
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X28HC256
RESETTING SOFTWARE DATA PROTECTION Figure 8. Reset Software Data Protection Timing Sequence
VCC AAA 5555 55 2AAA 80 5555 AA 5555 55 2AAA 20 5555 Standard Operating Mode
Data Address CE
tWC
WE
Figure 9. Write Sequence for resetting Software Data Protection
Write Data AA to Address 5555
In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the X28HC256 will be in standard operating mode. Note: Once initiated, the sequence of write operations should not be interrupted. SYSTEM CONSIDERATIONS Because the X28HC256 is frequently used in large memory arrays, it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation, and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit, it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation, this assures that all deselected devices are in their standby mode, and that only the selected device(s) is/are outputting data on the bus. Because the X28HC256 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the l/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended
Write Data 55 to Address 2AAA
Write Data 80 to Address 5555
Write Data AA to Address 5555
Write Data 55 to Address 2AAA
Write Data 20 to Address 5555
After tWC, Re-Enters Unprotected State
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X28HC256
that a 0.1F high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. In addition, it is recommended that a 4.7F electrolytic bulk capacitor be placed between VCC and VSS for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces.
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X28HC256
ABSOLUTE MAXIMUM RATINGS Temperature under bias X28HC256 ...................................... -10C to +85C X28HC256I, X28HC256M............. -65C to +135C Storage temperature ........................ -65C to +150C Voltage on any pin with respect to VSS ........................................-1V to +7V D.C. output current ............................................. 10mA Lead temperature (soldering, 10 seconds)........ 300C RECOMMENDED OPERATING CONDITIONS Temperature
Commercial Industrial Military
COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Min.
0C -40C -55C
Max.
+70C +85C +125C
Supply Voltage
X28HC256
Limits
5V 10%
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol
ICC ISB1 ISB2 ILI ILO VlL
(2) (2)
Parameter
VCC active current (TTL Inputs) VCC standby current (TTL Inputs) VCC standby current (CMOS Inputs) Input leakage current Output leakage current Input LOW voltage Input HIGH voltage Output LOW voltage Output HIGH voltage
Min.
Typ.(7)
30 1 200
Max.
60 2 500 10 10
Unit
mA mA A A A V V V V IOL = 6mA IOH = -4mA
Test Conditions
CE = OE = VIL, WE = VIH, All I/O's = open, address inputs = .4V/2.4V levels @ f = 10MHz CE = VIH, OE = VIL, All I/O's = open, other inputs = VIH CE = VCC - 0.3V, OE = GND, All I/Os = open, other inputs = VCC - 0.3V VIN = VSS to VCC VOUT = VSS to VCC, CE = VIH
-1 2 2.4
0.8 VCC + 1 0.4
VIH
VOL VOH
Notes: (1) Typical values are for TA = 25C and nominal supply voltage. (2) VIL min. and VIH max. are for reference only and are not tested.
POWER-UP TIMING Symbol
tPUR
(3) (3)
Parameter
Power-up to read Power-up to write
Max.
100 5
Unit
s ms
tPUW
Note:
(3) This parameter is periodically sampled and not 100% tested.
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X28HC256
CAPACITANCE TA = +25C, f = 1MHz, VCC = 5V Symbol
CI/O CIN
(9) (9)
Test
Input/output capacitance Input capacitance
Max.
10 6
Unit
pF pF
Conditions
VI/O = 0V VIN = 0V
ENDURANCE AND DATA RETENTION Parameter
Endurance Data retention
Min.
1,000,000 100
Max.
Unit
Cycles Years
A.C. CONDITIONS OF TEST
Input pulse levels Input rise and fall times Input and output timing levels 0V to 3V 5ns 1.5V
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
MODE SELECTION CE
L L H X X
OE
L H X L X
WE
H L X X H
Mode
Read Write Standby and write inhibit Write inhibit Write inhibit
I/O
DOUT DIN High Z -- --
Power
active active standby -- --
EQUIVALENT A.C. LOAD CIRCUIT
5V 1.92K OUTPUT 1.37K 30pF
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X28HC256
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read Cycle Limits X28HC256-70 X28HC256-90 X28HC256-12 X28HC256-15 Symbol
tRC tCE tAA
(5) (5)
Parameter
Read cycle time Chip enable access time Address access time Output enable access time CE LOW to active output OE LOW to active output CE HIGH to high Z output OE HIGH to high Z output Output hold from address change
Min.
70
Max.
70 70 35
Min.
90
Max.
90 90 40
Min.
120
Max.
120 120 50
Min.
150
Max.
150 150 50
Unit
ns ns ns ns ns ns
(5)
tOE tLZ(4) tOLZ tHZ
(4) (4) (4)
0 0 35 35 0
0 0 40 40 0
0 0 50 50 0
0 0 50 50 0
ns ns ns
tOHZ
tOH
Read Cycle
tRC Address tCE CE tOE OE VIH WE tOLZ tLZ Data I/O HIGH Z Data Valid tAA Notes: (4) tLZ min., tHZ, tOLZ min. and tOHZ are periodically sampled and not 100% tested, tHZ and tOHZ are measured with CL = 5pF, from the point when CE, OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven. (5) For faster 256K products, refer to X28VC256 product line. tOH tHZ Data Valid tOHZ
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X28HC256
Write Cycle Limits Symbol
tWC
(7)
Parameter
Write cycle time Address setup time Address hold time Write setup time Write hold time CE pulse width OE HIGH setup time OE HIGH hold time WE pulse width WE HIGH recovery (page write only) Data valid Data setup Data hold Delay to next write after polling is true Byte load cycle
Min.
0 50 0 0 50 0 0 50 50
Typ.(6)
3
Max.
5
Unit
ms ns ns ns ns ns ns ns ns ns
tAS tAH tCS tCH tCW tOES tOEH tWP tWPH(8) tDV tDS tDH tDW
(8)
1 50 0 10 0.15 100
s ns ns s s
tBLC
Notes: (6) Typical values are for TA = 25C and nominal supply voltage. (7) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. (8) tWPH and tDW are periodically sampled and not 100% tested.
WE Controlled Write Cycle
tWC Address tAS tCS CE tAH tCH
OE tOES tWP WE tOEH
Data In tDS
Data Valid tDH HIGH Z
Data Out
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X28HC256
CE Controlled Write Cycle
tWC Address tAS CE tOES OE tOEH tCS WE tCH tAH tCW
Data In tDS Data Out HIGH Z
Data Valid tDH
Page Write Cycle
OE(9)
CE tWP WE tWPH tBLC
Address(10)
I/O Byte 0 Byte 1 Byte 2 Byte n Byte n+1
Last Byte Byte n+2 tWC
*For each successive write within the page write operation, A7-A15 should be the same or writes to an unknown address could occur. Notes: (9) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. (10)The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing.
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X28HC256
DATA Polling Timing Diagram(11)
Address
An
An
An
CE
WE tOEH tOES
OE tDW I/O7 DIN = X DOUT = X tWC DOUT = X
Toggle Bit Timing Diagram(11)
CE
WE tOEH OE tDW I/O6 HIGH Z * tWC * I/O6 beginning and ending state will vary, depending upon actual tWC. Note: (11)Polling operations are by definition read cycles and are therefore subject to read cycle timings. * tOES
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X28HC256
PACKAGING INFORMATION 28-Lead Ceramic Flat Pack Type F
Pin 1 Index 1 28
0.019 (0.48) 0.015 (0.38)
0.050 (1.27) BSC 0.740 (18.80) Max.
0.045 (1.14) Max. 0.440 (11.18) Max. 0.130 (3.30) 0.090 (2.29)
0.006 (0.15) 0.003 (0.08) 0.370 (9.40) 0.250 (6.35) Typ. 0.300 2 Plcs.
0.180 (4.57) Min.
0.045 (1.14) 0.025 (0.66)
0.030 (0.76) Min.
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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X28HC256
PACKAGING INFORMATION 28-Lead Ceramic Pin Grid Array Package Type K
12 11 9 7 5 4
13 10 8 6 2 3
15 14
17 16 20 22
18 19 A 0.008 (0.20) 21 23 25 26 0.050 (1.27) A NOTE: LEADS 4,12,18 & 26
28 1
24 27
Typ. 0.100 (2.54) All Leads
0.080 (2.03) 0.070 (1.78)
Pin 1 Index
0.080 (2.03) 4 Corners 0.070 (1.78) 0.110 (2.79) 0.090 (2.29) 0.072 (1.83) 0.062 (1.57)
0.020 (0.51) 0.016 (0.41)
0.660 (16.76) 0.640 (16.26)
A A 0.561 (14.25) 0.541 (13.75) 0.185 (4.70) 0.175 (4.44)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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X28HC256
PACKAGING INFORMATION 28-Lead Plastic Dual In-Line Package Type P
1.470 (37.34) 1.400 (35.56)
0.557 (14.15) 0.510 (12.95) Pin 1 Index Pin 1 1.300 (33.02) Ref. 0.085 (2.16) 0.040 (1.02)
Seating Plane 0.160 (4.06) 0.120 (3.05)
0.160 (4.06) 0.125 (3.17) 0.030 (0.76) 0.015 (0.38)
0.110 (2.79) 0.090 (2.29)
0.065 (1.65) 0.040 (1.02)
0.022 (0.56) 0.014 (0.36)
0.625 (15.88) 0.590 (14.99)
Typ. 0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
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X28HC256
PACKAGING INFORMATION 28-Lead Plastic Small Outline Gull Wing Package Type S
0.299 (7.59) 0.290 (7.37)
0.419 (10.64) 0.394 (10.01)
0.020 (0.508) 0.014 (0.356)
0.713 (18.11) 0.697 (17.70) 0.105 (2.67) 0.092 (2.34) 0.012 (0.30) 0.003 (0.08)
Base Plane Seating Plane
0.050 (1.270) BSC
0.050" Typical 0.0200 (0.5080) X 45 0.0100 (0.2540) 0.013 (0.32) 0.008 (0.20) 0.050" Typical 0.42" Max.
0 - 8
0.0350 (0.8890) 0.0160 (0.4064)
FOO TPRINT
0.030" Typical 28 Places
NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
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X28HC256
PACKAGING INFORMATION 32-Lead Hermetic Dual In-Line Package Type D
1.690 (42.95) Max.
0.610 (15.49) 0.500 (12.70)
Pin 1 0.005 (0.13) Min. 0.100 (2.54) Max.
Seating Plane 0.232 (5.90) Max. 0.060 (1.52) 0.015 (0.38)
0.150 (3.81) Min.
0.200 (5.08) 0.125 (3.18)
0.110 (2.79) 0.090 (2.29) Typ. 0.100 (2.54)
0.065 (1.65) 0.033 (0.84) Typ. 0.055 (1.40)
0.023 (0.58) 0.014 (0.36) Typ. 0.018 (0.46)
0.620 (15.75) 0.590 (14.99) Typ. 0.614 (15.60)
0.015 (0.38) 0.008 (0.20)
0 15
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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X28HC256
PACKAGING INFORMATION 32-Pad Ceramic Leadless Chip Carrier Package Type E
0.300 (7.62) BSC 0.150 (3.81) BSC 0.015 (0.38) 0.003 (0.08) 0.020 (0.51) x 45 Ref.
Pin 1
0.095 (2.41) 0.075 (1.91) 0.022 (0.56) 0.006 (0.15) DIA.
0.200 (5.08) BSC 0.015 (0.38) Min. 0.028 (0.71) 0.022 (0.56) (32) Plcs.
0.055 (1.39) 0.045 (1.14) TYP. (4) PLCS.
0.050 (1.27) BSC
0.040 (1.02) x 45 Ref. Typ. (3) Plcs.
0.458 (11.63) 0.442 (11.22) 0.458 (11.63) -- 0.120 (3.05) 0.060 (1.52)
0.088 (2.24) 0.050 (1.27)
0.560 (14.22) 0.540 (13.71)
0.558 (14.17) --
0.400 (10.16) BSC
Pin 1 Index Corner
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: 1% NLT 0.005 (0.127)
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X28HC256
PACKAGING INFORMATION 32-Lead Plastic Leaded Chip Carrier Package Type J
0.420 (10.67)
0.050" Typical
0.030" Typical 32 Places
0.510" Typical 0.400" 0.050 (1.27) Typ.
0.050" Typical
FOOTPRINT
0.300" Ref. 0.410"
0.021 (0.53) 0.045 (1.14) x 45 0.013 (0.33) Typ. 0.017 (0.43) Seating Plane 0.004 Lead CO - Planarity -- 0.015 (0.38) 0.095 (2.41) 0.060 (1.52) 0.140 (3.56) 0.100 (2.45) Typ. 0.136 (3.45) 0.048 (1.22) 0.042 (1.07)
0.495 (12.57) 0.485 (12.32) Typ. 0.490 (12.45) 0.453 (11.51) 0.447 (11.35) Typ. 0.450 (11.43) 0.300 (7.62) Ref. Pin 1
0.595 (15.11) 0.585 (14.86) Typ. 0.590 (14.99) 0.553 (14.05) 0.547 (13.89) Typ. 0.550 (13.97) 0.400 (10.16)Ref. 3 Typ.
NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
REV 1.1 2/1/01
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Characteristics subject to change without notice.
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X28HC256
PACKAGING INFORMATION 32-Lead Thin Small Outline Package (TSOP) Type T
See Note 2 12.50 (0.492) 12.30 (0.484) Pin #1 Ident. O 0.76 (0.03)
0.50 (0.0197) BSC See Note 2 8.02 (0.315) 7.98 (0.314) 0.26 (0.010) 0.14 (0.006)
1.18 (0.046) 1.02 (0.040) 0.17 (0.007) 0.03 (0.001) Seating Plane 0.58 (0.023) 0.42 (0.017)
14.15 (0.557) 13.83 (0.544)
14.80 0.05 (0.583 0.002) 0.30 0.05 (0.012 0.002) Typical 32 Places 15 Eq. Spc. 0.50 0.04 0.0197 0.016 = 7.50 0.06 (0.295 0.0024) Overall Tol. Non-Cumulative
Solder Pads
0.17 (0.007) 0.03 (0.001) FOOTPRINT
0.50 0.04 1.30 0.05 (0.051 0.002) (0.0197 0.0016)
NOTE: 1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES). REV 1.1 2/1/01
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Characteristics subject to change without notice.
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X28HC256
Ordering Information X28HC256 Device X X -X Access Time -70 = 70ns -90 = 90ns -12 = 120ns -15 = 150ns Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C M = Military = -55C to +125C MB = MIL-STD-883 Package P = 28-Lead Plastic DIP D = 28-Lead CERDIP J = 32-Lead PLCC S = 28-Lead plastic SOIC E = 32-Pad LCC K = 28-Pin grid array F = 28-Lead flat pack T = 32-Lead TSOP
LIMITED WARRANTY
(c)Xicor, Inc. 2000 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
REV 1.1 2/1/01
www.xicor.com
Characteristics subject to change without notice.
23 of 23

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