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VSP2254
www.ti.com
SLES063 - DECEMBER 2002
36 MHz SAMPLE TWO CHANNEL CCD SIGNAL PROCESSOR
FEATURES D TWO CHANNEL CCD SIGNAL PROCESSING:
- Correlated Double Sampling
D 75-dB SNR D 14-BIT A/D CONVERSION:
- No Missing Codes
APPLICATIONS D Digital Video Camera (DVC) D Digital Still Camera (DSC) D Front End for Dual Channel CCD DESCRIPTION
The VSP2254 is a high-speed and high-resolution mixedsignal processing IC for CCD signal processing, which integrates two channels of correlated double sampling (CDS) and a 14-bit analog-to-digital converter. The VSP2254 also provides black level clamping for an accurate black level reference, input signal clamping, and offset correction of the CDS. The VSP2254 operates from 2.7 V to 3.6 V of single supply.
D PORTABLE OPERATION:
- - - Low Voltage: 2.7 V to 3.6 V Low Power: 210 mW (typ) at 2.7 V Power-Down Mode: 14 mW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
VSP2254
www.ti.com SLES063 - DECEMBER 2002
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
PRODUCT PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE -25C to 85C 25C PACKAGE MARKING VSP2254 ORDERING NUMBER(1) VSP2254GSJ VSP2254GSJ BGA 96 GSJ VSP2254GSJR (1) For the most current specification and package information, refer to our web site at www.ti.com. TRANSPORT MEDIA Tray Tape and reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) UNITS Supply voltage, VCC, VDD Supply voltage differences, among VCC terminals Ground voltage differences, AGND, DGND Digital input voltage Analog input voltage Input current (any pins except supplies) Ambient temperature under bias Storage temperature, Tstg Junction temperature TJ Lead temperature (soldering) 4V 0.1 V 0.1 V -0.3 V to (VDD + 0.3 V) -0.3 V to (VCC + 0.3 V) 10 mA -40C to 125C -55C to 150C 150C 260C, 5 s
Package temperature (IR reflow, peak) 260C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
all specifications at TA = 25C, all power supply voltages = 3 V, and conversion rate = 27 MHz, unless otherwise noted(1) PARAMETER Resolution Channel Maximum conversion rate DIGITAL INPUTS Logic family VIT+ VIT- IIH IIL Positive-going input threshold voltage Negative-going input threshold voltage Input current ADC clock duty cycle Input capacitance DIGITAL OUTPUT (Channel A/B) Logic family Logic coding VOH VOL Output voltage Logic high, IOH = -2 mA Logic low, IOL = 2 mA 2.4 0.4 CMOS Straight Binary V V Logic high, VIN = 3 V Logic low, VIN = 0 V 50% 5 pF CMOS 1.7 1 20 20 V V A A 36 TEST CONDITIONS MIN TYP 14 2 MHz MAX UNIT Bits
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VSP2254
www.ti.com SLES063 - DECEMBER 2002
ELECTRICAL CHARACTERISTICS (continued)
all specifications at TA = 25C, all power supply voltages = 3 V, and conversion rate = 27 MHz, unless otherwise noted(1) PARAMETER ANALOG INPUT (Channel A/B) Input signal level for FS out Input capacitance Input limit TRANSFER CHARACTERISTICS (Channel A/B) Differential nonlinearity Integral nonlinearity No missing codes Step response settling time Overload recovery time Data latency Signal-to-noise ratio(1) Channel separation CCD offset correction range Optical black clamp level CDS (Channel A/B) Reference sample settling time Data sample settling time INPUT CLAMP (Channel A/B) Clamp-on resistance Clamp level OBCLP LOOP DAC resolution Minimum DAC output current Maximum DAC output current Loop time constant Slew rate REFERENCE (Channel A/B) Positive reference voltage Negative reference voltage POWER SUPPLY VCC, VDD PD Supply voltage Power dissipation At VCC = 3 V, fCLK = 36 MHz Power-down mode (fCLK = 0 MHz) -25 55 2.7 3 210 14 85 3.6 V mW mW C C/W 1.75 1.25 V V Time constant for ADCOUT code from 0 LSB to 1543 LSB (14 bit), CCOB = 0.1 F ADCOUT CODE above 1543 LSB (14 bit), CCOB = 0.1 F 10 0.15 153 40.7 1530 bits A A s V/s 400 1.5 V Within 1 LSB, driver impedance = 50 Within 1 LSB, driver impedance = 50 6.9 6.9 ns ns -180 512 Grounded input cap Full-scale step input Step input from 1.8 V to 0 V 2 8 Assured 1 2 8 (fixed) 75 80 200 pixels pixels clocks dB dB mV LSB LSB LSB -0.3 900 10 3.3 1100 mV pF V TEST CONDITIONS MIN TYP MAX UNIT
TEMPERATURE RANGE Operation temperature JA Thermal resistance (1) SNR = 20 log (full-scale voltage/rms noise)
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VSP2254
www.ti.com SLES063 - DECEMBER 2002
PIN ASSIGNMENTS
1 2 3 4 5 6 7 8 9 10
A
SHP_A
B1_A
B3_A
B6_A
B8_A
B11_A
B13_A
VCC
NC
NC
B
SHD_A
B0_A
B2_A
B5_A
B9_A
B10_A
AGND
COB_A
BYPCM_A
BYPM_A
C
NC
AGND
VCC
B4_A
B7_A
B12_A
AGND
BYPP_A
AGND
CCDIN_A
D
ADCCK
NC
NC
NC
NC
NC
NC
VCC
REFN_A
CM_A
E
VDD
DGND
STB
NC
NC
NC
AGND
REFP_A
F
AGND
DGND
CLPDM
NC
NC
NC
VCC
REFP_B
G
CLPOB
PBLK
NC
NC
NC
NC
NC
VCC
REFN_B
CM_B
H
AGND
VCC
B2_B
B5_B
B8_B
B13_B
VCC
NC
AGND
CCDIN_B
J
SHD_B
SHP_B
B3_B
B6_B
B10_B
B11_B
AGND
BYPP_B
NC
BYPM_B
K
B0_B
B1_B
B4_B
B7_B
B9_B
B12_B
AGND
COB_B
NC
BYPCM_B
NOTE: The corner of the A1 position is indicated on the device top by a dot.
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VSP2254
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Terminal Functions
TERMINAL NAME ADCCK AGND B0_A B0_B B1_A B1_B B10_A B10_B B11_A B11_B B12_A B12_B B13_A B13_B B2_A B2_B B3_A B3_B B4_A B4_B B5_A B5_B B6_A B6_B B7_A B7_B B8_A B8_B B9_A B9_B BYPCM_A BYPCM_B BYPM_A BYPM_B BYPP_A BYPP_B CCDIN_A CCDIN_B CLPDM NO. D1 B7, C2, C7, C9, E9, F1, H1, H9, J7, K7 B2 K1 A2 K2 B6 J5 A6 J6 C6 K6 A7 H6 B3 H3 A3 J3 C4 K3 B4 H4 A4 J4 C5 K4 A5 H5 B5 K5 B9 K10 B10 J10 C8 J8 C10 H10 F3 TYPE(1) DI P DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO AO AO AO AO AO AO AI AI DI Clock for ADC output Analog ground A-channel ADC output bit 0 B-channel ADC output bit 0 (LSB) A-channel ADC output bit 1 B-channel ADC output bit 1 A-channel ADC output bit 10 B-channel ADC output bit 10 A-channel ADC output bit 11 B-channel ADC output bit 11 A-channel ADC output bit 12 B-channel ADC output bit 12 A-channel ADC output bit 13 (MSB) B-channel ADC output bit 13 (MSB) A-channel ADC output bit 2 B-channel ADC output bit 2 A-channel ADC output bit 3 B-channel ADC output bit 3 A-channel ADC output bit 4 B-channel ADC output bit 4 A-channel ADC output bit 5 B-channel ADC output bit 5 A-channel ADC output bit 6 B-channel ADC output bit 6 A-channel ADC output bit 7 B-channel ADC output bit 7 A-channel ADC output bit 8 B-channel ADC output bit 8 A-channel ADC output bit 9 B-channel ADC output bit 9 A-channel CDS common reference, bypass-to-ground by a 0.1-F capacitor B-channel CDS common reference, bypass-to-ground by a 0.1-F capacitor A-channel CDS negative reference, bypass-to-ground by a 500-pF to 1000-pF capacitor B-channel CDS negative reference, bypass-to-ground by a 500-pF to 1000-pF capacitor A-channel CDS positive reference, bypass-to-ground by a 500-pF to 1000-pF capacitor B-channel CDS positive reference, bypass-to-ground by a 500-pF to 1000-pF capacitor A-channel CCD signal input B-channel CCD signal input Dummy clamp pulse, (active low) DO: Digital Output, AI: Analog Input, AO: Analog Output. DESCRIPTION
(1) P: Power Supply and Ground,
DI: Digital Input,
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VSP2254
www.ti.com SLES063 - DECEMBER 2002
Terminal Functions (Continued)
TERMINAL NAME CLPOB CM_A CM_B COB_A COB_B DGND NC NO. G1 D10 G10 B8 K8 E2 F2 A9, A10, C1, D2, D3, D4, D5, D6, D7, E4, E7, E8, F4, F7, F8, G3-G7, H8, J9, K9 G2 D9 G9 E10 F10 B1 J1 A1 J2 E3 A8, C3, D8, E1, F9, G8, H2 H7 E1 TYPE(1) DI AO AO AO AO P P - Digital ground for digital outputs Not connected, must be open Optical black clamp pulse, (active low) A-channel ADC common reference, bypass-to-ground by a 0.1-F capacitor B-channel ADC common reference, bypass-to-ground by a 0.1-F capacitor A-channel OBC loop output voltage, connect a 0.1-F capacitor between ground B-channel OBC loop output voltage, connect a 0.1-F capacitor between ground DESCRIPTION
PBLK REFN_A REFN_B REFP_A REFP_B SHD_A SHD_B SHP_A SHP_B STB VCC VDD
DI AO AO AO AO DI DI DI DI DI P P
A/D output preblanking. Low: all 0, High: normal output A-channel ADC negative reference, bypass-to-ground a 0.1-F capacitor B-channel ADC negative reference, bypass-to-ground by a 0.1-F capacitor A-channel ADC positive reference, bypass-to-ground by a 0.1-F capacitor B-channel ADC positive reference, bypass-to-ground by a 0.1-F capacitor A-channel CCD data sampling pulse, (active low) B-channel CCD data sampling pulse, (active low) A-channel CCD ref sampling pulse, (active low) B-channel CCD ref sampling pulse, (active low) Standby, low: normal operation, high: standby Analog power supply Digital supply for digital outputs DO: Digital Output, AI: Analog Input, AO: Analog Output.
(1) P: Power Supply and Ground,
DI: Digital Input,
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VSP2254
www.ti.com SLES063 - DECEMBER 2002
FUNCTIONAL BLOCK DIAGRAM
BYPP
COB
BYPM BYPCM
REFP
CM
REFN
A-Channel Internal Reference
Buf
Current DAC
Decoder
CCD Out Signal
Clamp
CDS
CCDIN_A
14-Bit A-to-D Converter
Output Register
14-Bit Digital Output (A-Channel)
SHP_A SHD_A ADCCK SHP_B SHD_B Timing / Control
CLPOB CLPDM PBLK STB
CCDIN_B
CDS
14-Bit A-to-D Converter
Output Register
14-Bit Digital Output (B-Channel)
CCD Out Signal
Clamp
Buf
Current DAC
Decoder
B-Channel Internal Reference
BYPP
COB
BYPM
BYPCM
REFP
CM
REFN
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VSP2254
www.ti.com SLES063 - DECEMBER 2002
TIMING SPECIFICATION
Timing Specifications (for each channel)
N CCD N+1 N+2 N+3
tw(P) SHP
t(CKP)
t(DP) td(S) t(PD) tw(D) t(CKP)
SHD
t(INHIBIT) t(ADC)
td(S) t(CKP) t(ADC)
ADCCK
th
td(O)
B[13:0]
N-9
N-8
N-7
N-6
N-5
PARAMETER t(CKP) t(ADC) tw(P) tw(D) t(PD) t(DP) td(S) t(INHIBIT) th td(O) Clock period ADCCK high or low level SHP pulse width SHD pulse width SHP rising edge to SHD falling edge SHD rising edge To SHP falling edge Sampling delay Inhibited clock period Output hold time Output delay
MIN 27 10
MAX 13.8 6.9 6.9
MAX
UNIT ns ns ns ns ns ns ns
4 6.9 3 10 7 27 8 20
ns ns ns clocks
DL Data latency (1) t(WP) + t(PD) should be nearly equal to t(WD) + t(DP).
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VSP2254
www.ti.com SLES063 - DECEMBER 2002
SYSTEM OVERVIEW
Introduction
The VSP2254 is a two channel high-resolution mixed-signal IC that contains key features associated with the processing of the CCD signal in a DVC. The VSP2254 integrates two channels of independent CCD processing path. Figure 1 shows a simplified block diagram of one channel of the VSP2254. The device includes a correlated double sampler (CDS), a 14-bit analog to digital converter (ADC), a black-level clamp loop, input clamp, timing generator, and voltage reference. An off-chip emitter follower buffer or preamp is needed between the CCD output and the VSP2254 CCDIN input. Both channels are driven common SHP/SHD, ADCCK, CLPOB, CLPDM, and STB.
CLPOB ADCCK CLPOB STB
10-Bit DAC
Decoder
CCD Input CLPDM
CDS
14-Bit ADC
Output Register
14-Bit Output
Input Clamp
ADCCK
PBLK
STB
Figure 1. Simplified Block Diagram of VSP2254 (One Channel) Correlated Double Sampler (CDS)
The output signal of a CCD image sensor is sampled twice during one pixel period: once at the reference interval and again at the data interval. Subtracting these two samples extracts the video information of the pixel and removes any noise which is common--or correlated--to both the intervals. Thus, a CDS is important to reduce the reset noise and the low-frequency noises that are present on the CCD output signal. Figure 2 shows the block diagram of the CDS. The CDS is driven through an off-chip coupling capacitor CIN. (A 0.1-F capacitor is recommended for CIN.) AC-coupling is highly recommended, because the dc level of the CCD output signal is usually too high (several volts) for the CDS to work properly. The appropriate common-mode voltage for the CDS is around 0.5 V-1.5 V. The reference level sampling is performed while SHP is active and the voltage level is held on the sampling capacitor C1 at the trailing edge of SHP. The data level sampling is performed while SHD is active and the voltage level is held on the sampling capacitor C2 at the trailing edge of SHD. Then the subtraction of the two levels is performed by the switched-capacitor amplifier. The off-chip emitter follower buffer must be able to drive more than 10 pF, because the 10-pF sampling capacitor is seen at the input pin. (Usually, additional stray capacitance of a few pico farads is present.) The analog input signal range of the VSP2254 is about 1 Vp-p.
SHP C1 CCD Input CIN + OPA _ C2 SHD SHP
CLPDM
CM
Figure 2. Block Diagram of CDS and Input Clamp
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VSP2254
www.ti.com SLES063 - DECEMBER 2002
Input Clamp
The buffered CCD output is capacitively coupled to the VSP2254. The purpose of the input clamp is to restore the dc component of the input signal, which was lost with the ac-coupling and establish the desired dc bias point for the CDS. Figure 2 shows the block diagram of the input clamp. The input level is clamped to the internal reference voltage CM (1.5 V) during the dummy pixel interval. More specifically, the clamping function becomes active when both CLPDM and SHP are active.
14-Bit A/D Converter
The ADC utilizes a fully differential pipelined architecture of 1.5 bit per stage, which is well-suited for low-power, low-voltage and high-speed applications. The ADC assures 14-bit resolution for the entire full scale. The 1.5 bit per stage structure of the ADC is advantageous to realize a better linearity for a smaller signal level, because large linearity errors tend to occur at specific points in the full scale and the linearity gets better for a level of signal below that specific point.
Black Level Clamp Loop and 10-Bit DAC
To extract the video information correctly, the CCD signal must be referenced to a well-established black level. The VSP2254 has an auto-zero loop (calibration loop) to establish the black level using the CCD's optical black (OB) pixels. Figure 3 shows the block diagram of the black level clamp loop. The input signal level from the OB pixels is identified as the real black level and the loop is closed during this period (actually during the period while CLPOB = ACTIVE). While the auto-zero loop is closed, the difference between the ADC output code is evaluated and applied to the decoder, which then controls the 10-bit current DAC. The current DAC can charge or discharge the external capacitor at COB, dependent on the sign of the code difference. The loop adjusts the voltage at COB, which sets the offset of the CDS so as to make the code difference zero. Thus, the ADC output code converges to black level during CLPOB = ACTIVE and the black level derived from the OB pixels after the loop has converged. CLPOB performs OB clamp of both channels simultaneously. A 0.1-F bypass capacitor is recommended for COB and with this capacitor, the loop's time constant is 40.7 s (typ) for the ADC output code from 0 LSB to 1543 LSB (the convergence curve becomes exponential). For the output code above 1543 LSB, the current DAC injects constant (maximum) current into the capacitor and the convergence curve becomes linear. The slew rate for that is 1530 V/s (typ). The loop not only eliminates the CCD's own black level offset, but also eliminates the offset of the VSP2254's CDS and ADC themselves.
PBLK ADCCK STB
CCDIN
CDS
14-Bit ADC
Output Register
To Output
BYPP
Buffer 10-Bit Current DAC
Decoder
CLPOB
COB ADCCK STB CLPOB
Off Chip
On Chip
Figure 3. Block Diagram of Digital PGA and Black Level Clamp Loop Preblanking and Data Latency
The VSP2254 has an input blanking (or preblanking) function. When PBLK = low, digital outputs all become zero at the ninth rising edge of ADCCK, counting from when PBLK becomes low to accommodate the clock latency of the VSP2254.
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VSP2254
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Data latency of the VSP2254 is seven clock cycles. The digital output data comes out at the rising edge of ADCCK with a delay of seven clock cycles. Some CCDs have large transient output signals during blanking intervals. If the input voltage is higher than the supply rail or lower than the ground rail by 0.3 V, then protection diodes are turned on preventing the input voltage from going further. Such a high-swing signal may cause damage to the VSP2254 and should be avoided.
Standby Mode
For the purpose of power saving, the VSP2254 can be put into the standby mode (power-down mode) by forcing the STB input to a high level when the device is not in use. In this mode, all the function blocks are disabled and the digital outputs all go to zero. The consumption current drops to 5 mA. As all the bypass capacitors discharge during this mode, a substantial time (usually of the order of 200 ms-300 ms) is required to restore from the standby mode. STB is effective for both channels.
Timings
The CDS and the ADC are operated by SHP, SHD, and their derivative timing clocks generated by the on-chip timing generator. The output register and decoder are operated by ADCCK. The digital output data is synchronized with ADCCK. The timing relationship between the CCD signal, SHP, SHD, ADCCK, and the output data is shown on the VSP2254 timing specification. CLPOB is used to activate the black level clamp loop during the OB pixel interval and CLPDM is used to activate the input clamping during the dummy pixel interval. In the standby mode, ADCCK, SHP, SHD, CLPOB, and CLPDM are internally masked and pulled high.
Voltage Reference
All the reference voltages and bias currents used on the device are created from an internal band gap circuitry. The VSP2254 has symmetrical independent voltage reference for each channel. Both channels of the CDS and the ADC use three main reference voltages, REFP (1.75 V), REFN (1.25 V), and CM (1.5 V) of the individual reference. REFP and REFN are buffered on-chip. CM is derived as the mid-voltage of the resistor chain connecting REFP and REFN internally. The ADC's full scale range is determined by twice the difference voltage between REFP and REFN. REFP, REFN, and CM should be heavily decoupled with appropriate capacitors.
Power Supply, Grounding, and Device Decoupling Recommendations
The VSP2254 incorporates a high-precision, high-speed AD converter and analog circuitry, which are vulnerable to any extraneous noise from the rails or elsewhere. The driver stage of the digital outputs (B[13:0]) is supplied through a dedicated supply pin (VDD) and should be separated from the other supply pins completely or at least with a ferrite bead. This ensures the most consistent results, since digital power lines often carry high levels of wide-band noise that would otherwise be coupled into the device and degrade the achievable performance. It is ecommended that analog and digital ground pins of the VSP2254 be separated. Proper grounding, short lead length, and the use of ground planes are also important for high-frequency designs. Multilayer PC boards are recommended for the best performance, since they offer distinct advantages like minimizing ground impedance, separation of signal layers by ground layers, etc. It is also recommended to keep the capacitive loading on the output data lines as low as possible (typically less than 15 pF). Larger capacitive loads demand higher charging current surges, which can feed back into the analog portion of the VSP2254 and affect the performance. If possible, external buffers or latches should be used, which provide the added benefit of isolating the VSP2254 from any digital noise activities on the data lines. In addition, resistors in series with each data line may help minimizing the surge current. Values in the range of 100 to 200 limits the instantaneous current the output stage has to provide for recharging the parasitic capacitance as the output levels change from low-to-high or high-to-low. Because of the high-operation speed, the converter also generates high-frequency current transients and noises that are fed back into the supply and reference lines. This requires the supply and reference pins to be sufficiently bypassed. In most cases, 0.1-F ceramic chip capacitors are adequate to decouple the reference pins. Supply pins should be decoupled to the ground plane with a parallel combination of tantalum (1 F-22 F) and ceramic (0.1 F) capacitors. The effectiveness of the decoupling largely depends on the proximity to the individual pin. VDD should be decoupled to the proximity of DGND. Attention must be paid to the bypassing of COB, BYPP, and BYPM, since these capacitor values determine important analog performances of the device.
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VSP2254
www.ti.com SLES063 - DECEMBER 2002
MECHANICAL DATA
GSJ (S-PBGA-N96) PLASTIC BALL GRID ARRAY
9,10 SQ 8,90
7,20 TYP 0,80 K J H G F E 0,40
A1 Corner
D C B A 1 2 3 4 5 6 7 8 9 10
Bottom View 0,35 0,25
1,20 MAX
Seating Plane 0,50 0,40
0,08
0,45 MAX
0,08
4204222/A 02/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. MicroStar Junior package configuration. Fall within JEDEC MO-225.
MicroStar Junior is a trademark of Texas Instruments. 12
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Copyright 2002, Texas Instruments Incorporated

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