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DATA SHEET
PD78F0058,78F0058Y
8-BIT SINGLE-CHIP MICROCONTROLLERS
MOS INTEGRATED CIRCUIT
DESCRIPTION
The PD78F0058 is a product of the PD780058 Subseries in the 78K/0 Series and equivalent to the PD780058 with a flash memory in place of internal ROM. This device is incorporated with a flash memory which can be programmed without being removed from the substrate. The PD78F0058Y is a products based on the PD78F0058, with an I2C bus interface supporting multimaster. Functions are described in detail in the following user's manuals, which should be read when carrying out design work.
PD780058, 780058Y Subseries User's Manual
78K/0 Series User's Manual Instruction
:U12013E :U12326E
FEATURES * Pin-compatible with mask * Flash memory * Internal high-speed RAM * Internal expansion RAM * Buffer RAM * Power supply voltage
ROM version (except VPP pin) : 60 KbytesNote 1 : 1024 bytes : 1024 bytesNote 2 : 32 bytes : VDD = 2.7 to 5.5 V
Notes 1. The flash memory capacity can be changed with the memory size switching register (IMS). 2. The internal expansion RAM capacity can be changed with the internal expansion RAM size switching register (IXS). Remark For the differences between the flash memory versions and the mask ROM versions, refer to 1. DIFFERENCES BETWEEN PD78F0058, 78F0058Y, AND MASK ROM VERSION.
APPLICATION FIELDS
Car audio systems, cellular phones, pagers, printers, AV equipment, cameras, PPCs, vending machines, etc.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U12092EJ1V0DS00 (1st edition) Date Published March 2000 N CP(K) Printed in Japan The mark shows major revised points.
(c)
1997, 2000
PD78F0058, 78F0058Y
ORDERING INFORMATION
Part Number Package 80-pin plastic QFP (14 x 14 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.05 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.0 mm) 80-pin plastic QFP (14 x 14 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.05 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.0 mm)
PD78F0058GC-8BT PD78F0058GK-BE9 PD78F0058GK-9EUNote PD78F0058YGC-8BT PD78F0058YGK-BE9 PD78F0058YGK-9EUNote
Note Under development
2
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries name.
Products under development Products in mass production Y subseries products supports the I2C bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780065 PD780078 PD780034A PD780024A PD78014H PD78018F PD78083
Inverter control
EMI-noise reduced version of the PD78078
PD78078Y PD78070AY PD780018AY PD780058Y PD78058FY PD78054Y PD780078Y PD780034AY PD780024AY PD78018FY
PD78054 with timer and enhanced external interface
ROM-less version of the PD78078
PD78078Y with enhanced serial I/O and limited functions PD78054 with enhanced serial I/O
EMI-noise reduced version of the PD78054
PD78018F with UART and D/A converter and enhanced I/O PD780024A with expanded RAM PD780034A with timer and enhanced serial I/O PD780024A with enhanced A/D converter PD78018F with enhanced serial I/O
EMI-noise reduced version of the PD78018F Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V)
64-pin
PD780988
FIPTM drive
On-chip inverter control circuit and UART. EMI-noise reduced version.
100-pin 100-pin 80-pin 80-pin 78K/0 Series 80-pin
PD780208 PD780228 PD780232 PD78044H PD78044F
LCD drive
PD78044F with enhanced I/O and FIP C/D. Display output total: 53 PD78044H with enhanced I/O and FIP C/D. Display output total: 48
For panel control. On-chip FIP C/D. Display output total: 53
PD78044F with N-ch open drain I/O. Display output total: 34
Basic subseries for FIP drive. Display output total: 34
100-pin 100-pin 100-pin
PD780308 PD78064B PD78064
Call ID
PD780308Y PD78064Y
PD78064 with enhanced SIO and expanded ROM and RAM EMI-noise reduced version of the PD78064
Basic subseries for LCD drive, on-chip UART
80-pin
PD780841
Bus interface
On-chip Call ID function, simplified DTMF. EMI-noise reduced version.
100-pin 80-pin 80-pin 80-pin 64-pin
PD780948 PD78098B PD780701Y PD780833Y PD780814
Meter control
On-chip DCAN controller
PD78054 with IEBusTM controller. EMI-noise reduced version.
On-chip DCAN/IEBus controller On-chip J1850 (CLASS2) controller Special in DCAN controller function
100-pin 80-pin 80-pin 80-pin
PD780958 PD780955 PD780852 PD780824
Industrial meter control Ultra low-power consumption. On-chip UART. On-chip controller/driver for automotive meter drive For automotive meter drive. On-chip DCAN controller
Data Sheet U12092EJ1V0DS00
3
PD78F0058, 78F0058Y
The major functional differences among the subseries are listed below.
Function Subseries Name Control ROM Capacity 8-Bit 10-Bit 8-Bit 8-bit 16-bit Watch WDT A/D A/D D/A 1 ch 1 ch 1 ch 8 ch - 2 ch Timer Serial Interface 3 ch (UART: 1 ch) VDD MIN. External Value Expansion 1.8 V
I/O 88
PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780065 PD780078
32 K to 40K 4 ch 48 K to 60K - 24 K to 60 K 2 ch
61 3 ch (time-division UART: 1 ch) 3 ch (UART: 1 ch) 68
2.7 V 1.8 V
48 K to 60 K 16 K to 60 K 40 K to 48 K 48 K to 60 K 2 ch 1 ch 8 ch - - 8 ch -
69
2.7 V 2.0 V
4 ch (UART: 1 ch) 3 ch (UART: 2 ch) 3 ch (UART: 1 ch)
60 52 51
2.7 V 1.8 V
PD780034A 8 K to 32 K PD780024A PD78014H PD78018F PD78083
Inverter control FIP drive 8 K to 60 K 8 K to 16 K
2 ch
53
-
- - 1 ch - 8 ch -
1 ch (UART: 1 ch) 3 ch (UART: 2 ch)
33 47 4.0 V
-
PD780988
16 K to 60 K 3 ch Note
PD780208 PD780228 PD780232 PD78044H PD78044F
32 K to 60 K 2 ch 48 K to 60 K 3 ch 16 K to 24 K 32 K to 48 K 2 ch 16 K to 40 K 48 K to 60 K 2 ch
1 ch -
1 ch -
1 ch
8 ch
-
-
2 ch 1 ch
74 72 40 68
2.7 V 4.5 V
-
4 ch 1 ch 1ch 8 ch
2 ch 1 ch 2 ch
2.7 V
LCD drive
PD780308 PD78064B PD78064
1 ch
1ch
1 ch
8 ch
-
-
3 ch (time-division UART: 1 ch) 2 ch (UART: 1 ch)
57
2.0 V
-
32 K 16 K to 32 K 24 K to 32 K 1 ch 60 K 40 K to 60 K 32 K to 60 K 48 K to 60 K 4 ch 40 K 6 ch 2 ch 1 ch 2 ch 1 ch 2 ch 2 ch 1 ch 1 ch - 1 ch 12 ch - 1 ch 5 ch - 1 ch 1 ch 1 ch 1 ch 2 ch 8 ch - - - - 2 ch - -
Call ID Bus interface supported Meter control
PD780841 PD780948 PD78098B PD780814 PD780958 PD780955 PD780852 PD780824
2 ch (UART: 1 ch) 3 ch (UART: 1 ch)
57 79 69
2.7 V 4.0 V 2.7 V 4.0 V 2.2 V
- -
2 ch (UART: 1 ch) 2 ch (UART: 1 ch) 2 ch (UART: 2 ch) 3 ch (UART: 1 ch) 2 ch (UART: 1 ch)
46 69 50 56 59
-
32 K to 40 K 3 ch 32 K to 60 K
4.0 V 4.0 V
Note 16-bit timer: 2 channels 10-bit timer: 1 channel
4
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
The major functional differences among the Y subseries are shown below.
Function ROM Capacity Subseries Name Control Configuration of Serial Interface I/O VDD MIN. Value 48 K to 60 K - 48 K to 60 K 3-wire/2-wire/I C : 1 ch 3-wire with automatic transmit/receive function : 1 ch 3-wire/UART : 1 ch 3-wire with automatic transmit/receive function : 1 ch Time-division 3-wire : 1 ch I2C bus (multimaster supported) : 1 ch 3-wire/2-wire/I2C : 1 ch 3-wire with automatic transmit/receive function : 1 ch 3-wire/time-division UART : 1 ch 3-wire/2-wire/I2C : 1 ch 3-wire with automatic transmit/receive function : 1 ch 3-wire/UART : 1 ch 3-wire UART 3-wire/UART I2C bus (multimaster supported) UART 3-wire I2C bus (multimaster supported) : 1 ch : 1 ch : 1 ch : 1 ch : 1 ch : 1 ch : 1 ch
2
PD78078Y PD78070AY PD780018AY
88 61 88
1.8 V 2.7 V
PD780058Y
24 K to 60 K
68
1.8 V
PD78058FY PD78054Y PD780078Y
48 K to 60 K 16 K to 60 K 48 K to 60 K
69
2.7 V 2.0 V
52
1.8 V
PD780034AY PD780024AY PD78018FY
LCD drive
8 K to 32 K
51
1.8 V
8 K to 60 K 48 K to 60 K
3-wire/2-wire/I2C : 1 ch 3-wire with automatic transmit/receive function : 1 ch 3-wire/2-wire/I2C 3-wire/time-division UART 3-wire 3-wire/2-wire/I2C 3-wire/UART : 1 ch : 1 ch : 1 ch : 1 ch : 1 ch
53 57 2.0 V
PD780308Y
PD78064Y
16 K to 32 K
Remark The functions other than the serial interface are common to the Subseries without Y.
Data Sheet U12092EJ1V0DS00
5
PD78F0058, 78F0058Y
OVERVIEW OF FUNCTIONS
Product Name Item Internal memory Flash memory High-speed RAM Buffer RAM Expanded RAM Memory space General registers Minimum instruction execution time When main system clock is selected When subsystem clock is selected 60 Kbytes 1,024 bytes 32 bytes 1,024 bytes 64 Kbytes 8 bits x 32 registers (8 bits x 8 registers x 4 banks) 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (@5.0 MHz operation) 122 s (@32.768 kHz operation) * * * * 16-bit operation Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjust, etc. 68 2 62 4
PD78F0058
PD78F0058Y
Instruction set
I/O ports
Total: * CMOS input: * CMOS I/O: * N-ch open-drain I/O:
A/D converter D/A converter Serial interface
* 8-bit resolution x 8 channels (VDD = 2.7 to 5.5 V) * 8-bit resolution x 2 channels (VDD = 2.7 to 5.5 V) * 3-wire serial I/O/2-wire serial I/O/ * 3-wire serial I/O/SBI/2-wire serial I2C mode selectable: 1 channel I/O mode selectable: 1 channel * 3-wire serial I/O mode (automatic data transmit/receive function for up to 32 bytes provided on chip): 1 channel * 3-wire/serial I/O/UART mode (time division transfer function provided on chip) selectable: 1 channel * * * * 16-bit timer/event counter: 8-bit timer/event counter: Watch timer: Watchdog timer: 1 2 1 1 channel channels channel channel
Timers
Timer outputs Clock output
3 (14-bit PWM output x 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (@5.0 MHz operation with main system clock) 32.768 kHz (@32.768 kHz operation with subsystem clock) 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@5.0 MHz operation with main system clock) Maskable Non-maskable Software Internal: 13, External: 6 Internal: 1 1 Internal: 1, External: 1 VDD = 2.7 to 5.5 V TA = -40 to +85C * 80-pin plastic QFP (14 x 14 mm) * 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.05 mm) * 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.0 mm)
Buzzer output Vectored interrupt sources Test inputs Supply voltage Operating ambient temperature Package
6
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ...........................................................................................
8
2. BLOCK DIAGRAM .......................................................................................................................... 10 3. DIFFERENCES BETWEEN PD78F0058, 78F0058Y, AND MASK ROM VERSIONS ............... 11
3.1 Memory Size Switching Register (IMS) ................................................................................................ 12 3.2 Internal Expansion RAM Size Switching Register (IXS) .................................................................... 13
4. PIN FUNCTIONS ............................................................................................................................. 14
4.1 Port Pins ................................................................................................................................................... 14 4.2 Non-Port Pins ........................................................................................................................................... 16 4.3 Pin I/O Circuits and Recommended Connection of Unused Pins .................................................... 18
5. MEMORY SPACE ........................................................................................................................... 22 6. FLASH MEMORY PROGRAMMING ............................................................................................... 23
6.1 Selection of Transmission Mode ........................................................................................................... 23 6.2 Function of Flash Memory Programming ............................................................................................ 24 6.3 Connection of Flashpro III ...................................................................................................................... 24 6.4 Example of Settings for Flashpro III (PG-FP3) .................................................................................... 26
7. ELECTRICAL SPECIFICATIONS .................................................................................................. 27 8. 9. PACKAGE DRAWINGS ................................................................................................................. 56 RECOMMENDED SOLDERING CONDITIONS ........................................................................... 59
APPENDIX A. DEVELOPMENT TOOLS .......................................................................................... 61 APPENDIX B. RELATED DOCUMENTS .......................................................................................... 64
Data Sheet U12092EJ1V0DS00
7
PD78F0058, 78F0058Y
1. PIN CONFIGURATION (TOP VIEW)
* 80-pin plastic QFP (14 x 14 mm)
PD78F0058GC-8BT, 78F0058YGC-8BT
* 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.05 mm)
PD78F0058GK-BE9, 78F0058YGK-BE9
* 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.0 mm)
PD78F0058GK-9EUNote, 78F0058YGK-9EUNote
Note Under development
P01/INTP1/TI01 P00/INTP0/TI00 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P14/ANI4 P13/ANI3 P12/ANI2 P10/ANI0 P11/ANI1 XT1/P07
AVREF0
VDD0
VDD1
P15/ANI5 P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RxD0 P71/SO2/TxD0 P72/SCK2/ASCK P20/SI1 P21/SO1 P22/SCK1 P23/STB/TxD1 P24/BUSY/RxD1 P25/SI0/SB0 [/SDA0] P26/SO0/SB1 [/SDA1] P27/SCK0 [/SCL] P40/AD0 P41/AD1
1 2 3 4 5 6 7 8 9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
VSS0
XT2
VPP
X1
X2
RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RTP2 P121/RTP1 P120/RTP0 P37 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR
10 11 12 13 14 15 16 17 18 19
41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P56/A14
P57/A15
P60
P61
P62
P63
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P52/A10
P53/A11
P54/A12
Cautions 1. 2.
Connect the VPP pin directly to VSS0 or VSS1 in normal operation mode. Connect the AVSS pin to VSS0. ]: PD78F0058Y only.
Remarks 1. [
2. When the microcontroller is used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended.
8
Data Sheet U12092EJ1V0DS00
P55/A13
P64/RD
P50/A8
P51/A9
VSS1
PD78F0058, 78F0058Y
PIN IDENTIFICATION
A8 to A15 AD0 to AD7 ANI0 to ANI7 ANO0, ANO1 ASCK ASTB AVREF0, AVREF1 AVSS BUSY BUZ : Address Bus : Address/Data Bus : Analog Input : Analog Output : Asychronous Serial Clock : Address Strobe : Analog Reference Voltage : Analog Ground : Busy : Buzzer Clock RD RESET RTP0 to RTP7 RxD0, RxD1 SB0, SB1 SCK0 to SCK2 SCL SDA0, SDA1 SI0 to SI2 SO0 to SO2 STB TI00, TI01 TI1, TI2 TO0 to TO2 TxD0, TxD1 VDD0, VDD1 VPP VSS0, VSS1 WAIT WR X1, X2 XT1, XT2 : Read Strobe : Reset : Real-Time Output Port : Receive Data : Serial Bus : Serial Clock : Serial Clock : Serial Data : Serial Input : Serial Output : Strobe : Timer Input : Timer Input : Timer Output : Transmit Data : Power Supply : Programming Power Supply : Ground : Wait : Write Strobe : Crystal (Main System Clock) : Crystal (Subsystem Clock)
INTP0 to INTP5 : Interrupt from Peripherals P00 to P05, P07 : Port 0 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P72 P120 to P127 P130, P131 PCL : Port 1 : Port 2 : Port 3 : Port 4 : Port 5 : Port 6 : Port 7 : Port 12 : Port 13 : Programmable Clock
Data Sheet U12092EJ1V0DS00
9
PD78F0058, 78F0058Y
2. BLOCK DIAGRAM
TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34 P00 P01 to P05 P07 P10 to P17
16-bit timer/ event counter
Port 0
8-bit timer/ event counter 1 8-bit timer/ event counter 2
Port 1
Port 2
P20 to P27
Port 3 Watchdog timer
P30 to P37
Watch timer
Port 4
P40 to P47
SI0/SB0 [/SDA0] /P25 SO0/SB1 [/SDA1] /P26 SCK0 [/SCL] /P27 SI1/P20 SO1/P21 SCK1/P22 STB/TxD1/P23 BUSY/RxD1/P24 BUSY/RxD1/P24 STB/TxD1/P23 SI2/RxD0/P70 SO2/TxD0/P71 SCK2/ASCK/P72 ANI0/P10 to ANI7/P17 AVSS AVREF0
Serial interface 0 78K/0 CPU core Serial interface 1 FLASH MEMORY
Port 5
P50 to P57
Port 6
P60 to P67
Port 7
P70 to P72
Port 12 Serial interface 2 RAM Port 13
P120 to P127
P130, P131
A/D converter
Real-time output port
RTP0/P120 to RTP7/P127
ANO0/P130, ANO1/P131 AVSS AVREF1 INTP0/P00 to INTP5/P05
D/A converter
External access
Interrupt control
AD0/P40 to AD7/P47 A8/P50 to A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67
BUZ/P36
Buzzer output System control
PCL/P35
Clock output control
VDD0, VDD1
VSS0, VSS1
VPP
RESET X1 X2 XT1/P07 XT2
Remark [
]: PD78F0058Y only.
10
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
3. DIFFERENCES BETWEEN PD78F0058, 78F0058Y, AND MASK ROM VERSIONS
The PD78F0058 and 78F0058Y are products provided with a flash memory which enables on-board reading, erasing, and rewriting of programs with device mounted on target system. The functions of the PD78F0058 and 78F0058Y (except the functions specified for flash memory and mask option of P60 to P63 pins) can be made the same as those of the mask ROM versions by setting the memory size switching register (IMS) and internal expansion RAM size switching register (IXS). Table 3-1 shows the differences between the flash memory version (PD78F0058, 78F0058Y) and the mask ROM versions (PD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y,780056Y, and 780058Y). Table 3-1. Differences between PD78F0058, 78F0058Y and Mask ROM Versions
Item
PD78F0058
PD78F0058Y
Mask ROM Versions
PD780058 Subseries
Internal ROM structure Internal ROM capacity Flash memory 60 Kbytes Mask ROM
PD780058Y Subseries
PD780053, PD780054, PD780055, PD780056, PD780058, PD780053, PD780054, PD780055, PD780056, PD780058,
780053Y 780054Y 780055Y 780056Y 780058Y 780053Y 780054Y 780055Y 780056Y 780058Y
: : : : : : : : : :
24 32 40 48 60
Kbytes Kbytes Kbytes Kbytes Kbytes
Internal expansion RAM capacity
1024 bytes
None None None None 1024 bytes
Internal ROM capacity changeable/not changeable with memory size switching register (IMS) Internal expansion RAM capacity changeable/not changeable with internal expansion RAM size switching register (IXS) Supply voltage IC pin VPP pin P60 to P63 pin mask option with internal pull-up resistors Serial interface (SBI) Serial interface (I C)
2
ChangeableNote 1
Not changeable
ChangeableNote 2
Not changeable
VDD = 2.7 to 5.5 V Not provided Provided Not provided
VDD = 1.8 to 5.5 V Provided Not provided Provided
Provided Not provided
Not provided Provided
Provided Not provided
Not provided Provided
Notes 1. Flash memory is set to 60 Kbytes by RESET input. 2. Internal expansion RAM is set to 1024 bytes by RESET input. Caution The noise resistance and noise radiation differ between flash memory versions and mask ROM versions. When considering the replacement of flash memory versions with mask ROM versions in the process from trial manufacturing to mass production, adequate evaluation should be carried out using CS products (not ES products) of mask ROM versions. Remark Only the PD780058, 780058Y, 78F0058, and 78F0058Y are provided with IXS.
Data Sheet U12092EJ1V0DS00
11
PD78F0058, 78F0058Y
3.1 Memory Size Switching Register (IMS)
This register sets a part of internal memory unused by software. The memory mapping can be made the same as that of mask ROM versions with different types of internal memory (ROM and RAM) by setting the memory size switching register (IMS). The IMS is set with an 8-bit memory manipulation instruction. RESET input sets the IMS to CFH. Figure 3-1. Format of Memory Size Switching Register
Symbol IMS 7 RAM2 6 5 4 0 3 2 1 0 Address FFF0H At reset CFH R/W R/W
RAM1 RAM0
ROM3 ROM2 ROM1 ROM0
ROM3 ROM2 ROM1 ROM0 Selection of Internal ROM Capacity 0 1 1 1 1 1 Others 1 0 0 1 1 1 1 0 1 0 1 1 0 0 0 0 0 1 24 Kbytes 32 Kbytes 40 Kbytes 48 Kbytes 56 KbytesNote 60 Kbytes Setting prohibited
RAM2 RAM1 RAM0 1 Others 1 0
Selection of Internal High-speed RAM Capacity 1024 bytes Setting prohibited
Note When using external device expansion function, set the internal ROM capacity to less than 56 Kbytes. Table 3-2 shows the IMS set value to make the memory mapping the same as those of mask ROM versions. Table 3-2. Set Value of Memory Size Switching Register
Target Mask ROM Versions IMS Set Value C6H C8H CAH CCH CFH
PD780053, 780053Y PD780054, 780054Y PD780055, 780055Y PD780056, 780056Y PD780058, 780058Y
12
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
3.2 Internal Expansion RAM Size Switching Register (IXS)
This register sets the internal expansion RAM capacity by software. The memory mapping can be made the same as that of mask ROM versions with different types of internal expansion RAM by setting the internal expansion RAM size switching register (IXS). The IXS is set with an 8-bit memory manipulation instruction. RESET input sets the IXS to 0AH. Figure 3-2. Format of Internal Expansion RAM Size Switching Register
Symbol IXS
7 0
6 0
5 0
4 0
3
2
1
0
Address FFF4H
At reset 0AH
R/W W
IXRAM3 IXRAM2 IXRAM1 IXRAM0
IXRAM3 IXRAM2 IXRAM1 IXRAM0 Selection of Internal Expansion RAM Capacity 1 1 Others 1 0 0 1 0 0 0 bytes 1024 bytes Setting prohibited
Table 3-3 shows the IXS set value to make the memory mapping the same as those of mask ROM versions. Table 3-3. Set Value of Internal Expansion RAM Size Switching Register
Target Mask ROM Versions IMS Set Value 0CH
PD780053, 780053Y PD780054, 780054Y PD780055, 780055Y PD780056, 780056Y PD780058, 780058Y
0AH
Data Sheet U12092EJ1V0DS00
13
PD78F0058, 78F0058Y
4. PIN FUNCTIONS 4.1 Port Pins (1/2)
Pin Name P00 P01 P02 P03 P04 P05 P07Note 1 P10 to P17 Input I/O Input only Port 1 8-bit input/output port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of softwareNote 2. Port 2 8-bit input/output port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software. Input Input I/O Input I/O Port 0 7-bit input/output port Function Input only Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software. After Reset Input Input Alternate Function INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 XT1 ANI0 to ANI7
P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47
I/O
Input
SI1 SO1 SCK1 STB/TxD1 BUSY/RxD1 SI0/SB0 [/SDA0] SO0/SB1 [/SDA1] SCK0 [/SCL]
I/O
Port 3 8-bit input/output port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software.
Input
TO0 TO1 TO2 TI1 TI2 PCL BUZ -
I/O
Port 4 8-bit input/output port Input/output can be specified in 8-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software. The test input flag (KRIF) is set to 1 by falling edge detection.
Input
AD0 to AD7
Notes 1. When using the P07/XT1 pins as an input port, set bit 6 (FRC) of the processor clock control register (PCC) to 1. Do not use the on-chip feedback resistor of the subsystem clock oscillator. 2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input pins, set port 1 to the input mode. At this time, on-chip pull-up resistors are automatically disconnected. Remark [ ]: PD78F0058Y only.
Data Sheet U12092EJ1V0DS00
14
PD78F0058, 78F0058Y
4.1 Port Pins (2/2)
Pin Name I/O Function After Reset Input Alternate Function A8 to A15
P50 to P57
I/O
Port 5 8-bit input/output port LEDs can be driven directly. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software. N-ch open-drain input/output port Port 6 LEDs can be driven directly. 8-bit input/outport port Input/output can be specified in 1-bit units.
P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72
I/O
Input
-
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
RD WR WAIT ASTB
I/O
Port 7 3-bit input/output port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software. Port 12 8-bit input/output port Input/output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistor can be specified by means of software. Port 13 2-bit input/output port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software.
Input
SI2/RxD0 SO2/TxD0 SCK2/ASCK
P120 to P127
I/O
Input
RTP0 to RTP7
P130, P131
I/O
Input
ANO0, ANO1
Data Sheet U12092EJ1V0DS00
15
PD78F0058, 78F0058Y
4.2 Non-Port Pins (1/2)
Pin Name I/O Function After Reset Input Alternate Function P00/TI00 P01/TI01 P02 P03 P04 P05 Input Serial interface serial data input Input P25/SB0 [/SDA0] P20 P70/RxD Output Serial interface serial data output Input P26/SB1 [/SDA1] P21 P71/TxD I/O Serial interface serial data input/output Input P25/SI0 [/SDA0] P26/SO0 [/SDA1]
INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 SI0 SI1 SI2 SO0 SO1 SO2 SB0 SB1 SDA0 SDA1 SCK0 SCK1 SCK2 SCL STB BUSY RxD0 RxD1 TxD0 TxD1 ASCK TI00 TI01 TI1 TI2 TO0 TO1 TO2 PCL BUZ RTP0 to RTP7 AD0 to AD7
Input
External interrupt request input for which the valid edge (rising edge, falling edge, or both rising edge and falling edges) can be specified.
PD78F0058Y only
P25/SI0/SB0 P26/SO0/SB1
I/O
Serial interface serial clock input/output
Input
P27 [/SCL] P22 P72/ASCK
PD78F0058Y only
Output Input Input Serial interface automatic transmit/receive strobe output Serial interface automatic transmit/receive busy input Asynchronous serial interface serial data input Input Input Input
P27/SCK0 P23/TxD1 P24/RxD1 P70/SI2 P24/BUSY
Output
Asynchronous serial interface serial data output
Input
P71/SO2 P23/STB
Input Input
Asynchronous serial interface serial clock input External count clock input to the 16-bit timer (TM0) Capture trigger signal input to the capture register (CR00) External count clock input to the 8-bit timer (TM1) External count clock input to the 8-bit timer (TM2)
Input Input
P72/SCK2 P00/INTP0 P01/INTP1 P33 P34
Output
16-bit timer (TM0) output (also used for 14-bit PWM output) 8-bit timer (TM1) output 8-bit timer (TM2) output
Input
P30 P31 P32
Output Output Output I/O
Clock output (for trimming of main system clock and subsystem clock) Buzzer output Real-time output port from which data is output in synchronization with a trigger Lower address/data bus for expanding memory externally
Input Input Input Input
P35 P36 P120 to P127 P40 to P47
Remark [
]: PD78F0058Y only.
Data Sheet U12092EJ1V0DS00
16
PD78F0058, 78F0058Y
4.2 Non-Port Pins (2/2)
Pin Name I/O Function After Reset Input Input Alternate Function P50 to P57 P64 P65 Input Input P66 P67 P10 to P17 P130, P131 - - -
A8 to A15 RD WR WAIT ASTB
Output Output
Higher address bus for expanding memory externally Strobe signal output for reading from external memory Strobe signal output for writing to external memory
Input Output
Wait insertion at external memory access Strobe output that externally latches address information output to ports 4 and 5 to access external memory. A/D converter analog input D/A converter analog output A/D converter reference voltage input (also used for analog power supply) D/A converter reference voltage input A/D converter and D/A converter ground potential Use at the same potential as VSS0. System reset input Connecting crystal resonator for main system clock oscillation
ANI0 to ANI7 ANO0, ANO1 AVREF0 AVREF1 AVSS
Input Output Input Input - Input Input - Input - - - - - -
Input Input - - -
RESET X1 X2 XT1 XT2 VDD0 VSS0 VDD1 VSS1 VPP
- - -
- - - P07 - - - - - -
Connecting crystal resonator for subsystem clock oscillation
Input -
Port block positive power supply Port block ground potential Positive power supply (except for port and analog blocks) Ground potential (except for port and analog blocks) Setting flash memory programming mode. Applying high voltage for program write/verify. Connect directly to VSS0 or VSS1 in normal operation mode.
- - - - -
Data Sheet U12092EJ1V0DS00
17
PD78F0058, 78F0058Y
4.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 4-1. For the input/output circuit configuration of each type, see Figure 4-1. Table 4-1. Input/Output Circuit Type of Each Pin (1/2)
Pin Name Input/Output Circuit Type 2 8-C I/O Recommended Connection
P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P07/XT1 P10/ANI0 to P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB/TxD1 P24/BUSY/RxD1 P25/SI0/SB0 [/SDA0] P26/SO0/SB1 [/SDA1] P27/SCK0 [/SCL] P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 P40/AD0 to P47/AD7
Input I/O
Connect to VSS0. Input : Independently connect to VSS0 via a resistor. Output : Leave open.
16 11-D 8-C 5-H 8-C 5-H 8-C 10-B
Input I/O
Connect to VDD0. Input : Independently connect to VDD0 or VSS0 via a resistor.
Output : Leave open.
5-H
8-C
5-H
5-N
Input : Independently connect to VDD0 via a resistor. Output : Leave open. Input : Independently connect to VDD0 or VSS0 via a resistor. Output : Leave open. Input : Independently connect to VDD0 via a resistor. Output : Leave open. Input : Independently connect to VDD0 or VSS0 via a resistor. Output : Leave open.
P50/A8 to P57/A15
5-H
P60 to P63
13-K
P64/RD P65/WR P66/WAIT P67/ASTB
5-H
Remark
[
]: PD78F0058Y only.
18
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
Table 4-1. Input/Output Circuit Type of Each Pin (2/2)
Pin Name P70/SI2/RxD0 P71/SO2/TxD0 P72/SCK2/ASCK P120/RTP0 to P127/RTP7 P130/ANO0, P131/ANO1 RESET XT2 AVREF0 AVREF1 AVSS VPP 2 16 - Input - Leave open. Connect to VSS0. Connect to VDD0. Connect to VSS0. Connect directly to VSS0 or VSS1. 12-C Input : Independently connect to VSS0 via a resistor. Output : Leave open. - Input/Output Circuit Type 8-C 5-H 8-C 5-H I/O Recommended Connection
I/O
Input
: Independently connect to VDD0 or VSS0 via a resistor.
Output : Leave open.
Data Sheet U12092EJ1V0DS00
19
PD78F0058, 78F0058Y
Figure 4-1. Pin Input/Output Circuits (1/2)
Type 2
Type 8-C VDD0
Pullup enable IN Data VDD0 P-ch
P-ch
IN/OUT Schmitt-triggered input with hysteresis characteristic Output disable N-ch VSS0
Type 5-H Pullup enable VDD0 Data
VDD0
Type 10-B
VDD0
P-ch
Pullup enable VDD0 Data IN/OUT P-ch
P-ch
P-ch
IN/OUT Open drain Output disable VSS0 N-ch
Output disable
N-ch VSS0
Input enable Type 5-N VDD0 Type 11-D Pullup enable Data VDD0 P-ch VDD0 P-ch IN/OUT IN/OUT Output disable N-ch VSS0 Output disable Comparator N-ch P-ch + - VSS0
Pullup enable VDD0 Data P-ch
P-ch
N-ch VSS0 VREF (Threshold voltage)
Input enable
20
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
Figure 4-1. Pin Input/Output Circuits (2/2)
VDD0
Type 12-C Pullup enable VDD0 Data
Type 16 Feedback cut-off P-ch
P-ch
P-ch IN/OUT
Output disable Input enable
N-ch VSS0 P-ch Analog output voltage N-ch VSS0
XT1
XT2
Type 13-K
IN/OUT Data Output disable VSS0 VDD0 N-ch
RD
P-ch
Middle-voltage input buffer
Data Sheet U12092EJ1V0DS00
21
PD78F0058, 78F0058Y
5. MEMORY SPACE
Figure 5-1 shows the memory map of the PD78F0058 and 78F0058Y. Figure 5-1. Memory Map
FFFFH Special function register (SFR) 256x8 bits FF00H FEFFH FEE0H FEDFH Internal high-speed RAM 1024x8 bits FB00H FAFFH Data memory space FAE0H FADFH Use prohibited 1000H 0FFFH CALLF entry area Use prohibited F800H F7FFH Internal expansion RAM 1024x8 bits F400H F3FFH Use prohibited Note F000H EFFFH Program memory space 0000H Flash memory 61440x8 bits 0040H 003FH Vector table area 0000H CALLT table area 0080H 007FH 0800H 07FFH Program area EFFFH Program area
General registers 32x8 bits
Internal buffer RAM 32x8 bits FAC0H FABFH
Note The area between F000H and F3FFH cannot be used when the flash memory size is 60 Kbytes. This area can be used by setting the flash memory size to 56 Kbytes or less with the memory size switching register (IMS).
22
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
6. FLASH MEMORY PROGRAMMING
The program memory provided in the PD78F0058 and 78F0058Y is flash memory. Writing to a flash memory can be performed without removing the memory from the target system (on-board). Writing is performed connecting the dedicated flash programmer (Flashpro III (part number : FL-PR3, PG-FP3) to the host machine and the target system. Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd.
6.1 Selection of Transmission Mode
Writing to a flash memory is performed using the Flashpro III with a serial transmission mode. One of the transmission mode is selected from those in Table 6-1. The selection of the transmission mode is made by using the format shown in Figure 6-1. Each transmission mode is selected by the number of V PP pulses shown in Table 6-1. Table 6-1. List of Transmission Mode
Transmission Mode 3-wire serial I/O Channels 3 P27/SCK0 [/SCL] P26/SO0/SB1 [/SDA1] P25/SI0/SB0 [/SDA0] P22/SCK1 P21/SO1 P20/SI1 P72/SCK2/ASCK P71/SO2/TxD0 P70/SI1/RxD0 UART 2 P71/SO2/TxD0 P70/SI2/RxD0 P23/TxD1 P24/RxD1 Pseudo 3-wire serial I/ONote 1 P32/TO2 (serial clock input/output) P31/TO1 (serial data output) P30/TO0 (serial data input) 12 9 8 2 1 Pin VPP Pulses 0
Note Serial transmission is performed by controlling the port using software. Caution Select a communication mode always using the number of VPP pulses shown in Table 6-1. Remark [ ] : PD78F0058Y only.
Data Sheet U12092EJ1V0DS00
23
PD78F0058, 78F0058Y
Figure 6-1. Format of Transmission Mode Selection
10 V VPP VDD VSS VDD RESET VSS
1
2
n
6.2 Function of Flash Memory Programming
Operations such as writing to a flash memory are performed by various command/data transmission and reception operations according to the selected transmission mode. Table 6-2 shows major functions of flash memory programming. Table 6-2. Major Functions of Flash Memory Programming
Functions Batch delete Batch blank check Data write Deletes the entire memory contents. Checks the deletion status of the entire memory. Performs write to the flash memory based on the write start address and the number of data to be written (number of bytes). Compares the entire memory contents with the input data. Descriptions
Batch verify
6.3 Connection of Flashpro III
The connection of the Flashpro III and the PD78F0058 and 78F0058Y differs according to the transmission mode (3-wire serial I/O, UART, pseudo 3-wire). The connection for each transmission mode is shown in Figures 6-2 to 6-4. Figure 6-2. Connection of Flashpro III for 3-wire Serial I/O Mode
Flashpro III VPPnNote VDD RESET CLK SCK SO SI GND
PD78F0058, 78F0058Y
VPP VDD0, VDD1 RESET X1 SCK0, SCK1, SCK2 SI0, SI1, SI2 SO0, SO1, SO2 VSS0, VSS1
Note n = 1, 2
24
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
Figure 6-3. Connection of Flashpro III for UART Mode
PD78F0058, 78F0058Y
VPP VDD0, VDD1 RESET X1 RxD0, RxD1 TxD0, TxD1 VSS0, VSS1
Flashpro III VPPnNote VDD RESET CLK SO SI GND Note n = 1, 2
Figure 6-4. Connection of Flashpro III for Pseudo 3-wire Serial I/O Mode
Flashpro III VPPnNote VDD RESET CLK SCK SO SI GND
PD78F0058, 78F0058Y
VPP VDD0, VDD1 RESET X1 P32 (serial clock) P30 (serial input) P31(serial output) VSS0, VSS1
Note n = 1, 2
Data Sheet U12092EJ1V0DS00
25
PD78F0058, 78F0058Y
6.4 Example of Settings for Flashpro III (PG-FP3)
Make the following setting when writing to flash memory using Flashpro III (PG-FP3) <1> Load the parameter file. <2> Select serial mode and serial clock using the type command. <3> An example of the settings for the PG-FP3 is shown below. Table 6-3. Example of Settings for PG-FP3
Communication Mode 3-wire serial I/O COMM PORT CPU CLK Example of Setting for PG-FP3 SIO-ch0/1/2 On Target Board In Flashpro On Target Board SIO CLK In Flashpro SIO CLK UART COMM PORT CPU CLK On Target Board UART BPS Pseudo 3-wire COMM PORT CPU CLK 4.1943 MHz 1.0 MHz 4.0 MHz 1.0 MHz UART-ch0/1 On Target Board 4.1943 MHz 9600 bpsNote 2 PortA On Target Board In Flashpro On Target Board SIO CLK In Flashpro SIO CLK 4.1943 MHz 1.0 kHz 4.0 MHz 1.0 kHz 12 8/9 Number of VPP PulsesNote 1 0/1/2
Notes 1. The number of VPP pulses supplied from Flashpro III when serial communication is initialized. The pins to be used for communication are determined according to the number of these pulses. 2. Select one of 9600 bps, 19200 bps, 38400 bps, or 768000 bps. Remark COMM PORT : Selection of serial port SIO CLK : Selection of serial clock frequency CPU CLK : Selection of source of CPU clock to be input
26
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
7. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD VPP AVREF0 AVREF1 AVSS Input voltage VI1 P00-P05, P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P64-P67, P70-P72, P120-P127, P130, P131, X1, X2, XT2, RESET P60-P63 N-ch open drain Conditions Ratings -0.3 to +6.5 -0.3 to +10.5 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 Unit V V V V V V
VI2 Output voltage VO
-0.3 to +16 -0.3 to VDD + 0.3
V V V mA mA
Analog input voltage VAN Output current, high IOH
P10-P17 Per pin
Analog input pin
AVSS - 0.3 to AVREF0 + 0.3 -10 -15
Total for P01-P05, P30-P37, P56, P57, P60-P67, P120-P127 Total for P10-P17, P20-P27, P40-P47, P50-P55, P70-P72, P130, P131 IOLNote
-15
mA
Output current, low
Per pin
Peak value rms value
30 15 100 70 100 70 50 20 50 20 -40 to +85 10 to 40 -65 to +125
mA mA mA mA mA mA mA mA mA mA C C C
Total for P50-P55
Peak value rms value
Total for P56, P57, P60-P63
Peak value rms value
Total for P10-P17, P20-P27, P40-P47, P70-P72, P130, P131 Total for P01-P05, P30-P37, P64-P67, P120-P127 Operating ambient temperature Storage temperature Tstg TA During normal operation During flash memory programming
Peak value rms value Peak value rms value
Note
The rms value should be calculated as follows: [rms value] = [Peak value] x Duty Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Caution
Data Sheet U12092EJ1V0DS00
27
PD78F0058, 78F0058Y
Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Resonator Ceramic resonator Recommended Circuit Parameter Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2 Conditions VDD = Oscillation voltage range After VDD reaches oscillation voltage range MIN. 1.0 VDD = 4.5 to 5.5 V MIN. 1.0 TYP. MAX. 5.0 4 Unit MHz ms
X2
X1 VPP
C2
C1
Crystal resonator
X2
X1 VPP
Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2
5.0 10 30
MHz ms
C2
C1
External clock
X2
X1
X1 input frequency (fX)Note 1 X1 input high-/low-level width (tXH , tXL)
1.0 85
5.0 500
MHz ns
PD74HCU04
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
28
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Resonator Crystal resonator Recommended Circuit Parameter Oscillation frequency (fXT)Note 1 Oscillation stabilization timeNote 2 VDD = 4.5 to 5.5 V Conditions MIN. 32 TYP. 32.768 1.2 MAX. 35 2 10 Unit kHz s
VPP XT2 R2 C4
XT1
C3
External clock
XT2
XT1
XT1 input frequency (fXT)Note 1 XT1 input high-/low-level width (tXTH , tXTL)
32
100
kHz
5
15
s
PD74HCU04
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance I/O capacitance Symbol CIN CIO Conditions f = 1 MHz Unmeasured pins returned to 0 V. f = 1 MHz Unmeasured pins returned to 0 V. P01-P05, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P64-P67, P70-P72, P120-P127, P130, P131 P60-P63 MIN. TYP. MAX. 15 15 Unit pF pF
20
pF
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U12092EJ1V0DS00
29
PD78F0058, 78F0058Y
DC Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Parameter Input voltage, high Symbol VIH1 Conditions P10-P17, P21, P23, P30-P32, P35-P37, P40-P47, P50-P57, P64-P67, P71, P120-P127, P130, P131 P00-P05, P20, P22, P24-P27, P33, P34, P70, P72, RESET VIH3 P60-P63 (N-ch open drain) VIH4 VIH5 X1, X2 XT1/P07, XT2 VDD = 2.7 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V Input voltage, low VIL1 P10-P17, P21, P23, P30-P32, P35-P37, P40-P47, P50-P57, P64-P67, P71, P120-P127, P130, P131 P00-P05, P20, P22, P24-P27, P33, P34, P70, P72, RESET VIL3 P60-P63 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V VIL4 VIL5 X1, X2 XT1/P07, XT2 VDD = 2.7 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V Output voltage, high Output voltage, low VOL1 VOH VDD = 4.5 to 5.5 V, IOH = -1 mA IOH = -100 A P50-P57, P60-P63 P01-P05, P10-P17, P20-P27, P30-P37, P40-P47, P64-P67, P70-P72, P120-P127, P130, P131 VOL2 SB0, SB1, SCK0 VDD = 4.5 to 5.5 V, IOL = 15 mA VDD = 4.5 to 5.5 V, IOL = 1.6 mA VDD = 4.5 to 5.5 V, open drain, pulled-up (R = 1 k) VOL3 IOL = 400 A 0.5 V 0 0 0 0 0 VDD - 1.0 VDD - 0.5 0.4 2.0 0.4 0.3VDD 0.2VDD 0.4 0.2VDD 0.1VDD V V V V V V V V V VDD = 2.7 to 5.5 V VDD - 0.5 0.8VDD 0.9VDD 0 VDD VDD VDD 0.3VDD V V V V VDD = 2.7 to 5.5 V 0.7VDD 15 V VDD = 2.7 to 5.5 V MIN. 0.7VDD TYP. MAX. VDD Unit V
VIH2
VDD = 2.7 to 5.5 V
0.8VDD
VDD
V
VIL2
VDD = 2.7 to 5.5 V
0
0.2VDD
V
0.2VDD
V
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
30
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
DC Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Parameter Input leakage current, high Symbol ILIH1 VIN = VDD Conditions P00-P05, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P72, P120-P127, P130, P131, RESET X1, X2, XT1/P07, XT2 VIN = 15 V VIN = 0 V P60 to P63 P00-P05, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P64-P67, P70-P72, P120-P127, P130, P131, RESET X1, X2, XT1/P07, XT2 P60-P63 VOUT = VDD VOUT = 0 V VIN = 0 V, P01-P05, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P64-P67, P70-P72, P120-P127, P130, P131 15 30 MIN. TYP. MAX. 3 Unit
A
ILIH2 ILIH3 Input leakage current, low ILIL1
20 80 -3
A A A
ILIL2 ILIL3 Output leakage current, high Output leakage current, low Software pull-up resistorNote 2 ILOH ILOL R
-20 -3 Note 1 3 -3 90
A A A A
k
Notes 1. A low-level input leakage current of -200 A (MAX.) flows only for 1.5 clocks (without wait) after a read instruction has been executed to port 6 (P6) or port mode register 6 (PM6). At times other than this 1.5clock interval, a -3 A (MAX.) current flows. 2. Software pull-up resistor can only be used within the range VDD = 2.7 to 5.5 V. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U12092EJ1V0DS00
31
PD78F0058, 78F0058Y
DC Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Parameter Power supply currentNote 5 Symbol IDD1Note 5 5.0 MHz crystal oscillation operating mode (fXX = 2.5 MHz)Note 3 5.0 MHz crystal oscillation operating mode (fXX = 5.0 MHz)Note 4 5.0 MHz crystal oscillation HALT mode (fXX = 2.5 MHz)Note 3 Conditions VDD = 5.0 V 10%Note 1 VDD = 3.0 V 10%Note 2 VDD = 5.0 V 10%Note 1 VDD = 3.0 V 10%Note 2 VDD = 5.0 V 10% Peripheral functions operating Peripheral functions not operating VDD = 3.0 V 10% Peripheral functions operating Peripheral functions not operating 5.0 MHz crystal oscillation HALT mode (fXX = 5.0 MHz)Note 4 VDD = 5.0 V 10% Peripheral functions operating Peripheral functions not operating VDD = 3.0 V 10% Peripheral functions operating Peripheral functions not operating IDD3Note 5 32.768 kHz crystal oscillation operating modeNote 6 IDD4Note 5 32.768 kHz crystal oscillation HALT modeNote 6 IDD5Note 5 XT1 = VDD STOP mode When feedback resistor is used VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% 110 86 22.5 3.2 1.0 0.5 0.1 0.05 220 172 45 6.4 30 10 30 10 0.6 4.5 1.5 mA mA 1.3 8.4 3.1 mA mA 0.44 1.1 mA 2.9 mA 1.0 5.6 2.8 mA mA MIN. TYP. 6.2 1.3 13.1 2.1 MAX. 12.5 3.1 25.7 4.9 Unit mA mA mA mA
IDD2
A A A A A A A A
IDD6Note 5 XT1 = VDD STOP mode When feedback resistor is not used
Notes 1. High-speed mode operation (when the processor clock control register (PCC) is set to 00H). 2. Low-speed mode operation (when PCC is set to 04H). 3. Operation with main system clock fXX = fX/2 (when the oscillation mode select register (OSMS) is set to 00H) 4. Operation with main system clock fXX = fX (when OSMS is set to 01H) 5. Refers to the current flowing to the VDD0 and VDD1 pins. The current flowing to the A/D converter, D/A converter, and on-chip pull-up resistor is not included. 6. When the main system clock operation is stopped.
32
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Parameter Cycle time (Min. instruction execution time) Symbol TCY Conditions Operating with main system clock (fXX = 2.5 MHz)Note 1 3.5 V VDD 5.5 V 2.7 V VDD < 3.5 V 0.4 0.8 40Note 3 2/fsam + 2/fsam + 0.1Note 4 0.2Note 4 122 32 32 125 VDD = 2.7 to 5.5 V MIN. 0.8 TYP. MAX. 64 Unit
s s s s s s s
Operating with main system clock (fXX = 5.0 MHz)Note 2
Operating with subsystem clock TI00 input high-/ low-level width TI01 input high-/ low-level width TI1, TI2 input frequency TI1, TI2 input high-/low-level width Interrupt request input high-/ low-level width RESET lowlevel width tRSL tINTH tINTL INTP1-INTP5, P40-P47 VDD = 2.7 to 5.5 V INTP0 tTIH1 tTIL1 VDD = 4.5 to 5.5 V tTIH00 tTIL00 tTIH01 tTIL01 fTI1 VDD = 4.5 to 5.5 V 3.5 V VDD 5.5 V 2.7 V VDD < 3.5 V VDD = 2.7 to 5.5 V
10
0 0 100 1.8 3.5 V VDD 5.5 V 2/fsam + 0.1Note 4 2.7 V VDD < 3.5 V 2/fsam + VDD = 2.7 to 5.5 V 0.2Note 4
4 275
MHz kHz ns
s s s s s
10 10
Notes 1. Operation with main system clock fXX = fX/2 (when the oscillation mode select register (OSMS) is set to 00H) 2. Operation with main system clock fXX = fX (when OSMS is set to 01H) 3. Value when external clock is used. When a crystal resonator is used, it is 114 s (MIN.) 4. Selection of fsam = fXX/2N, fXX/32, fXX/64, and fXX/128 is possible with bits 0 and 1 (SCS0, SCS1) of the sampling clock select register (SCS) (when N= 0 to 4).
Data Sheet U12092EJ1V0DS00
33
PD78F0058, 78F0058Y
TCY vs. VDD (@fXX = fX/2 main system clock operation) TCY vs. VDD (@fXX = fX main system clock operation)
60
60
10
Cycle time TCY [s] Cycle time TCY [s]
10 Guaranteed operation range Guaranteed operation range 2.0 1.0 0.5 0.4
2.0 1.0 0.5 0.4
0 1 2 3 4 5 6 Supply voltage VDD [V]
0 1 2 3 4 5 6 Supply voltage VDD [V]
34
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
(2) Read/write operation (a) When MCS = 1, PCC2 to PCC0 = 000B (TA = -40 to +85C, VDD = 3.5 to 5.5 V)
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from RD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 WAIT input time from RD tRDWT1 tRDWT2 WAIT input time from WR WAIT low-level width Write data setup time Write data hold time WR low-level width RD delay time from ASTB WR delay time from ASTB ASTB delay time from RD at external fetch Address hold time from RD at external fetch Write data output time from RD Write data output time from WR Address hold time from WR RD delay time from WAIT WR delay time from WAIT tRDWD tWRWD tWRADH tWTRD tWTWR 40 0 0.85tCY 1.15tCY + 40 1.15tCY + 30 50 1.15tCY + 40 3.15tCY + 40 3.15tCY + 30 ns ns ns ns ns tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST (1.15 + 2n)tCY (2.85 + 2n)tCY - 100 20 (2.85 + 2n)tCY - 60 25 0.85tCY + 20 0.85tCY - 10 1.15tCY + 20 0 (2 + 2n)tCY - 60 (2.85 + 2n)tCY - 60 0.85tCY - 50 2tCY - 60 2tCY - 60 (2 + 2n)tCY Conditions MIN. 0.85tCY - 50 0.85tCY - 50 50 (2.85 + 2n)tCY - 80 (4 + 2n)tCY - 100 (2 + 2n)tCY - 100 (2.85 + 2n)tCY - 100 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRDADH
0.85tCY - 50
1.15tCY + 50
ns
Remarks
1. 2. 3. 4.
MCS: Bit 0 of the oscillation mode select register (OSMS) PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC) tCY = TCY/4 n indicates the number of waits.
Data Sheet U12092EJ1V0DS00
35
PD78F0058, 78F0058Y
(b) When MCS = 0 or PCC2 to PCC0 000B (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from RD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 WAIT input time from RD tRDWT1 tRDWT2 WAIT input time from WR WAIT low-level width Write data setup time Write data hold time WR low-level width RD delay time from ASTB WR delay time from ASTB ASTB delay time from RD at external fetch Address hold time from RD at external fetch Write data output time from RD Write data output time from WR Address hold time from WR RD delay time from WAIT WR delay time from WAIT tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST tRDADH tRDWD tWRWD tWRADH tWTRD tWTWR (1 + 2n)tCY (2.4 + 2n)tCY - 60 20 (2.4 + 2n)tCY - 20 0.4tCY - 30 1.4tCY - 30 tCY - 10 tCY - 50 0.4tCY - 20 0 tCY 0.6tCY + 180 0.6tCY + 120 60 tCY + 60 2.6tCY + 180 2.6tCY + 120 tCY + 20 tCY + 50 0 (1.4 + 2n)tCY - 20 (2.4 + 2n)tCY - 20 tCY - 100 2tCY - 100 2tCY - 100 (2 + 2n)tCY Conditions MIN. tCY - 80 tCY - 80 0.4tCY - 10 (3 + 2n)tCY - 160 (4 + 2n)tCY - 200 (1.4 + 2n)tCY - 70 (2.4 + 2n)tCY - 70 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks
1. 2. 3. 4.
MCS: Bit 0 of the oscillation mode select register (OSMS) PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC) tCY = TCY/4 n indicates the number of waits.
36
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
(3) Serial interface (TA = -40 to +85C, VDD = 2.7 to 5.5 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0... Internal clock output)
Parameter SCK0 cycle time Symbol tKCY1 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK0 high-/low-level width SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0 tSIK1 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V tKSI1 tKH1, tKL1 VDD = 4.5 to 5.5 V MIN. 800 1,600 tKCY1/2 - 50 tKCY1/2 - 100 100 150 400 TYP. MAX. Unit ns ns ns ns ns ns ns
tKSO1
C = 100 pFNote
300
ns
Note C is the load capacitance of the SCK0 and SO0 output lines. (ii) 3-wire serial I/O mode (SCK0... External clock input)
Parameter SCK0 cycle time Symbol tKCY2 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK0 high-/low-level width SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0 SCK0 rise/fall time tKH2, tKL2 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V tSIK2 2.7 V VDD 5.5 V MIN. 800 1,600 400 800 100 TYP. MAX. Unit ns ns ns ns ns
tKSI2 C = 100 pFNote
400
ns
tKSO2
300
ns
tR2, tF2
When using external device expansion function When not using external device expansion function
160 1,000
ns ns
Note C is the load capacitance of the SO0 output line.
Data Sheet U12092EJ1V0DS00
37
PD78F0058, 78F0058Y
(iii) 2-wire serial I/O mode (SCK0... Internal clock output)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width Symbol tKCY3 tKH3 tKL3 R = 1 k, C = 100 pFNote Conditions 2.7 V VDD 5.5 V VDD = 2.7 to 5.5 V VDD = 4.5 to 5.5 V MIN. 1,600 tKCY3/2 - 160 tKCY3/2 - 50 tKCY3/2 - 100 SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 tSIK3 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V tKSI3 tKSO3 300 350 600 0 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines. (iv) 2-wire serial I/O mode (SCK0... External clock input)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SCK0 rise/fall time Symbol tKCY4 tKH4 tKL4 tSIK4 tKSI4 R = 1 k, C = 100 tR4, tF4 pFNote 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V Conditions 2.7 V VDD 5.5 V 2.7 V VDD 5.5 V 2.7 V VDD 5.5 V VDD = 2.7 to 5.5 V MIN. 1,600 650 800 100 tKCY4/2 TYP. MAX. Unit ns ns ns ns ns
tKSO4
0 0
300 500 160
ns ns ns
When using external device expansion function When not using external device expansion function
1,000
ns
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
38
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
(v) SBI mode (SCK0... Internal clock output) (PD78F0058 only)
Parameter SCK0 cycle time Symbol tKCY5 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK0 high-/low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 tKH5, tKL5 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V tSIK5 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V tKSI5 tKSO5 R = 1 k, C = 100 pFNote VDD = 4.5 to 5.5 V MIN. 800 3,200 tKCY5/2 - 50 tKCY5/2 - 150 100 300 tKCY5/2 0 0 tKCY5 tKCY5 tKCY5 tKCY5 250 1,000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tKSB tSBK
SB0, SB1 high-level width tSBH SB0, SB1 low-level width tSBL
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines. (vi) SBI mode (SCK0... External clock input) (PD78F0058 only)
Parameter SCK0 cycle time Symbol tKCY6 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK0 high-/low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 tKH6, tKL6 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V tSIK6 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V tKSI6 tKSO6 R = 1 k, C = 100 pFNote VDD = 4.5 to 5.5 V MIN. 800 3,200 400 1,600 100 300 tKCY6/2 0 0 tKCY6 tKCY6 tKCY6 tKCY6 When using external device expansion function When not using external device expansion function 160 1,000 300 1,000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SB0, SB1 from SCK0 tKSB SCK0 from SB0, SB1 tSBK SB0, SB1 high-level width tSBH SB0, SB1 low-level width SCK0 rise/fall time tSBL tR6, tF6
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
Data Sheet U12092EJ1V0DS00
39
PD78F0058, 78F0058Y
(vii) I2C bus mode (SCL... Internal clock output) (PD78F0058Y only)
Parameter SCL cycle time SCL high-level width SCL low-level width Symbol tKCY7 tKH7 tKL7 R = 1 k, Conditions 2.7 V VDD < 5.5 V 4.5 V VDD < 5.5 V 2.7 V VDD < 4.5 V SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay tKSO7 time from SCL SDA0, SDA1 from SCL tKSB or SDA0, SDA1 from SCL SCL from SDA0, SDA1 tSBK SDA0, SDA1 high-level width tSBH 4.5 V VDD < 5.5 V 0 0 200 400 500 300 500 ns ns ns ns ns tSIK7 2.7 V VDD < 5.5 V C = 100 pFNote 2.7 V VDD < 5.5 V MIN. 10 tKCY7 - 160 tKCY7 - 50 tKCY7 - 100 200 TYP. MAX. Unit
s s
ns ns ns
tKSI7
0
ns
Note
R and C are the load resistance and load capacitance of the SCL, SDA0, and SDA1 output lines. (viii) I2C bus mode (SCL... External clock input) (PD78F0058Y only)
Parameter Symbol tKCY8 tKH8 tSIK8 Conditions MIN. 1 400 200 TYP. MAX. Unit
SCL cycle time SCL high-level width SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL)
s
ns ns
tKSI8
0
ns
SDA0, SDA1 output delay tKSO8 time from SCL SDA0, SDA1 from SCL tKSB or SDA0, SDA1 from SCL SCL from SDA0, SDA1 tSBK SDA0, SDA1 high-level width tSBH
R = 1 k, C = 100 pFNote
4.5 V VDD < 5.5 V
0 0 200
300 500
ns ns ns
400 500
ns ns
Note
R and C are the load resistance and load capacitance of the SDA0 and SDA1 output lines.
40
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
(b) Serial interface channel 1 (i) 3-wire serial I/O mode (SCK1...Internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK1 high-/low-level width tKH9, tKL9 VDD = 4.5 to 5.5 V MIN. 800 1,600 tKCY9/2 - 50 tKCY9/2 - 100 SI1 setup time (to SCK1) tSIK9 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SI1 hold time (from SCK1) tKSI9 C = 100 pFNote 100 150 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SO1 output delay time from SCK1 tKSO9
Note C is the load capacitance of the SCK1 and SO1 output lines.
(ii) 3-wire serial I/O mode (SCK1...External clock input)
Parameter SCK1 cycle time Symbol tKCY10 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK1 high-/low-level width tKH10, tKL10 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SI1 setup time (to SCK1) SI1 hold time (from SCK1) tSIK10 tKIS10 C = 100 pFNote VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V MIN. 800 1,600 400 800 100 400 300 160 1,000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
SO1 output delay time from SCK1 tKSO10 SCK1 rise/fall time tR10, tF10
When using external device expansion function When not using external device expansion function
Note C is the load capacitance of the SO1 output line.
Data Sheet U12092EJ1V0DS00
41
PD78F0058, 78F0058Y
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1...Internal clock output)
Parameter SCK1 cycle time Symbol tKCY11 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK1 high-/low-level width tKH11, tKL11 VDD = 4.5 to 5.5 V MIN. 800 1,600 tKCY11/2 - 50 tKCY11/2 - 100 SI1 setup time (to SCK1) tSIK11 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SI1 hold time (from SCK1) tKSI11 C = 100 pFNote tKCY11/2 - 100 2.7 V VDD < 5.5 V tKCY11 - 30 100 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V tSPS 100 150 2tKCY11 100 150 400 300 tKCY11/2 + 100 tKCY11 + 30 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SO1 output delay time from SCK1 tKSO11 STB from SCK1 Strobe signal high-level width Busy signal setup time (to busy signal detection timing) Busy signal hold time (from busy signal detection timing) SCK1 from busy inactive tSBD tSBW tBYS tBYH
Note C is the load capacitance of the SCK1 and SO1 output lines. (iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1...External clock input)
Parameter SCK1 cycle time Symbol tKCY12 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK1 high-/low-level width tKH12, tKL12 tSIK12 tKSI12 C = 100 pFNote VDD = 2.7 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V VDD = 2.7 to 5.5 V MIN. 800 1,600 400 800 100 400 300 160 1,000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
SI1 setup time (to SCK1) SI1 hold time (from SCK1)
SO1 output delay time from SCK1 tKSO12 SCK1 rise/fall time tR12, tF12
When using external device expansion function When not using external device expansion function
Note C is the load capacitance of the SO1 output line.
42
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
(c) Serial interface channel 2 (i) 3-wire serial I/O mode (SCK2...Internal clock output)
Parameter SCK2 cycle time Symbol tKCY13 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK2 high-/low-level width tKH13, tKL13 tSIK13 VDD = 4.5 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SI2 hold time (from SCK2) tKSI13 C = 100 pFNote MIN. 800 1,600 tKCY13/2 - 50 tKCY13/2 - 100 100 150 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SI2 setup time (to SCK2)
SO2 output delay time from SCK2 tKSO13
Note C is the load capacitance of the SO2 output line. (ii) 3-wire serial I/O mode (SCK2...External clock input)
Parameter SCK2 cycle time Symbol tKCY14 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK2 high-/low-level width tKH14, tKL14 tSIK14 tKSI14 C = 100 pFNote VDD = 2.7 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V VDD = 2.7 to 5.5 V MIN. 800 1,600 400 800 100 400 300 160 1 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SI2 setup time (to SCK2) SI2 hold time (from SCK2)
SO2 output delay time from SCK2 tKSO14 SCK2 rise/fall time tR14, tF14
Other than below VDD = 4.5 to 5.5 V When not using external device expansion function
s
Note C is the load capacitance of the SO2 output line.
Data Sheet U12092EJ1V0DS00
43
PD78F0058, 78F0058Y
(iii) UART mode (Dedicated baud rate generator output)
Parameter Transfer rate Symbol Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V MIN. TYP. MAX. 78,125 39,063 Unit bps bps
(iv) UART mode (External clock input)
Parameter ASCK cycle time Symbol tKCY15 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V ASCK high-/low-level width tKH15, tKL15 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V Transfer rate 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V ASCK rise/fall time tR15, tF15 VDD = 4.5 to 5.5 V, when not using external device expansion function. 160 ns MIN. 800 1,600 400 800 39,063 19,531 1,000 TYP. MAX. Unit ns ns ns ns bps bps ns
44
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
AC Timing Measurement Points (Excluding X1, XT1 Inputs)
0.8VDD 0.2VDD
Point of measurement
0.8VDD 0.2VDD
Clock Timing
1/fX
tXL
tXH VIH4 (MIN.) VIL4 (MAX.)
X1 input
1/fXT
tXTL XT1 input
tXTH VIH5 (MIN.) VIL5 (MAX.)
TI Timing
tTIL00, tTIL01
tTIH00, tTIH01
TI00, TI01
1/fTI1 tTIL1 tTIH1
TI1, TI2
Data Sheet U12092EJ1V0DS00
45
PD78F0058, 78F0058Y
Interrupt Request Input Timing
tINTL INTP0 to INTP5
tINTH
RESET Input Timing
tRSL
RESET
46
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
Read/Write Operation External fetch (no wait):
A8 to A15
Higher 8-bit address tADD1
AD0 to AD7 tADS tASTH ASTB
Lower 8-bit address
Hi-Z
Operation code tRDD1 tRDADH tRDAST
tADH
RD tASTRD tRDL1 tRDH
External fetch (wait insertion):
A8 to A15
Higher 8-bit address
tADD1 AD0 to AD7 tADS tASTH ASTB
Lower 8-bit address
Hi-Z tRDD1
Operation code tRDADH tRDAST
tADH
RD tASTRD tRDL1 tRDH
WAIT tRDWT1 tWTL tWTRD
Data Sheet U12092EJ1V0DS00
47
PD78F0058, 78F0058Y
External data access (no wait):
A8 to A15
Higher 8-bit address
tADD2 AD0 to AD7 tADS tADH tASTH ASTB
Lower 8-bit address
Hi-Z tRDD2
Read data
Hi-Z
Write data
Hi-Z
tRDH
RD tASTRD tRDL2 tRDWD tWRWD WR tASTWR tWRL tWDS tWDH tWRADH
External data access (wait insertion):
A8 to A15
Higher 8-bit address
tADD2 AD0 to AD7 tADS tADH tASTH ASTB
Lower 8-bit address
Hi-Z tRDD2
Read data
Hi-Z
Write data
Hi-Z
tRDH
tASTRD RD tRDL2 tRDWD tWRWD WR tASTWR tWRL tWRADH tWDS tWDH
WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR
48
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
Serial Transfer Timing 3-wire serial I/O mode:
tKCYm tKLm tRn SCK0 to SCK2 tSIKm tKSIm tKHm tFn
SI0 to SI2 tKSOm
Input data
SO0 to SO2
Output data
m = 1, 2, 9, 10, 13, 14 n = 2, 10, 14
2-wire serial I/O mode:
tKCY3, 4
tKL3, 4 tR4 SCK0 tSIK3, 4 tKSO3, 4 SB0, SB1
tKH3, 4 tF4
tKSI3, 4
Data Sheet U12092EJ1V0DS00
49
PD78F0058, 78F0058Y
SBI mode (bus release signal transfer):
tKCY5, 6 tKL5, 6 tR6 SCK0 tKSB tSBL tSBH tSBK tSIK5, 6 tKSI5, 6 tKH5, 6 tF6
SB0, SB1 tKSO5, 6
SBI mode (command signal transfer):
tKCY5,6
tKL5, 6 tR6 SCK0
tKH5, 6
tF6
tSIK5, 6 tKSB tSBK tKSI5, 6
SB0, SB1 tKSO5, 6
I2C bus mode :
tKCYm
SCL tKLm tKHm tKSOm SDA0, SDA1 tSIKm tKSB tSBK tKSB
tKSIm
tSBH m = 7, 8
tSIKm
50
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
3-wire serial I/O mode with automatic transmit/receive function:
SO1
D2
D1
D0
D7
SI1
D2 tSIK11, 12 tKSO11, 12
D1
D0 tKSI11, 12 tKH11, 12 tF12
D7
SCK1
tR12
tKL11, 12 STB tKCY11, 12
tSBD
tSBW
3-wire serial I/O mode with automatic transmit/receive function (busy processing):
SCK1
7
8
9Note
10Note tBYS
10 + nNote tBYH tSPS
1
BUSY (Active high)
Note
The signal is not actually driven low here; it is shown as such to indicate the timing.
UART mode (external clock input):
tKCY15 t KL15 tR15 tKH15 tF15
ASCK
Data Sheet U12092EJ1V0DS00
51
PD78F0058, 78F0058Y
A/D Converter Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall errorNote 1 2.7 V AVREF0 < 4.5 V 4.5 V AVREF0 < 5.5 V Conversion time Analog input voltage Reference voltage AVREF0 current TCONV VIAN AVREF0 IREF0 When A/D converter is operatingNote 2 2.7 V AVREF0 < 5.5 V 16 AVSS 2.7 500 0 Symbol Conditions MIN. 8 TYP. 8 MAX. 8 1.0 0.6 100 AVREF0 VDD 1,500 3 Unit bit % %
s
V V
A A
When A/D converter is not operatingNote 3
Notes 1. Excludes quantization error (1/2 LSB). This value is indicated as a ratio to the full-scale value. 2. The current flowing to the AVREF0 pin when bit 7 (CS) of the A/D converter mode register (ADM) is 1. 3. The current flowing to the AVREF0 pin when bit 7 (CS) of the A/D converter mode register (ADM) is 0. D/A Converter Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall error R = 2 MNote 1 R=4 MNote 1 MNote 1
Note 1
Symbol
Conditions
MIN.
TYP.
MAX. 8 1.2 0.8 0.6 15
Unit bit % % %
R = 10 Settling time Output resistance Analog reference voltage AVREF1 current RO AVREF1 IREF1 Note 2
C = 30 pF Note 2
s
k
8 1.8 VDD 2.5 4 8
V mA k
Resistance between AVREF1 and AVSS RAIREF1
DACS0, DACS1 = 55HNote 2
Notes 1. R and C are the D/A converter output pin load resistance and load capacitance, respectively. 2. Value for one D/A converter channel Remark DACS0 and DACS1: D/A conversion value setting registers 0, 1
52
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention power supply voltage Data retention power supply current Symbol VDDDR Conditions MIN. 1.8 TYP. MAX. 5.5 Unit V
IDDDR
VDDDR = 1.8 V Subsystem clock stop and feed-back resistor disconnected 0 Release by RESET Release by interrupt request
0.1
10
A
Release signal set time Oscillation stabilization wait time
tSREL tWAIT
s
2 /fX Note
17
ms ms
Note
Selection of 212/fXX and 214/fXX to 217/fXX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). fXX: Main system clock frequency (fX or fX/2) fX: Main system clock oscillation frequency
Remark
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation HALT mode STOP mode Operating mode
Data retention mode
VDD STOP instruction execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode STOP mode Operating mode
Data retention mode
VDD STOP instruction execution Standby release signal (Interrupt request)
VDDDR tSREL
tWAIT
Data Sheet U12092EJ1V0DS00
53
PD78F0058, 78F0058Y
Flash Memory Programming Characteristics (VDD = 2.7 to 5.5 V, TA = 10 to 40C) (1) Write/delete characteristics
Parameter Write current (VDD pin)Note 1 Symbol tDDW When VPP = VPP1 Conditions 5.0 MHz crystal oscillation operation mode (fXX = 2.5 MHz)Note 2 5.0 MHz crystal oscillation operation mode (fXX = 5.0 MHz)Note 3 Write current (VPP pin)Note 1 IPPW When VPP = VPP1 5.0 MHz crystal oscillation operation mode (fXX = 2.5 MHz)Note 2 5.0 MHz crystal oscillation operation mode (fXX = 5.0 MHz)Note 3 Delete current (VDD pin)Note 1 IDDE When VPP = VPP1 5.0 MHz crystal oscillation operation mode (fXX = 2.5 MHz)Note 2 5.0 MHz crystal oscillation operation mode (fXX = 5.0 MHz)Note 3 Delete current (VPP pin)Note 1 Unit delete time Total delete time Number of overwrite VPP power supply voltage IPPE tER tERA CWRT VPP0 VPP1 Delete and write are counted as one cycle In normal mode At flash memory programming 0 9.7 10.0 When VPP = VPP1 0.5 1 MIN. TYP. MAX. 15.5 Unit mA
28.7
mA
19.5
mA
32.7
mA
15.5
mA
28.7
mA
100 1 20 20 0.2 VDD 10.3
mA s s times V V
Notes 1.
1. AVREF current and Port current (current flowing to internal pull-up resistor) are not included. 2. When main system clock is operating at fXX = fXX/2 (when oscillation mode selection resistor (OSMS) is set to 00H). 3. When main system clock is operating at fXX = fXX (when OSMS is set to 01H).
2) Serial write operation characteristics
Parameter VPP setup time VPP setup time from VDD RESET setup time from VPP VPP count start time from RESET Count execution time VPP counter high-level width VPP counter low-level width VPP counter noise elimination width Symbol tPSRON tDRPSR tPSRRF tRFCF tCOUNT tCH tCL tNFW 8.0 8.0 40 VPP high voltage VPP high voltage VPP high voltage Conditions MIN. 1.0 1.0 1.0 1.0 2.0 TYP. MAX. Unit
s s s s
ms
s s
ns
54
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
Flash Write Mode Setting Timing
VDD VDD 0V VPPH VPP VPP VPPL tPSRON tPSRRF tCOUNT VDD RESET (input) 0V tCL tDRPSR tRFCF tCH
Data Sheet U12092EJ1V0DS00
55
PD78F0058, 78F0058Y
8. PACKAGE DRAWINGS
80-PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end S C D R Q
80 1
21 20
F J G P H I
M
K S N S L M
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.200.20 14.000.20 14.000.20 17.200.20 0.825 0.825 0.320.06 0.13 0.65 (T.P.) 1.600.20 0.800.20 0.17 +0.03 -0.07 0.10 1.400.10 0.1250.075 3 +7 -3 1.70 MAX. P80GC-65-8BT-1
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
56
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
80 PIN PLASTIC TQFP (FINE PITCH) (12x12)
A B
60 61
41 40
detail of lead end S C D Q R
80 1 20
21
F G P H I
M
J K M
N
NOTE
S
L
S
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 14.000.20 12.000.20 12.000.20 14.000.20 1.25 1.25 0.22 +0.05 -0.04 0.10 0.50 (T.P.) 1.000.20 0.500.20 0.145 +0.055 -0.045 0.10 1.050.07 0.100.05 55 1.27 MAX. P80GK-50-BE9-6
Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
Data Sheet U12092EJ1V0DS00
57
PD78F0058, 78F0058Y
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
A B
60 61
41 40
detail of lead end S C D P T
80 1 F G H I
M
21 20 Q J
R
L U
K S N
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
S
M
ITEM A B C D F G H I J K L M N P Q R S T U
MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.5 0.1450.05 0.08 1.0 0.10.05 3 +4 -3 1.10.1 0.25 0.60.15 P80GK-50-9EU-1
58
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
9. RECOMMENDED SOLDERING CONDITIONS
The PD78F0058 and 78F0058Y should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 9-1. Surface Mounting Type Soldering Conditions
PD78F0058GC-8BT
: 80-pin plastic QFP (14 x 14 mm)
PD78F0058YGC-8BT : 80-pin plastic QFP (14 x 14 mm)
Soldering Method Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature) Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin row) - WS60-00-1 VP15-00-2 Soldering Conditions Recommended Condition Symbol IR35-00-2
Caution
Do not use different soldering methods together (except for partial heating). 80-pin plastic TQFP (12 x 12 mm, resin thickness 1.05 mm) 80-pin plastic TQFP (12 x 12 mm, resin thickness 1.05 mm)
Soldering Conditions Recommended Condition Symbol Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less, Exposure limit: 7 daysNote (after 7 days, prebake at 125C for 10 hours) IR35-107-2
PD78F0058GK-BE9: PD78F0058YGK-BE9:
Soldering Method Infrared reflow
VPS
Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less, Exposure limit: 7 daysNote (after 7 days, prebake at 125C for 10 hours)
VP15-107-2
Wave soldering Partial heating
- Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
- -
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U12092EJ1V0DS00
59
PD78F0058, 78F0058Y
PD78F0058GK-9EU : 80-pin plastic TQFP (12 x 12 mm, resin thickness 1.0 mm) PD78F0058YGK-9EU : 80-pin plastic TQFP (12 x 12 mm, resin thickness 1.0 mm)
Soldering Method Infrared reflow VPS Wave soldering Partial heating Undefined Undefined Undefined Pin temperature: 300C max., Time: 3 seconds max. (per pin row) Soldering Conditions Recommended Condition Symbol Undefined Undefined Undefined -
60
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD780058, 780058Y Subseries. Also, refer to (5) Cautions on using development tools. (1) Language processing software
RA78K0 CC78K0 DF780058 CC78K0-L Assembler package common to the 78K/0 Series C compiler package common to the 78K/0 Series Device file for the PD780058, 780058Y Subseries C compiler library source file common to the 78K/0 Series
(2) Flash memory writing tools
Flashpro III (Part number: FL-PR3, PG-FL3) FA-80GC-8BT FA-80GK FA-80GK-9EU Dedicated flash programmer for microcontrollers incorporating flash memory Adapter for flash memory writing
(3) Debugging tools * When using the IE-78K0-NS in-circuit emulator
IE-78K0-NS IE-70000-MC-PS-B IE-78K0-NS-PA IE-70000-98-IF-C IE-70000-CD-IF-A IE-70000-PC-IF-C IE-70000-PCI-IF IE-780308-NS-EM1 NP-80GC NP-80GK TGK-080SDW EV-9200GC-80 ID78K0-NS SM78K0 DF780058 In-circuit emulator common to the 78K/0 Series Power supply unit for IE-78K0-NS Performance board to enhance and expand the functions of the IE-78K0-NS Adapter used when a PC-9800 series PC (except notebook PC) is used as the host machine (C bus supported) PC card and interface cable used when a PC-9800 series notebook PC is used as the host machine (PCMCIA socket supported) Adapter necessary when an IBM PC/AT TM-compatible is used as the host machine (ISA bus supported) Interface adapter necessary when using a PC with PCI bus as the host machine Emulation board common to the PD780308 Subseries Emulation probe for 80-pin plastic QFP (GC-8BT type) Emulation probe for 80-pin plastic TQFP (GK-BE9, GK-9EU type) Conversion adapter to connect the NP-80GK and a target system board on which 80-pin plastic TQFP (GK-BE9, GK-9EU type) can be mounted Socket to be mounted on a target system board made for 80-pin plastic QFP (GC-8BT type) Integrated debugger for IE-78K0-NS System simulator common to the 78K/0 Series Device file for the PD780058, 780058Y Subseries
Data Sheet U12092EJ1V0DS00
61
PD78F0058, 78F0058Y
* When using the IE-78001-R-A in-circuit emulator
IE-78001-R-A IE-70000-98-IF-C IE-70000-PC-IF-C IE-78000-R-SV3 IE-780308-NS-EM1 IE-780308-R-EM IE-78K0-R-EX1 EP-78230GC-R EP-78054GK-R TGK-080SDW EV-9200GC-80 ID78K0 SM78K0 DF780058 In-circuit emulator common to the 78K/0 Series Adapter used when PC-9800 series PC (except notebook type) is used as host machine (C bus supported) Interface adapter when using IBM PC/AT-compatible as the host machine (ISA bus supported) Interface adapter and cable used when EWS is used as the host machine Emulation board common to the PD780308 Subseries Emulation probe conversion board necessary when using the IE-780308-NS-EM1 on the IE-78001-R-A. Emulation probe for 80-pin plastic QFP (GC-8BT type) Emulation probe for 80-pin plastic TQFP (GK-BE9, GK-9EU type) Conversion adapter to connect the EP-78054GK-R and a target system on which an 80pin plastic TQFP (GK-BE9, GK-9EU type) can be mounted Socket to be mounted on a target system board made for 80-pin plastic QFP (GC-8BT type) Integrated debugger for IE-78001-R-A 78K/0 Series common system simulator Device file for the PD780058, 780058Y Subseries
(4) Real-time OS
RX78K/0 MX78K0 Real-time OS for the 78K/0 Series OS for the 78K/0 Series
62
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
(5) Cautions on using development tools * * * The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780058. The CC78K0 and RX78K/0 are used in combination with the RA78K0 and DF780058. The FL-PR3, FA-80GC-8BT, FA-80GK, FA80GK-9EU, NP-80GC, and NP-80GK are products of Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813). Contact an NEC distributor regarding the purchase of these products. * TGK-080SDW is a product made by Tokyo Eletech Corp. For further information, contact Daimaru Kogyo, Ltd. Electronics Department (Tokyo) (TEL: +81-3-3820-7112) Electronics 2nd Department (Osaka) (TEL: +81-6-6244-6672) * * For third-party development tools, see the Single-Chip Microcontroller Development Tool Selection Guide (U11069E) The host machine and OS suitable for each software are as follows:
Host Machine [OS] PC PC-9800 Series [Japanese Windows TM ] IBM PC/AT-compatible Software RA78K0 CC78K0 ID78K0-NS ID78K0 SM78K0 RX78K/0 MX78K0 [Japanese/English Windows] Note Note Note Note EWS HP9000 series 700 TM [HP-UX TM ] SPARCstation TM [SunOS TM ,Solaris TM ] NEWS TM (RISC) [NEWS-OS TM ] - -
Note DOS-based software
Data Sheet U12092EJ1V0DS00
63
PD78F0058, 78F0058Y
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No. Japanese English U12013E U12182E This document U12326E - - U14458E
PD780058, 780058Y Subseries User's Manual PD780053, 780054, 780055, 780056, 780058 Data Sheet PD78F0058, 78F0058Y Data Sheet
78K/0 Series User's Manual - Instruction 78K/0 Series Instruction Table 78K/0 Series Instruction Set 78K/0, 78K/0S Series Flash Memory Write Application Note
U12013J U12182J U12092J U12326J U10903J U10904J U14458J
Documents Related to Development Tools (User's Manuals)
Document Name Document No. Japanese RA78K0 Assembler Package Operation Assembly Language Structured Assembly Language RA78K Series Structured Assembler Preprocessor CC78K0 C Compiler Operation Language IE-78K0-NS IE-78001-R-EM IE-780308-NS-EM1 IE-780308-R-EM EP-78230 EP-78054GK-R SM78K0 System Simulator Windows Based Reference External Part User Open Interface Specifications Windows Based Reference Reference Reference Guide U11802J U11801J U11789J U12323J U11517J U11518J U13731J To be prepared To be prepared U11362J EEU-985 U13630J U10181J U10092J U12900J U11151J U11539J U11649J English U11802E U11801E U11789E EEU-1402 U11517E U11518E U13731E To be prepared To be prepared U11362E EEU-1515 - U10181E U10092E U12900E - U11539E U11649E
SM78K Series System Simulator ID78K0-NS Integrated Debugger ID78K0 Integrated Debugger ID78K0 Integrated Debugger ID78K0 Integrated Debugger
EWS Based PC Based Windows Based
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
64
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
Documents Related to Embedded Software (User's Manuals)
Document Name Document No. Japanese 78K/0 Series Real-Time OS Fundamentals Installation 78K/0 Series OS MX78K0 Fundamental U11537J U11536J U12257J English U11537E U11536E U12257E
Other Related Documents
Document Name Document No. Japanese SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Microcomputer-Related Products by Third Party X13769X C10535J C11531J C10983J C11892J U11416J C10535E C11531E C10983E C11892E - English
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
Data Sheet U12092EJ1V0DS00
65
PD78F0058, 78F0058Y
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided thst the system conforms to the I 2C Standard Specification as defined by Philips.
66
Data Sheet U12092EJ1V0DS00
PD78F0058, 78F0058Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U12092EJ1V0DS00
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PD78F0058, 78F0058Y
FIP and IEbus are trademarks of NEC Corporation. Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/ or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
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