View R8C11_201885.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

REJ09B0062-0091Z
16
R8C/11 Group
Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES
Preliminary
Before using this material, please visit our website to confirm that this is the most current document available.
Rev. 0.91 Revision date: Sep 08, 2003
www.renesas.com
Keep safety first in your circuit designs!
*
Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. * Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. * All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). * When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. * Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. * The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. * If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. * Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
How to Use This Manual
This hardware manual provides detailed information on features in the R8C/11 Group microcomputer. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputer. Each register diagram contains bit functions with the following symbols and descriptions.
XXX register
b7 b6 b5 b4 b3 b2 b1 b0
*1
Symbol XXX Address XXX After reset 0016
0
Bit symbol
XXX0
Bit name
XXX bit
b1 b0
Function
1 0: XXX 0 1: XXX 1 0: Avoid this setting 1 1: XXX
RW RW
*2
XXX1
RW
(b2)
Nothing is assigned. When write, should set to "0". When read, its content is indeterminate.
(b3)
Reserved bit
Must set to "0"
RW
*3
XXX4
XXX bit
Function varies depending on each operation mode
RW
XXX5
WO
XXX6 0: XXX 1: XXX
RW
XXX7
XXX bit
RO
*1 Blank:Set to "0" or "1" according to your intended use 0: Set to "0" 1: Set to "1" X: Nothing is assigned *2 RW: RO: WO: -: *3 Terms to use here are explained as follows. * Nothing is assigned Nothing is assigned to the bit concerned. When write, set to "0" for new function in future plan. * Reserved bit Reserved bit. Set the specified value. * Avoid this setting The operation at having selected is not guaranteed. * Function varies depending on each operation mode Bit function varies depending on peripheral function mode. Refer to register diagrams in each mode. Read and write Read only Write only Nothing is assigned
M16C Family Documents
Document Short Sheet Data Sheet Hardware Manual
Contents
Hardware overview Hardware overview and electrical characteristics Hardware specifications (pin assignments, memory maps, specifications of peripheral functions, electrical characteristics, timing charts) Detailed description about instructions and microcomputer performance by each instruction * Application examples of peripheral functions * Sample programs * Introductory description about basic functions in M16C family * Programming method with the assembly and C languages
Software Manual Application Note
Table of Contents
SFR Page Reference Chapter 1. Overview .............................................................. 1
1.1 Applications .................................................................................................................... 1 1.2 Performance Outline ...................................................................................................... 2 1.3 Block Diagram ................................................................................................................ 3 1.4 Product Information ....................................................................................................... 4 1.5 Pin Assignments............................................................................................................. 5 1.6 Pin Description ............................................................................................................... 6
Chapter 2. Central Processing Unit (CPU) .......................... 7
2.1 Data Registers (R0, R1, R2 and R3) .............................................................................. 7 2.2 Address Registers (A0 and A1) ..................................................................................... 8 2.3 Frame Base Register (FB) .............................................................................................. 8 2.4 Interrupt Table Register (INTB)...................................................................................... 8 2.5 Program Counter (PC) .................................................................................................... 8 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ...................................... 8 2.7 Static Base Register (SB) .............................................................................................. 8 2.8 Flag Register (FLG) ........................................................................................................ 8 2.8.1 Carry Flag (C Flag) .................................................................................................... 8 2.8.2 Debug Flag (D Flag) ................................................................................................... 8 2.8.3 Zero Flag (Z Flag) ...................................................................................................... 8 2.8.4 Sign Flag (S Flag) ...................................................................................................... 8 2.8.5 Register Bank Select Flag (B Flag) .......................................................................... 8 2.8.6 Overflow Flag (O Flag) .............................................................................................. 8 2.8.7 Interrupt Enable Flag (I Flag) .................................................................................... 8 2.8.8 Stack Pointer Select Flag (U Flag) ........................................................................... 8 2.8.9 Processor Interrupt Priority Level (IPL) .................................................................. 8 2.8.10 Reserved Area.......................................................................................................... 8
Chapter 3. Memory ................................................................ 9 Chapter 4. Special Function Registers (SFR) ................... 10 Chapter 5. Reset .................................................................. 14
5.1 Hardware Reset ............................................................................................................ 14
5.1.1 Hardware Reset 1 .................................................................................................................................. 14 5.1.2 Hardware Reset 2 .................................................................................................................................. 17 5.1.3 Power-on Reset Function ..................................................................................................................... 18
5.2 Software Reset .............................................................................................................. 19 5.3 Watchdog Timer Reset ................................................................................................. 19 A-1
5.4 Voltage Detection Circuit ............................................................................................. 20
5.4.1 Voltage Detection Interrupt .................................................................................................................. 25 5.4.2 Get Out Of Stop Mode Due To The Voltage Detection Interrupt ....................................................... 27
Chapter 6. Clock Generating Circuit.................................. 28
6.1 Main Clock ..................................................................................................................... 33 6.2 Ring Oscillator Clock ................................................................................................... 34
6.2.1 Low-speed Ring Oscillator ................................................................................................................... 34 6.2.2 High-speed Ring Oscillator .................................................................................................................. 34
6.3 CPU Clock and Peripheral Function Clock ................................................................ 35
6.3.1 CPU Clock .............................................................................................................................................. 35 6.3.2 Peripheral Function Clock (f1, f2, f8, f32, fAD, f1SIO, f8SIO, f32SIO, fRING, fRING128) ................ 35 6.3.3 fRING and fRING128 ............................................................................................................................. 35 6.3.4 fRING-fast .............................................................................................................................................. 35
6.4 Power Control ............................................................................................................... 36
6.4.1 Normal Operation Mode ....................................................................................................................... 36 6.4.2 Wait Mode .............................................................................................................................................. 38 6.4.3 Stop Mode .............................................................................................................................................. 39
6.5 Oscillation Stop Detection Function ........................................................................... 42
6.5.1 How to Use Oscillation Stop Detection Function .............................................................................. 42
Chapter 7. Protection .......................................................... 44 Chapter 8. Processor Mode ................................................ 45
8.1 Types of Processor Mode ............................................................................................ 45
Chapter 9. Bus Control ....................................................... 46 Chapter 10. Interrupt ........................................................... 47
10.1 Interrupt Overview ...................................................................................................... 47
10.1.1 Type of Interrupts ................................................................................................................................ 47 10.1.2 Software Interrupts ............................................................................................................................. 48 10.1.3 Hardware Interrupts ............................................................................................................................ 49 10.1.4 Interrupts and Interrupt Vector .......................................................................................................... 50 10.1.5 Interrupt Control ................................................................................................................................. 52
______
10.2 INT Interrupt ................................................................................................................ 60
________
10.2.1 INT0 Interrupt ...................................................................................................................................... 60 _______ 10.2.2 INT0 Input Filter ................................................................................................................................... 61 ______ ______ 10.2.3 INT1 Interrupt and INT2 Interrupt ...................................................................................................... 62 ______ 10.2.4 INT3 Interrupt ...................................................................................................................................... 63
10.3 Key Input Interrupt ..................................................................................................... 65 10.4 Address Match Interrupt ............................................................................................ 66
Chapter 11. Watchdog Timer .............................................. 68 Chapter 12. Timers .............................................................. 70
12.1 Timer X ........................................................................................................................ 71 A-2
12.1.1 Timer Mode .......................................................................................................................................... 73 12.1.2 Pulse Output Mode ............................................................................................................................. 74 12.1.3 Event Counter Mode ........................................................................................................................... 75 12.1.4 Pulse Width Measurement Mode ....................................................................................................... 76 12.1.5 Pulse Period Measurement Mode ..................................................................................................... 78
12.2 Timer Y......................................................................................................................... 80
12.2.1 Timer Mode .......................................................................................................................................... 83 12.2.2 Programmable Waveform Generation Mode .................................................................................... 85
12.3 Timer Z ......................................................................................................................... 88
12.3.1Timer Mode ........................................................................................................................................... 91 12.3.2 Programmable Waveform Generation Mode .................................................................................... 93 12.3.3 Programmable One-shot Generation Mode ...................................................................................... 95 12.3.4 Programmable Wait One-shot Generation Mode ............................................................................. 98
12.4 Timer C ...................................................................................................................... 101
12.4.1 Input Capture Mode ......................................................................................................................... 105 12.4.2 Output Compare Mode .................................................................................................................... 107
Chapter 13. Serial I/O ........................................................ 109
13.1 Clock Synchronous Serial I/O Mode ....................................................................... 114
13.1.1 Polarity Select Function ................................................................................................................... 117 13.1.2 LSB First/MSB First Select Function .............................................................................................. 117 13.1.3 Continuous Receive Mode ............................................................................................................... 118
13.2 Clock Asynchronous Serial I/O (UART) Mode ....................................................... 119
13.2.1 TxD10/RxD1 Select Function (UART1) ............................................................................................ 122 13.2.2 TxD11 Select Function (UART1) ...................................................................................................... 122
Chapter 14. A-D Converter ............................................... 123
14.1 One-shot Mode ......................................................................................................... 127 14.2 Repeat Mode ............................................................................................................. 129 14.3 Sample and Hold ...................................................................................................... 131
Chapter 15. Programmable I/O Ports .............................. 132
15.1 Description ................................................................................................................ 132 15.2 Unassigned Pin Handling ........................................................................................ 140
Chapter 16. Electrical Characteristics ............................. 141 Chapter 17. Flash Memory Version ................................. 148
17.1 Overview .................................................................................................................... 148 17.2 Memory Map .............................................................................................................. 149 17.3 Functions To Prevent Flash Memory from Rewriting............................................ 150
17.3.1 ID Code Check Function .................................................................................................................. 150
17.4 CPU Rewrite Mode .................................................................................................... 151
17.4.1 EW0 Mode .......................................................................................................................................... 152 17.4.2 EW1 Mode .......................................................................................................................................... 152
A-3
17.4.3 Software Commands ........................................................................................................................ 158 17.4.4 Status Register .................................................................................................................................. 162 17.4.5 Full Status Check .............................................................................................................................. 163
17.5 Standard Serial I/O Mode ......................................................................................... 165
17.5.1 ID Code Check Function .................................................................................................................. 165
Chapter 18. On-chip Debugger ........................................ 169
18.1 Address Match Interrupt .......................................................................................... 169 18.2 Single Step Interrupt ................................................................................................ 169 18.3 UART1 ........................................................................................................................ 169 18.4 BRK Instruction ........................................................................................................ 169
Chapter 19. Usage Notes .................................................. 170
19.1 Stop Mode and Wait Mode ....................................................................................... 170 19.2 Interrupts ................................................................................................................... 170
19.2.1 Reading Address 0000016 ................................................................................................................ 170 19.2.2 SP Setting .......................................................................................................................................... 170 19.2.3 External Interrupt and Key Input Interrupt ..................................................................................... 170 19.2.4 Watchdog Timer Interrupt ................................................................................................................ 170 19.2.5 Changing Interrupt Source .............................................................................................................. 170 19.2.6 Changing Interrupt Control Register .............................................................................................. 172
19.3 Timers ........................................................................................................................ 173
19.3.1 Timers X, Y and Z .............................................................................................................................. 173 19.3.2 Timer X ............................................................................................................................................... 173 19.3.3 Timer Z ............................................................................................................................................... 173 19.3.4 Timer C ............................................................................................................................................... 173
19.4 Serial I/O .................................................................................................................... 174 19.5 A-D Converter ........................................................................................................... 175 19.6 Flash Memory Version ............................................................................................. 176
19.6.1 CPU Rewrite Mode ............................................................................................................................ 176
19.7 Noise .......................................................................................................................... 178
Chapter 20. Usage Notes for On-chip Debugger ............ 179 Appendix 1 Package Dimensions .................................... 180 Appendix 2 Connecting Examples for Serial Writer and On-chip Debugging Emulator .......................................... 181 Register Index ................................................................... 183 R8C/11 Group Usage Note Reference Book
For the most current Usage Note Reference Book, please visit our website.
A-4
SFR Page Reference
Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
Register
Symbol Page
Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16
Register
Symbol Page
Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 High-speed ring control register 0 Address match interrupt enable register Protect register High-speed ring control register 1 Oscillation stop detection register Watchdog timer reset register Watchdog timer start register Watchdog timer control register Address match interrupt register 0
PM0 45 PM1 45 CM0 30 CM1 30 HR0 32 AIER 67 PRCR 44 HR1 32 OCD 31 WDTR 69 WDTS 69 WDC 69 RMAD0 67
Key input interrupt control register KUPIC A-D conversion interrupt control register ADIC
Compare 2 interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register
53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53
Address match interrupt register 1
RMAD1
67
Voltage detection register 1 Voltage detection register 2
VCR1 VCR2
21 21
INT2 interrupt control register Timer X interrupt control register Timer Y interrupt control register Timer Z interrupt control register INT1 interrupt control register INT3 interrupt control register Timer C interrupt control register
Compare 1 interrupt control register
INT0 interrupt control register
CMP2IC S0TIC S0RIC S1TIC S1RIC INT2IC TXIC TYIC TZIC INT1IC INT3IC TCIC CMP1IC INT0IC
INT0 input filter select register Voltage detection interrupt register
INT0F D4INT
60 22
Blank columns are all reserved space. No use is allowed.
B-1
SFR Page Reference
Address 008016 008116 008216 008316 008416 008516 008616 008716 008816 008916 008A16 008B16 008C16 008D16 008E16 008F16 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C16 009D16 009E16 009F16 00A016 00A116 00A216 00A316 00A416 00A616 00A716 00A816 00A916 00AA16 00AB16 00AC16 00AE16 00AF16 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 00BC16 00BD16 00BE16 00BF16
01B316 01B416 01B516 01B616 01B716
Register Timer Y, Z mode register Prescaler Y Timer Y secondary Timer Y primary
Symbol Page TYZMR 80/88 PREY 81 TYSC 81 TYPR 81 Timer Y, Z waveform output control register PUM 82/90 Prescaler Z PREZ 89 Timer Z secondary TZSC 89 Timer Z primary TZPR 89
Address 00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16
Register A-D register
Symbol Page AD 126
Timer Y, Z output control register Timer X mode register Prescaler X Timer X register Count source set register Timer C register
TYZOC 81/89 TXMR 71 PREX 72 TX 72 TCSS 72/82/90 TC 103
00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 03FA16 00FB16 00FC16 00FD16 00FE16 00FF16
A-D control register 2 A-D control register 0 A-D control register 1
ADCON2 126 ADCON0 125 ADCON1 125
External input enable register Key input enable register Timer C control register 0 Timer C control register 1 Capture and compare 0 register Compare 1 register
UART0 transmit/receive mode register
INTEN KIEN TCC0 TCC1 TM0 TM1 U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON
60 65 103 104 103 103 112 111 111 112 111 111 112 111 111 112 113 111 113
Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P3 register Port P3 direction register Port P4 register Port P4 direction register
P0 P1 PD0 PD1 P3 PD3 P4 PD4
138 138 138 138 138 138 138 138
UART0 bit rate generator UART0 transmit buffer register
UART0 transmit/receive control register 0 00A516 UART0 transmit/receive control register 1
UART0 receive buffer register
UART1 transmit/receive mode register
UART1 bit rate generator UART1 transmit buffer register
UART1 transmit/receive control register 0 00AD16 UART1 transmit/receive control register 1
UART1 receive buffer register UART transmit/receive control register 2
Pull-up control register 0 Pull-up control register 1 Port P1 drivability control register Timer C output control register
PUR0 139 PUR1 139 DRR 139 TCOUT 104
Flash memory control register 4 Flash memory control register 1 Flash memory control register 0
FMR4 FMR1 FMR0
144 144 143
Blank columns are all reserved space. No use is allowed.
B-2
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
1. Overview
1. Overview
This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing instructions at high speed.
1.1 Applications
Electric household appliance, office equipment, housing equipment (sensor, security), general industrial equipment, audio, etc.
Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition.
Rev.0.91
2003 Sep 08
page 1 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
1. Overview
1.2 Performance Outline
Table 1.1. lists the performance outline of this MCU. Table 1.1 Performance outline Item Performance CPU Number of basic instructions 89 instructions Shortest instruction execution time 50 ns (f(XIN) = 20 MHZ, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHZ, VCC = 2.7 to 5.5 V) Operating mode Single-chip Address space 1M bytes Memory capacity See Table 1.2. Peripheral Interrupt Internal: 10 sources, External: 5 sources, function Software: 4 sources, Priority level: 7 levels Watchdog timer 15 bits x 1 (with prescaler) Timer Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel, Timer Z: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer C: 16 bits x 1 channel Circuits of input capture and output compare. Serial I/O *1 channel Clock synchronous, UART *1 channel UART A-D converter 10-bit A-D converter: 1 circuit, 12 channels Clock generation circuit 2 circuits *Main clock generation circuit (Equipped with a built-in feedback resistor) *Ring oscillator (high speed, low speed) On High-speed ring oscillator the frequency adjustment function is usable. Oscillation stop detection function Stop detection of main clock oscillation Voltage detection circuit Included Power on reset circuit Included Port Input/Output: 22 (including LED drive port), Input: 2 (LED drive I/O port: 8, max. 20 mA) Electrical Power supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHZ) characteristics VCC = 2.7 to 5.5 V (f(XIN) = 10 MHZ) Power consumption TBD (VCC = 5.0 V, (f(XIN) = 20 MHZ) TBD (VCC = 3.0 V, (f(XIN) = 10 MHZ) TBD (VCC = 3.0 V, Wait mode) TBD (VCC = 3.0 V, Stop mode) Flash memory Program/erase voltage VCC = 2.7 to 5.5 V Number of program/erase 100 times Operating ambient temperature -20 to 85 C -40 to 85 C (option) Package 32-pin plastic mold LQFP Option: If you require this option, please specify so.
Rev.0.91
2003 Sep 08
page 2 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
1. Overview
1.3 Block Diagram
Figure 1.1 shows this MCU block diagram.
8
8
5
1
2
I/O port
Port P0
Port P1
Port P3
Port P4
Peripheral functions
Timer A-D converter (10 bits 12 channels) System clock generator UART or Clock synchronous serial I/O (8 bits 1 channel) UART (8 bits 1 channel) XIN-XOUT High-speed ring oscillator Low-speed ring oscillator
Timer X (8 bits) Timer Y (8 bits) Timer Z (8 bits) Timer C (16 bits)
R8C Series CPU core
Watchdog timer (15 bits)
R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG
Memory
ROM (Note 1) RAM (Note 2)
Multiplier
Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type.
Figure 1.1 Block Diagram
Rev.0.91
2003 Sep 08
page 3 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
1. Overview
1.4 Product Information
Table 1.2 lists the products. Table 1.2 Product List
Type No. ROM capacity 8K bytes 12K bytes 16K bytes 8K bytes 12K bytes 16K bytes RAM capacity 512 bytes 768 bytes 1K bytes 512 bytes 768 bytes 1K bytes Package type 32P6U-A 32P6U-A 32P6U-A 32P6U-A 32P6U-A 32P6U-A D version As of September 2003 Remarks Flash memory version
** R5F21113FP ** R5F21114FP ** R5F21112DFP ** R5F21113DFP ** R5F21114DFP ** : Under development **
Type No. R 5 F
R5F21112FP
21 11 4 D FP
Package type: FP : 32P6U Shows characteristics and others. D: Operating ambient temperature -40 C to 85 C No symbol: Operating ambient temperature -20 C to 85 C ROM capacity: 2 : 8 KBytes. 3 : 12 KBytes. 4 : 16 KBytes. R8C/11 group
R8C/Tiny series
Memory type: F: Flash memory version
Renesas MCU Renesas semiconductors
Figure 1.2 Type No., Memory Size, and Package
Rev.0.91
2003 Sep 08
page 4 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
1. Overview
1.5 Pin Assignments
Figure 1.3 shows the pin configuration (top view).
PIN CONFIGURATION (top view)
24 23 22 21 20 19 18 17 P06/AN1 P05/AN2 P04/AN3 MODE P03/AN4 P02/AN5 P01/AN6 P00/AN7/TxD11 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 P45/INT0 P10/KI0/AN8/CMP00 P11/KI1/AN9/CMP01 P12/KI2/AN10/CMP02 P13/KI3/AN11 P14/TxD0 P15/RxD0 P16/CLK0
R8C/11 Group
12345678
Notes: 1. P47 functions only as an input port. 2. When using On-chip debugger, do not use pins P00/AN7/TxD11 and P37/TxD10/RxD1.
RESET XOUT/P47 (Note 1) VSS XIN/P46 VCC P17/INT1/CNTR0
P37/TxD10/RxD1 CNVSS
P30/CNTR0/CMP10 AVSS P31/TZOUT/CMP11 AVCC/VREF P32/INT2/CNTR1/CMP12 P33/INT3/ TCIN
P07/AN0 IVCC
Package: 32P6U-A
Figure 1.3 Pin Configuration (Top View)
Rev.0.91
2003 Sep 08
page 5 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
1. Overview
1.6 Pin Description
Table 1.3 shows the pin description Table 1.3 Pin description Signal name Power supply input IVcc Analog power supply input Reset input CNVss MODE Main clock input Pin name Vcc, Vss IVcc AVcc, AVss
___________
I/O type Input Output Input
RESET CNVss MODE XIN
Input Input Input Input Output
_______
Main clock output XOUT
_____ _______
INT interrupt input INT0 to INT3 _____ _____ Key input interrupt KI0 to KI3 input Timer X CNTR0 __________ CNTR0 Timer Y CNTR1 Timer Z TZOUT Timer C TCIN CMP00 to CMP03, CMP10 to CMP13 Serial interface CLK0 RxD0, RxD1 TxD0, TxD10, TxD11 Reference voltage VREF input A-D converter AN0 to AN11 I/O port P00 to P07, P10 to P17, P30 to P33, P37, P45
Input Input Input/Output Output Input/Output Output Input Output Input/Output Input Output Input Input Input/Output
Function Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the Vss pin. Connect this pin to Vss via a capacitor (0.1 F). These are power supply input pins for A-D converter. Connect the AVss pin to Vss. Connect a capacitor between pins AVcc and AVss. "L" on this input resets the MCU. Connect this pin to Vss via a resistor (approximately 5 k). Connect this pin to Vcc via a resistor (approximately 5 k). These pins are provided for the main clock generating circuit input/output. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. ______ These are INT interrupt input pins. These are key input interrupt input pins. This is the timer X I/O pin. This is the timer X output pin. This is the timer Y I/O pin. This is the timer Z output pin. This is the timer C input pin. These are the timer C output pins. This is a transfer clock I/O pin. These are serial data input pins. These are serial data output pins. This is a reference voltage input pin for A-D converter. These are analog input pins for A-D converter. These are 8-bit CMOS I/O ports. Each port has an input/output select direction register, allowing each pin in that port to be directed for input or output individually. Any port set to input can select whether to use a pullup resistor or not by program. P10 to P17 also function as LED drive ports. These are input only pins.
Input port
P46, P47
Input
Rev.0.91
2003 Sep 08
page 6 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks.
b31
b15
b8 b7
b0
R2 R3
R0H(R0's high bits) R0L(R0's low bits) R1H(R1's high bits) R1L(R1's low bits) R2 R3 A0 A1 FB Address registers (Note 1) Frame base registers (Note 1)
b0
Data registers (Note 1)
b19
b15
INTBH
INTBL
Interrupt table register
The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.
b19 b0
PC
b15 b0
Program counter
USP ISP SB
b15 b0
User stack pointer Interrupt stack pointer Static base register
FLG
b15 b8 b7 b0
Flag register
IPL
U I OB SZ DC
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area
Note 1: These registers comprise a register bank. There are two register banks.
Figure 2.1 Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32bit data register (R2R0). R3R1 is the same as R2R0.
Rev.0.91
2003 Sep 08
page 7 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
2. Central Processing Unit (CPU)
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status. 2.8.1 Carry Flag (C Flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 Debug Flag (D Flag) The D flag is used exclusively for debugging purpose. During normal use, it must be set to "0". 2.8.3 Zero Flag (Z Flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, it is "0". 2.8.4 Sign Flag (S Flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, it is "0". 2.8.5 Register Bank Select Flag (B Flag) Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1". 2.8.6 Overflow Flag (O Flag) This flag is set to "1" when the operation resulted in an overflow; otherwise, it is "0". 2.8.7 Interrupt Enable Flag (I Flag) This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is "0", and are enabled when the I flag is "1". The I flag is cleared to "0" when the interrupt request is accepted. 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is "0"; USP is selected when the U flag is "1". The U flag is cleared to "0" when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt is enabled. 2.8.10 Reserved Area When write to this bit, write "0". When read, its content is indeterminate.
Rev.0.91
2003 Sep 08
page 8 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
3. Memory
3. Memory
Figure 3.1 is a memory map of this MCU. The address space extends the 1M bytes from address 0000016 to FFFFF16. The internal ROM is allocated in a lower address direction beginning with address 0FFFF16. For example, a 16-Kbyte internal ROM is allocated to the addresses from 0C00016 to 0FFFF16. The fixed interrupt vector table is allocated to the addresses from 0FFDC16 to 0FFFF16. Therefore, store the start address of each interrupt routine here. The internal RAM is allocated in an upper address direction beginning with address 0040016. For example, a 1-Kbyte internal RAM is allocated to the addresses from 0040016 to 007FF16. In addition to storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated. Special function registers (SFR) are allocated to the addresses from 0000016 to 002FF16. Peripheral function control registers are located here. Of the SFR, any space which has no functions allocated is reserved for future use and cannot be used by users.
0000016 SFR
(See Chapter 4 for details.)
002FF16
0040016 Internal RAM 0XXXX16 0FFDC16 Undefined instruction Overflow BRK instruction Address match Single step
Watchdog timer,Oscillation stop detection,Voltage detection
0YYYY16 Internal ROM 0FFFF16 Expanding area FFFFF16 0FFFF16
(Reserved) (Reserved) Reset
Type name
R5F21114FP, R5F21114DFP R5F21113FP, R5F21113DFP R5F21112FP, R5F21112DFP
Internal ROM Address 0YYYY16 Size
16K bytes 12K bytes 8K bytes 0C00016 0D00016 0E00016
Internal RAM Address 0XXXX16 Size
1K bytes 768 bytes 512 bytes 007FF16 006FF16 005FF16
Figure 3.1 Memory Map
Rev.0.91
2003 Sep 08
page 9 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
4. Special Function Register (SFR)
4. Special Function Register (SFR)
Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
Register
Symbol
After reset
Processor mode register 0 1 Processor mode register 1 System clock control register 0 System clock control register 1 High-speed ring control register 0 Address match interrupt enable register Protect register High-speed ring control register 1 Oscillation stop detection register Watchdog timer reset register Watchdog timer start register Watchdog timer control register Address match interrupt register 0
PM0 PM1 CM0 CM1 HR0 AIER PRCR HR1 OCD WDTR WDTS WDC RMAD0
0016 0016 011010002 001000002 0016 XXXXXX002 00XXX0002 4016 000001002 XX16 XX16 000XXXXX2 0016 0016 X016 0016 0016 X016
Address match interrupt register 1
RMAD1
Voltage detection register 1 2 Voltage detection register 2 2
VCR1 VCR2
0016 1000000016
INT0 input filter select register Voltage detection interrupt register 2
INT0F D4INT
XXXXX0002 0016 3
010000012 4
X : Undefined Blank columns are all reserved space. No access is allowed. Notes: 1. Software reset or the watchdog timer reset does not affect bits 0 to 1 of PM0 register. 2. Software reset or the watchdog timer reset does not affect this register. 3. Owing to Reset input. 4. In the case of RESET pin = "H" retaining.
Rev.0.91
2003 Sep 08
page 10 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
4. Special Function Register (SFR)
Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16
Register
Symbol
After reset
Key input interrupt control register A-D conversion interrupt control register
Compare 2 interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register
KUPIC ADIC CMP2IC S0TIC S0RIC S1TIC S1RIC INT2IC TXIC TYIC TZIC INT1IC INT3IC TCIC CMP1IC INT0IC
XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XX00X0002
INT2 interrupt control register Timer X interrupt control register Timer Y interrupt control register Timer Z interrupt control register INT1 interrupt control register INT3 interrupt control register Timer C interrupt control register
Compare 1 interrupt control register
INT0 interrupt control register
X : Undefined Blank columns are all reserved space. No access is allowed.
Rev.0.91
2003 Sep 08
page 11 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
4. Special Function Register (SFR)
Address 008016 008116 008216 008316 008416 008516 008616 008716 008816 008916 008A16 008B16 008C16 008D16 008E16 008F16 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C16 009D16 009E16 009F16 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 00A916 00AA16 00AB16 00AC16 00AD16 00AE16 00AF16 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 00BC16 00BD16 00BE16 00BF16
Register Timer Y, Z mode register Prescaler Y Timer Y secondary Timer Y primary Timer Y, Z waveform output control register Prescaler Z Timer Z secondary Timer Z primary
Symbol TYZMR PREY TYSC TYPR PUM PREZ TZSC TZPR
After reset 0016 FF16 FF16 FF16 0016 FF16 FF16 FF16
Timer Y, Z output control register Timer X mode register Prescaler X Timer X register Count source set register Timer C register
TYZOC TXMR PREX TX TCSS TC
0016 0016 FF16 FF16 0016 0016 0016
External input enable register Key input enable register Timer C control register 0 Timer C control register 1 Capture, compare 0 register Compare 1 register
UART0 transmit/receive mode register
INTEN KIEN TCC0 TCC1 TM0 TM1 U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON
0016 0016 0016 0016 XX16 XX16 XX16 XX16 0016 XX16 XX16 XX16 000010002 000000102 XX16 XX16 0016 XX16 XX16 XX16 000010002 000000102 XX16 XX16 0016
UART0 bit rate generator UART0 transmit buffer register
UART0 transmit/receive control register 0 UART0 transmit/receive control register 1
UART0 receive buffer register
UART1 transmit/receive mode register
UART1 bit rate generator UART1 transmit buffer register
UART1 transmit/receive control register 0 UART1 transmit/receive control register 1
UART1 receive buffer register
UART transmit/receive control register 2
X : Undefined Blank columns are all reserved space. No access is allowed.
Rev.0.91
2003 Sep 08
page 12 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
4. Special Function Register (SFR)
Address
00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 03FA16 00FB16 00FC16 00FD16 00FE16 00FF16
Register A-D register
Symbol AD
After reset XX16 XX16
A-D control register 2 A-D control register 0 A-D control register 1
ADCON2 ADCON0 ADCON1
0016 00000XXX2 0016
Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P3 register Port P3 direction register Port P4 register Port P4 direction register
P0 P1 PD0 PD1 P3 PD3 P4 PD4
XX16 XX16 0016 0016 XX16 0016 XX16 0016
Pull-up control register 0 Pull-up control register 1 Port P1 drivability control register Timer C output control register
PUR0 PUR1 DRR TCOUT
00XX00002 XXXXXX0X2 0016 0016
01B316 01B416 01B516 01B616 01B716
Flash memory control register 4 Flash memory control register 1 Flash memory control register 0
FMR4 FMR1 FMR0
0100000X2 0100XX0X2 XX0000012
X : Undefined Blank columns are all reserved space. No access is allowed.
Rev.0.91
2003 Sep 08
page 13 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5.1 Hardware Reset
5. Reset
There are three types of resets: a hardware reset, a software reset, and an watchdog timer reset.
5.1 Hardware Reset
There are three kinds of hardware reset: hardware reset 1, hardware reset 2, and power-on reset.
5.1.1 Hardware Reset 1
____________ ____________
A reset is applied using the RESET pin. When an "L" signal is applied to the RESET pin while the power supply voltage is within the recommended operating condition, the pins are initialized (see
____________ ____________
Table 5.1 "Pin Status When RESET Pin Level is 'L'"). When the input level at the RESET pin is released from "L" to "H", the CPU and SFR are initialized, and the program is executed starting from the address indicated by the reset vector. Figure 5.1 shows the CPU register status after ____________ reset and figure 5.2 shows the reset sequence. The internal RAM is not initialized. If the RESET pin is pulled "L" while writing to the internal RAM, the internal RAM becomes indeterminate. Figures 5.3 to 5.4 show the reset circuit example using the hardware reset 1. Refer to Chapter 4, "Special Function Register (SFR)" for the status of SFR after reset. * When the power supply is stable ____________ (1) Apply an "L" signal to the RESET pin. (2) Wait 500 s. ____________ (3) Apply an "H" signal to the RESET pin. * Power on
____________
(1) Apply an "L" signal to the RESET pin. (2) Let the power supply voltage increase until it meets the recommended operating condition. (3) Wait td(P-R) or more until the internal power supply stabilizes. (4) Wait 500 s. ____________ (5) Apply an "H" signal to the RESET pin.
detection circuit monitors the voltage supplied to the VCC pin.
____________
Table 5.1 Pin Status When RESET Pin Level is "L"
Pin name
P0 P1 P30 to P33, P37 P45 to P47 Input port Input port
Status
Input port Input port
Rev.0.91
2003 Sep 08
page 14 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5.1 Hardware Reset
b15
b0
000016 000016 000016 000016 000016 000016 000016
Data register(R0) Data register(R1) Data register(R2) Data register(R3) Address register(A0) Address register(A1) Frame base register(FB)
b0
b19
0000016 Content of addresses 0FFFE16 to 0FFFC16
b15 b0
Interrupt table register(INTB) Program counter(PC)
000016 000016 000016
b15 b0
User stack pointer(USP) Interrupt stack pointer(ISP) Static base register(SB)
000016
b15 b8 b7 b0
Flag register(FLG)
IPL
UI
OBS Z DC
Figure 5.1 CPU Register Status After Reset
Internal ring oscillation More than 20 cycles are needed
RESET
CPU clock: 28cycles
CPU clock 0FFFC16 Address
(Internal address signal)
0FFFE16
0FFFD16
Content of reset vector
Figure 5.2 Reset Sequence
Rev.0.91
2003 Sep 08
page 15 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5.1 Hardware Reset
VCC 0V RESET VCC RESET 0V
2.7V
Equal to or less than 0.2VCC More than td(P-R) + 500 s are needed.
Figure 5.3 Example Reset Circuit Using The Hardware Reset 1
5V VCC RESET VCC
Supply voltage detection circuit
2.7V
0V 5V RESET 0V More than td(P-R) + 500 s are needed. Example when VCC = 5V.
Figure 5.4 Example Reset Circuit Using The Hardware Reset 1 (Voltage Check Circuit)
Rev.0.91
2003 Sep 08
page 16 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5.1 Hardware Reset
5.1.2 Hardware Reset 2
The microcomputer is reset when the voltage at the VCC input pin drops below Vdet if all of the following conditions hold true. * The VC27 bit in the VCR2 register is set to "1" (voltage detection circuit enabled) * The D40 bit in the D4INT register is set to "1" (voltage detection interrupt enabled) * The D46 bit in the D4INT register is set to "1" (hardware reset 2 when going through Vdet) Conversely, when the input voltage at the VCC pin rises to Vdet or more, the pins, CPU, and SFR are initialized, and the program is executed starting from the address indicated by the reset vector. The initialized pins and registers and the status thereof are the same as in hardware reset 1. Refer to Section 5.4 "Voltage Detection Circuit."
Rev.0.91
2003 Sep 08
page 17 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5.1 Hardware Reset
5.1.3 Power-on Reset Function The power-on reset is the function which can reset the microcomputer without the external reset
____________
circuit. The RESET pin should be connected to the VCC pin via about 5 k pull-up resistance using the power-on reset function, the function turns to active. When the input voltage at the VCC pin reaches to the Vdet level, count operation of the low-speed ring oscillator clock starts. When the operation counts the low-speed ring oscillator clock for 32 times, the microcomputer has its pins, CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset vector. The initialized pins and registers and the status thereof are the same as in hardware reset 1. * The D40 bit in the D4INT register turns to "1" automatically (voltage detection interrupt enabled) * The D46 bit in the D4INT register turns to "1" automatically (hardware reset 2 when going through Vdet) Additionally, the hardware reset 2 turns to active after the power-on reset. This is because the VC27 bit in the VCR2 register is set to "1" (voltage detection circuit enabled) after the power-on reset same as the hardware reset 1, so that hardware reset 2 active conditions are all satisfied including above D40 and D46 bit conditions. Figure 5.5 shows the power-on reset circuit. Figure 5.6 shows the power-on reset operation.
Internal reset signal RESET
S
Q
R fRING-S 5 bit counter Trigger VCC Vdet detection
Figure 5.5 Power-on Reset Circuit
VCC 0.5 V RESET about 5 k Internal reset signal Vcc 0V
2.7 V
Vdet
1 ms or more Less than100 s
1 fRING-S x 32
Figure 5.6 Power-on Reset Operation
Rev.0.91
2003 Sep 08
page 18 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5.2 Software Reset, 5.3 Watchdog Timer Reset
5.2 Software Reset When the PM03 bit in the PM0 register is set to "1" (microcomputer reset), the microcomputer has its pins, CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset vector. Some SFRs are not initialized by the software reset. Refer to Chapter 4, "SFR." 5.3 Watchdog Timer Reset Where the PM12 bit in the PM1 register is "1" (reset when watchdog timer underflows), the microcomputer initializes its pins, CPU and SFR if the watchdog timer underflows. Then the program is executed starting from the address indicated by the reset vector. Some SFRs are not initialized by the watchdog timer reset. Refer to Chapter 4, "SFR."
Rev.0.91
2003 Sep 08
page 19 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5.4 Voltage Detection Circuit
5.4 Voltage Detection Circuit
The voltage detection circuit has a circuit to monitor the input voltage at the VCC pin with Vdet. Besides the program, the hardware reset 2 and voltage detection interrupt can be used to check the input voltage at the VCC pin. Figure 5.7 shows the voltage detection circuit. Figure 5.8 shows VCR1 and VCR2 registers. Figure 5.9 shows the D4INT register. Figure 5.10 shows an operation example of the voltage detection circuit. Figure 5.11 to 5.12 show the operation example of the voltage detection circuit to get out of stop mode.
VC27
VCC1 VREF
+
Noise canceller
VCR1 register b3 VC13 bit
Voltage detection interrupt signal
Figure 5.7 Voltage Detection Circuit Block
Rev.0.91
2003 Sep 08
page 20 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5.4 Voltage Detection Circuit
Voltage detection register 1
b7 b6 b5 b4 b3 b2 b1 b0
0000
000
Symbol VCR1 Bit symbol
(b2-b0)
Address 001916 Bit name Reserved bit Voltage monitor flag1
After reset2 0016 Function Should set to "0" 0:VCC < Vdet 1:VCC Vdet or voltage detection circuit disabled RW RW RO
VC13
RW Should set to "0" Reserved bit (b7-b4) Notes: 1. The VC13 bit is valid when the VC27 bit in the VCR2 register is set to "1" (voltage detection circuit enabled). The VC13 bit is set to "1" (VCCVdet or voltage detection circuit disabled) when the VC27 bit in the VCR2 register is set to "0" (voltage detection circuit disabled). 2. Software reset or the watchdog timer reset does not affect this register.
Voltage detection register 21
b7 b6 b5 b4 b3 b2 b1 b0
0000000
Symbol VCR2 Bit symbol
(b6-b0)
Address 001A16 Bit name Reserved bit Voltage monitor bit2
After reset3 100000002 Function Should set to "0" 0: Voltage detection circuit disabled 1: Voltage detection circuit enabled RW RW RW
VC27
Notes: 1. Set the PRC3 bit in the PRCR register to "1" (write enabled) before writing to this register. 2. Set the VC27 bit to "1" (voltage detect circuit enabled) when hardware reset 2 is used, or the VC13 bit in the VCR1 register or D42 bit in the D4INT register is used, or the D40 bit is set to "1" (enabled). 3. Software reset or the watchdog timer reset does not affect this register.
Figure 5.8 VCR1 Register and VCR2 Register
Rev.0.91
2003 Sep 08
page 21 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5.4 Voltage Detection Circuit
Voltage detection interrupt register1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol D4INT
Bit symbol D40 D41
Address 001F16
After reset10 Reset input : 0016 RESET pin = "H" retaining : 010000012 Function
0 : Disable 1 : Enable 0: Disable (do not use the voltage detection interrupt to get out of stop mode) 1: Enable (use the voltage detection interrupt to get out of stop mode)
Bit name
Voltage detection interrupt enable bit7 STOP mode deactivation control bit2
RW RW
RW
D42 D43 DF0
Voltage change detection flag3, 4, 5 WDT overflow detect flag3, 4 Sampling clock select bit
0: Not detected 1: Vdet passing detection 0: Not detected (flag clear) 1: Detected
b5b4
RW RW RW RW RW
DF1 D46
00 : fRING-S divided by 1 01 : fRING-S divided by 2 10 : fRING-S divided by 4 11 : fRING-S divided by 8
Voltage monitor mode select bit6
0: Voltage detection interrupt request is generated when passing through Vdet 1: Hardware reset 2 when passing through Vdet
D47
Stop mode exiting condition select bit8
Notes: 1. Set the PRC3 bit in the PRCR register to "1" (write enable) before writing to this register. 2. If the voltage detection interrupt needs to be used to get out of stop mode again after once used for that purpose, reset the D41 bit by writing a "0" and then a "1". 3. Valid when the VC27 bit in the VCR2 register is set to "1" (voltage detection circuit enabled). 4. If the VC27 bit is set to "0" (voltage detection circuit disabled), the D42 and D43 bits are set to "0" (not detected). 5. This bit is set to "0" by writing a "0" in a program. (writing a "1" has no effect.) 6. Valid when the D40 bit is set to "1" (voltage detection interrupt enabled). 7. The D40 bit is valid when the VC27 bit in the VCR2 register is set to "1" (voltage detection circuit enabled). When setting the D40 bit to "1", the following setting is required. (1) Set the VC27 bit "1". (2) Wait for td(E-A) until the detecter circuit operates. (3) Wait for the sampling time (the sampling clock which is selected in the DF0 bit to DF1 bit times 4 cycles.) (4) Set the D40 bit to "1". (5) Set the CM14 bit in the CM1 register to "0" (low-speed ring oscillator on). 8. Valid when the D41 bit is set to "1" (enable). 9. The D46 bit can be selected. 10. The software reset or the watchdog timer reset do not affect this register.
In stop mode, voltage detection RW interrupt request is generated or hardware reset 2 when Vcc passes Vdet9 0: Over Vdet 1: Below Vdet
Figure 5.9 D4INT Register
Rev.0.91
2003 Sep 08
page 22 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5.4 Voltage Detection Circuit
5.0 V Vdet VCC Sampling time (3 to 4 clock)
5.0 V 1
fRING
x 32
Internal reset signal (D46 bit=1) VC13 bit Set to"1" by program (voltage detection circuit enabled) VC27 bit Interrupt acknowledged Sampling time (3 to 4 clock) Interrupt acknowledged
Voltage detection interrupt request (D46 bit=0)
The above applies to the following conditions. * D4INT register D40 bit = 1 (voltage detection interrupt enabled) * D4INT register D41 bit = 0 (do not use voltage detection interrupt to get out of stop mode) Sampling time : 4 cycles of sampling clock selected in DF0 bit to DF1 bit
Figure 5.10 Operation Example of Voltage Detection Circuit
Rev.0.91
2003 Sep 08
page 23 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5.4 Voltage Detection Circuit
5.0V Vdet VCC
Internal reset signal(D46 bit = 1)
VC13 bit
Set to "1" by program (voltage detection circuit enabled)
VC27 bit
CM 10 bit
Interrupt acknowledged
Voltage detection interrupt request (D46 bit = 0) The above applies to the following conditions. CM10 : CM1 register bit D4INT register D40 = 1 (voltage detection interrupt enabled) VC13 : VCR1 register bit D4INT register D41 = 1 (use voltage deteciton interrupt to get out of stop mode) VC27 : VCR2 register bit D4INT register D47 = 1 ( Vcc is below Vdet) D46 : D4INT register bit Sampling time : 4 cycles of sampling clock selected in DF0 bit to DF1 bit
Figure 5.11 Operation Example of Voltage Detection Circuit in use to get out of stop mode (1)
5.0V Vdet VCC 1 x 32 fRING
Internal reset signal (D46 bit = 1) VC13 bit
Set to "1" by program (voltage detection circuit enabled)
VC27 bit
CM10 bit
Interrupt acknowledged
Voltage detection interrupt request (D46 bit = 0) The above applies to the following conditions. D4INT register D40 bit = 1 (voltage detection interrupt enabled) D4INT register D41 bit = 1 (use voltage detection interrupt to get out of stop mode) D4INT register D47 bit = 0 (Vcc is over Vdet) Sampling time : 4 cycles of sampling clock selected in DF0 bit to DF1 bit
CM10 : CN1 register bit VC13 : VCR1 register bit VC27 : VCR2 register bit D46 : D4INT register bit
Figure 5.12 Operation Example of Voltage Detection Circuit in use to get out of stop mode (2)
Rev.0.91
2003 Sep 08
page 24 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5.4 Voltage Detection Circuit
5.4.1 Voltage Detection Interrupt Figure 5.13 shows the block diagram of voltage detection interrupt generation circuit. Refer to 5.4.2, "Exiting Stop Mode on a Voltage Detection Circuit" for Getting out of stop mode due to the voltage detection interrupt. A voltage detection interrupt is generated when the input voltage at the VCC pin rises to Vdet or more or drops below Vdet if all of the following conditions hold true in normal operation mode and wait mode. * The VC27 bit in the VCR2 register is set to "1" (voltage detection circuit enabled) * The D40 bit in the D4INT register is set to "1" (voltage detection interrupt enabled) * The D46 bit in the D4INT register is set "0" (voltage detection interrupt selected) To use the voltage detection interrupt , set the CM14 bit in the CM1 register to "0" (low-ring oscillator). Figure 5.14 shows an operation example of voltage detection interrupt generation circuit. The voltage detection interrupt shares the interrupt vector with the watchdog timer interrupt and oscillation stop detection interrupt. The D42 bit in the D4INT register becomes "1" when passing through Vdet is detected after the voltage inputted to the VCC pin is up or down. A voltage detection interrupt request is generated when the D42 bit changes state from "0" to "1". The D42 bit needs to be set to "0" in a program. Table 5.2 lists the voltage detection interrupt request generation conditions. It takes 4 cycles of sampling clock until the D42 bit is set to "1" since the voltage which inputs to Vcc pin passes Vdet. It is possible to set the sampling clock detecting that the voltage applied to the VCC pin has passed through Vdet with the DF0 to DF1 bits in the D4INT register. Table 5.2 Voltage Detection Interrupt Request Generation Conditions
Operation mode Normal operation mode1 VC27 bit 1 D40 bit 1 D41 bit 0 or 1 D42 bit 0 D46 bit 0 VC13 bit From 0 to 12 From 1 to 02 From 0 to 12 From 1 to 02 0 CM14 bit
Wait mode
1
1
0 or 1
0
0
0
Notes: 1. The status except the wait mode and stop mode is handled as the normal mode. (Refer to Chapter 6, "Clock Generation Circuit.") 2. Refer to Figure 5.14, "Operation Example of Voltage Detection Interrupt Generation Circuit" for interrupt generation timing.
Rev.0.91
2003 Sep 08
page 25 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5.4 Voltage Detection Circuit
Voltage detection circuit
Voltage detection interrupt generation circuit DF1 to DF0
=002 =012 =102 D42 bit is set to "0"(not detected) by writing a "0" in a program. When VC27 bit is set to "0" ( voltage detection circuit disabled), D42 bit is set to "0" . Watchdog timer interrupt signal
VC27 fRING-S
VC13 VCC1 VREF + Noise canceller (Canceller width: 200 ns) 1/2 1/2 1/2
=112
Voltage detection signal
Noise rejection circuit
Digital filter
D42
Voltage detection interrupt signal
Voltage detection signal is "H" when VC27 bit= 0 (disabled)
D41
Oscillation stop detection interrupt signal
Non-maskable interrupt signal
CM10
Watchdog timer block
D43 D47
Watchdog timer underflow signal
D40
Hardware reset 2
D46
This bit is set to "0"(not detected) by writing a "0" in a program.
D40, D41, D42, D43, DF0, DF1, D46, D47: Bits in D4INT register VC13: Bit in VCR1 register VC27: Bit in VCR2 register
CM02: Bit in CM0 register CM10: Bit in CM1 register
Figure 5.13 Operation Detection Interrupt Generation Block
VCC
VC13 bit
sampling
sampling
sampling
sampling
No voltage detection interrupt signals are generated when D42 bit is "H". Output of digital filter2 D42 bit Set D42 bit to "0" in a program (not detected) Voltage detection interrupt signal Notes: 1. D40 is "1"(voltage detection interrupt enabled). 2. Output of the digital filter shown in Figure 5.11 Set D42 bit to "0" in a program (not detected)
D42: Bit in D4INT register VC13: Bit in VCR1 register
Figure 5.14 Voltage Detection Interrupt Generation Circuit Operation Example
Rev.0.91
2003 Sep 08
page 26 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5.4 Voltage Detection Circuit
5.4.2 Exiting Stop Mode on a Voltage Detection Interrupt A voltage detection interrupt is generated when the input voltage at the VCC pin rises to Vdet or more or drops below Vdet if all of the following conditions hold true in stop mode. * The VC27 bit in the VCR2 register is set to "1" (voltage detection circuit enabled) * The D40 bit in the D4INT register is set to "1" (voltage detection interrupt enabled) * The D41 bit in the D4INT register is set "1" (voltage detection used to get out of stop mode) * The D46 bit in the D4INT register is set "0" (voltage detection interrupt selected) To use the voltage detection interrupt , set the CM14 bit in the CM1 register to "0" (low-ring oscillator). The voltage detection interrupt shares the interrupt vector with the watchdog timer interrupt and oscillation stop detection interrupt. The D42 bit in the D4INT register becomes "1" when passing through Vdet is detected after the voltage inputted to the VCC pin is up or down. A voltage detection interrupt request is generated when the D42 bit changes state from "0" to "1". The D42 bit needs to be set to "0" in a program. Table 5.3 lists the voltage detection interrupt request generation conditions in use to get out of stop mode. Table 5.3 Voltage Detection Interrupt Request Generation Conditions in use to get out of stop mode
Operation mode Stop mode VC27 bit 1 D40 bit 1 D41 bit 1 D42 bit 1 D46 bit 0 D47 bit 0 or 1 VC13 bit From 0 to 1 0 From 1 to 0 CM14 bit
Notes: 1. The status except the wait mode and stop mode is handled as the normal mode. (Refer to Chapter 6, "Clock Generation Circuit.") 2. Refer to Figure 5.14, "Operation Example of Voltage Detection Interrupt Generation Circuit" for interrupt generation timing.
Rev.0.91
2003 Sep 08
page 27 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
6. Clock Generating Circuit
6. Clock Generation Circuit
The clock generation circuit contains two oscillator circuits as follows: * Main clock oscillation circuit * Ring oscillator (oscillation stop detect function) Table 6.1 lists the clock generation circuit specifications. Figure 6.1 shows the clock generation circuit. Figures 6.2 and 6.4 show the clock-related registers. Table 6.1 Clock Generation Circuit Specifications
Item Use of clock Main clock oscillation circuit * CPU clock source * Peripheral function clock source Ring oscillator Low-speed ring oscillator High-speed ring oscillator * CPU clock source * CPU clock source * Peripheral function clock source * Peripheral function clock source * CPU and peripheral function * CPU and peripheral function clock sources when the main clock sources when the main clock stops oscillating clock stops oscillating Approx. 8 MHz Approx. 125 kHz
Clock frequency Usable oscillator Pins to connect oscillator Oscillation stop, restart function Oscillator status after reset Other
0 to 20 MHz * Ceramic oscillator * Crystal oscillator XIN, XOUT 1
Note 1
Note 1
Present Stopped Externally derived clock can be input
Present Stopped
Present Oscillating
Notes: 1. Can be used as P4 6 and P47 when the ring oscillator clock is used for CPU clock while the main clock oscillation circuit is not used.
Rev.0.91
2003 Sep 08
page 28 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
6. Clock Generating Circuit
fRING-fast
HR00
High-speed ring oscillator HR01=1 HR01=0
Ring oscillator clock fRING fRING128
CM14
Low-speed ring oscillator
1/128 fRING-S f1 f1SIO fAD f2 Oscillation stop detection f8 f8SIO f32 OCD2=1
Voltage detection circuit
Peripheral function clock
Main clock
e a
b
c d
f32SIO
CM10=1(Stop mode)
SQ R XOUT OCD2=0
Divider
XIN
CPU clock
RESET Hardware reset2 Power on reset Interrupt request level judgment output Voltage detective interrupt SQ R WAIT instruction R CM13 CM05
CM02
e a
1/2 1/2 1/2
b
1/2 1/2
c c
CM06=0 CM17 to CM16=112 CM06=1
CM06=0 CM17 to CM16=102 CM06=0 CM17 to CM16=012 CM06=0 CM17 to CM16=002
d
CM02, CM05, CM06: Bits in CM0 CM10, CM13, CM14, CM16, CM17: Bits in CM1 register OCD0, OCD1, OCD2: Bits in OCD register HR00, HR01: Bits in HR0 register
Details of divider
Oscillation stop detection circuit
Forcible discharge when OCD01 Pulse generation circuit for clock edge detection and charge, discharge control circuit
Main clock
Charge, discharge circuit OCD11
Oscillation stop detection interrupt generation circuit Watchdog timer interrupt OCD2 bit switch signal CM14 bit switch signal
Oscillation stop detection, watchdog timer, Voltage detection interrupt
Notes: 1. Set the same value to the OCD1 bit and OCD0 bit.
Figure 6.1 Clock Generation Circuit
Rev.0.91
2003 Sep 08
page 29 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
6. Clock Generating Circuit
System clock control register 01
b7 b6 b5 b4 b3 b2 b1 b0
0
01
00
Symbol CM0 Bit symbol
(b1-b0) CM02 (b3) (b4) CM05 CM06 (b7)
Address 000616 Bit name
Reserved bit WAIT peripheral function clock stop bit Reserved bit Reserved bit Main clock (XCIN-XCOUT) stop bit 2, 4 Main clock division select bit 05 Reserved bit
After reset 6816 Function
Must set to "0" 0 : Do not stop peripheral function clock in wait mode 6 1 : Stop peripheral function clock in wait mode Must set to "1" Must set to "0" 0 : On 1 : Off 3 0 : CM16 and CM17 valid 1 : Divide-by-8 mode Must set to "0"
RW RW RW RW RW RW RW RW
Notes 1: Set the PRC0 bit of PRCR register to "1" (write enable) before writing to this register. 2: The CM05 bit is provided to stop the main clock when the ring oscillator mode is selected. This bit cannot be used for detection as to whether the main clock stopped or not. To stop the main clock, the following setting is required: (1) Set the CM06 bit to "1" (divide-by-8 mode) (2) Set the OCD0 and OCD1 bits in the OCD register to "00 2" (disabling oscillation stop detection function). (3) Set the OCD2 bit to "1" (selecting ring oscillator). 3: During external clock input, only the clock oscillation buffer is turned off and clock input is accepted. 4: When the CM05 bit is set to "1" (main clock stop), P4 6 and P47 can be used as input ports. 5: When entering stop mode from high or middle speed mode, the CM06 bit is set to "1" (divide-by-8 mode). 6: During ring oscillator mode, this bit must be set to "0" (peripheral clock turned on when in wait mode).
System clock control register 11
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol CM1 Bit symbol
CM10 (b1) (b2) CM13 CM14 CM15 CM16 CM17
Address 000716 Bit name
All clock stop control bit 4 Reserved bit Reserved bit Port XIN-XOUT switch bit Low-speed ring oscillation stop bit 5,6 XIN-XOUT drive capability select bit 2 Main clock division select bit 1 3
After reset 2016 Function
0 : Clock on 1 : All clocks off (stop mode) Must set to "0" Must set to "0" 0 : Input port P46, P47 1 : XIN-XOUT pin 0 : Low-speed ring oscillator on 1 : Low-speed ring oscillator off 0 : LOW 1 : HIGH
b7 b6
RW RW RW RW RW RW RW RW RW
0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode
Notes: 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable). 2: When entering stop mode from high or middle speed mode, the CM15 bit is set to "1" (drive capability high). 3: Effective when the CM06 bit is "0" (CM16 and CM17 bits enable). 4: If the CM10 bit is "1" (stop mode), the internal feedback resistor becomes ineffective. 5: The CM14 bit can be set to "1" (low-speed ring oscillator off) if the OCD2 bit=0 (selecting main clock). When the OCD2 bit is set to "1" (selecting ring oscillator clock), the CM14 bit is set to "0" (low-speed ring oscillator on). This bit remains unchanged when " 1" is written. 6: When using voltage detection interrupt circuit, CM14 bit is set to "0"
Figure 6.2 CM0 Register and CM1 Register
Rev.0.91
2003 Sep 08
page 30 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
6. Clock Generating Circuit
Oscillation stop detection register1
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol OCD Bit symbol
OCD0 OCD1 OCD2 OCD3 (b7-b4)
Address 000C16 Bit name
Oscillation stop detection enable bit
After reset 0416 Function
b1 b0
RW RW
0 0: The function is disabled 4 0 1: Avoid this setting 1 0: Avoid this setting 1 1: The function is enabled 7 0: Select main clock 7 1: Select ring oscillator clock 2 0: Main clock on 1: Main clock off Must set to "0"
System clock select bit 6 Clock monitor bit 3, 5 Reserved bit
RW RO RW
Notes: 1. Set the PRC0 bit in the PRCR register to "1" (write enable) before rewriting this register. 2. The OCD2 bit is set to "1" (selecting ring oscillator clock) automatically if a main clock oscillation stop is detected while the OCD1 to OCD0 bits are set to "11 2" (oscillation stop detection function enabled). If the OCD3 bit is set to "1" (main clock stop), the OCD2 bit remains unchanged when trying to write "0" (selecting main clock). 3. The OCD3 bit is enabled when the OCD1 to OCD0 bits are set to "11 2" (oscillation stop detection function enabled). Read the OCD3 bit several times with the oscillation stop detection interrupt processing program to determine the main clock state. 4. The OCD1 to OCD0 bits should be set to "00 2" (oscillation stop detection function disabled)before entering stop mode and ring oscillator (main clock stops). The OCD1 to OCD0 bits should be set to "00 2" when the HR01 bit in the HR0 register is set to "1" (high-speed ring oscillator selected). 5. The OCD3 bit remains set to "0" (main clock on) if the OCD1 to OCD0 bits are set to "00 2". 6. The CM14 bit goes to "0" (low-speed ring oscillator on) if the OCD2 bit is set to "1" (selecting ring oscillator clock). 7. Refer to Figure 6.9 "switching clock source from low-speed ring oscillator to main clock" for the switching procedure when the main clock re-oscillates after detecting an oscillation stop.
Figure 6.3 OCD Register
Rev.0.91
2003 Sep 08
page 31 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
6. Clock Generating Circuit
High-speed ring control register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
00
0
0
Symbol HR0 Bit symbol
HR00 HR01
Address 000816
After reset 0016 RW RW RW
Bit Function name enable bit 0: High-speed ring oscillator off High-speed ring
1: High-speed ring oscillator on High-speed ring select bit1,2 0: Low-speed ring oscillator selected 1: High-speed ring oscillator selected
Reserved bit Should set to "0" RW (b7-b2) Notes: 1. The HR01 bit should be changed under the following conditions. * HR00 = 1 (high-speed ring oscillator on) * CM1 register CM14 bit = 0 (low-speed ring oscillator on) * CM0 register CM06 bit = 1 (divided-by-8 mode) 2. When OCD1 to OCD0 bits in the OCD register are set to "112"(the function is enabled), the HR01 bit should be set to "0".
High-speed ring control register 11
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol HR1
Address 000B16
After reset 4016 Function RW RW
The frequency of high-speed ring oscillator is adjusted with bits 0 to bits 6. Period of high-speed ring oscillator = td(HR offset) + (b6 + b5/2 + b4/4 + b3/8 + b2/16 + b1/32 + b0/64) x td(HR) Bit 7 should be set to "0". Note: 1. Set the PRC0 bit in the PRCR register to "1" (write enable) before rewriting this register.
Figure 6.4 HR0 Register and HR1 Register
Rev.0.91
2003 Sep 08
page 32 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
6.1 Main Clock
The following describes the clocks generated by the clock generation circuit. 6.1 Main Clock This clock is supplied by a main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. The main clock oscillator circuit may also be configured by feeding an externally generated clock to the XIN pin. Figure 6.5 shows examples of main clock connection circuit. After reset, the main clock is turned off. The main clock starts oscillating when the CM05 bit in the CM0 register is set to "0" (main clock on) after setting the CM13 bit in the CM1 register to "1" (XIN- XOUT pin). To use the main clock for the CPU clock, set the OCD2 bit in the OCD register to "0" (selecting main clock) after the main clock becomes oscillating stably. The power consumption can be reduced by setting the CM05 bit in the CM0 register to "1" (main clock off) if the OCD2 bit is set to "1" (selecting ring oscillator clock). Note that if an externally generated clock is fed into the XIN pin, the main clock cannot be turned off by setting the CM05 bit to "1". If necessary, use an external circuit to turn off the clock. During stop mode, all clocks including the main clock are turned off. Refer to Section 6.4, "Power Control."
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
XIN
XOUT (Note) Rd
XIN
XOUT Open
Externally derived clock CIN COUT Vcc Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN and XOUT following the instruction.
Figure 6.5 Examples of Main Clock Connection Circuit
Rev.0.91
2003 Sep 08
page 33 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
6.2 Ring Oscillator Clock
6.2 Ring Oscillator Clock This clock is supplied by a ring oscillator. There are two kinds of ring oscillator: high-speed ring oscillator and low-speed ring oscillator. These oscillators are selected by the bit HR01 bit in the HR0 register. 6.2.1 Low-speed Ring Oscillator The clock derived from the low-speed ring oscillator is used as the clock source for the CPU clock, peripheral function clock, fRING, fRING128 and fRING-S. After reset, the ring oscillator clock derived from low-speed ring oscillator by divided by 8 is selected for the CPU clock. If the main clock stops oscillating when the OCD1 to OCD0 bits in the OCD register are "112" (oscillation stop detection function enabled), the low-speed ring oscillator automatically starts operating, supplying the necessary clock for the microcomputer. The frequency of the low-speed ring oscillator varies depending on the supply voltage and the operation ambient temperature. The application products must be designed with sufficient margin to accommodate the frequency range. 6.2.2 High-speed Ring Oscillator The clock derived from high-speed ring oscillator is used as the clock source for the CPU clock, peripheral function clock, fRING, fRING128, and fRING1-fast. After reset, the ring oscillator clock derived from high-speed ring oscillator is halted. The oscillation is started by setting the HR00 bit in the HR0 register to "1" (high-speed ring oscillator on). The frequency can be adjusted by the HR1 register. The relationship between the value of HR1 register and the period of high-speed ring oscillator is shown below. It is noted that the difference in delay between the bits should be adjusted by changing each bit. Bit 7 should be set be "0". Period of high-speed ring oscillator = td(HR offset) + (b6 + b5/2 + b4/4 + b3/8 + b2/16 + b1/32 + b0/64) b0 to b6 : Bits in HR1 register
Rev.0.91
2003 Sep 08
page 34 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
6.3 CPU Clock and Peripheral Function Clock
6.3 CPU Clock and Peripheral Function Clock
There are two type clocks: CPU clock to operate the CPU and peripheral function clock to operate the peripheral functions. Also refer to "Figure 6.1 Clock Generating Circuit". 6.3.1 CPU Clock This is an operating clock for the CPU and watchdog timer. The clock source for the CPU clock can be chosen to be the main clock or ring oscillator clock. The selected clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to select the divideby-n value. After reset, the ring oscillator clock divided by 8 provides the CPU clock. When the clock source for the CPU clock is switched over, set the CM06 bit to "1" (divide-by-8 mode) before changing the OCD2 bit. Note that when entering stop mode from high or middle speed mode, the CM06 bit is set to "1" (divideby-8 mode). 6.3.2 Peripheral Function Clock (f1, f2, f8, f32, fAD, f1SIO, f8SIO, f32SIO, fRING, fRING128) These are operating clocks for the peripheral functions. Of these, fi (i=1, 2, 8, 32) is derived from the main clock or ring oscillator clock by dividing them by i. The clock fi is used for timers X, Y, Z and C. The clock fjSIO (j=1, 8, 32) is derived from the main clock or ring oscillator clock by dividing them by j. The clock fjSIO is used for serial I/O. The fAD clock is produced from the main clock or the ring oscillator clock and is used for the A-D converter. When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to "1" (peripheral function clock turned off during wait mode), the clocks fi, fjSIO, and fAD are turned off. 6.3.3 fRING and fRING128 These are operating clocks for the peripheral functions. The fRING runs at the same frequency as the ring oscillator, and can be used as the souce for the timer Y. The fRING128 is derived from the fRING by dividing it by 128, and can be used for the timer C input capture function. When the WAIT instruction is executed, the clocks fRING and fRING128 are not turned off. 6.3.4 fRING-fast This is used as the count source for the timer C. The fRING-fast is derived from the high-speed ring oscillator and provided by setting the HR00 bit to "1" (high-speed ring oscillator on). When the WAIT instruction is executed, the clock fRING-fast is not turned off.
Rev.0.91
2003 Sep 08
page 35 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
6.4 Power Control
6.4 Power Control
There are three power control modes. For convenience' sake, all modes other than wait and stop modes are referred to as normal operation mode here. 6.4.1 Normal Operation Mode Normal operation mode is further classified into three modes. In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are turned off, the power consumption is further reduced. Before the clock sources for the CPU clock can be switched over, the new clock source to which switched must be oscillating stably. If the new clock source is the main clock, allow a sufficient wait time in a program until it becomes oscillating stably. * High-speed Mode The main clock divided by 1 (undivided) provides the CPU clock. If the CM14 bit is set to "0" (lowspeed ring oscillator on) or the HR00 bit in the HR0 register is set to "1" (high-speed ring oscillator on), the fRING and fRING128 can be used for timers Y and C. When the HR00 bit is set to "1", fRING-fast can be used for timer C. * Medium-speed Mode The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the CM14 bit is set to "0" (lowspeed ring oscillator on) or the HR00 bit in the HR0 register is set to "1" (high-speed ring oscillator on), the fRING and fRING128 can be used for timers Y and C. When the HR00 bit is set to "1", fRING-fast can be used for timer C. * Ring Oscillator Mode The ring oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The ring oscillator clock is also the clock source for the peripheral function clocks. Set the CM06 bit to "1" (divided by 8 mode) when returning to high-speed and medium-speed. When the HR00 bit is set to "1", fRING-fast can be used for timer C.
Rev.0.91
2003 Sep 08
page 36 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
6.4 Power Control
Table 6.2 Setting Clock Related Bit and Modes
Modes High-speed mode Mediumdivided by 2 speed divided by 4 mode divided by 8 divided by 16 Ring oscillator mode1 no division divided by 2 divided by 4 divided by 8 divided by 16 OCD register OCD2 0 0 0 0 0 1 1 1 1 1 CM1 register CM17, CM16 002 012 102 112 002 012 102 112 CM0 register CM06 CM05 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1
Notes: 1. The low-speed ring oscillator is used as the ring oscillator clock when the CM1 register CM14 bit=0 (low-speed ring oscillator on) and HR0 register HR01 bit=0 (low-speed ring oscillator selected). The high-speed ring oscillator is used as the ring oscillator clock when the HR0 register HR00 bit=1 (highspeed ring oscillator on) and HR01 bit=1 (high-speed ring oscillator selected).
Rev.0.91
2003 Sep 08
page 37 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
6.4 Power Control
6.4.2 Wait Mode In wait mode, the CPU clock is turned off, so are the CPU and the watchdog timer because both are operated by the CPU clock. Because the main clock and ring oscillator clock both are on, the peripheral functions using these clocks keep operating. * Peripheral Function Clock Stop Function If the CM02 bit is "1" (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO, f8SIO, f32SIO, and fAD clocks are turned off when in wait mode, with the power consumption reduced that much. * Entering Wait Mode The microcomputer is placed into wait mode by executing the WAIT instruction. * Pin Status During Wait Mode The status before wait mode is retained. * Exiting Wait Mode The microcomputer is moved out of wait mode by a hardware reset or peripheral function interrupt. When using a hardware reset to exit wait mode, set the ILVL2 to ILVL0 bits for the peripheral function interrupts to "0002" (interrupts disabled) before executing the WAIT instruction. The peripheral function interrupts are affected by the CM02 bit. If CM02 bit is "0" (peripheral function clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait mode. If CM02 bit is "1" (peripheral function clocks turned off during wait mode), the peripheral functions using the peripheral function clocks stop operating, so that only the peripheral functions clocked by external signals can be used to exit from wait mode. Table 6. 3 lists the interrupts to exit wait mode and the usage conditions. When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT instruction. 1. In the ILVL2 to ILVL0 bits in the interrupt control register, set the interrupt priority level of the peripheral function interrupt to be used to exit wait mode. Also, for all of the peripheral function interrupts not used to exit wait mode, set the ILVL2 to ILVL0 bits to "0002" (interrupt disable). 2. Set the I flag to "1". 3. Enable the peripheral function whose interrupt is to be used to exit wait mode. In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an interrupt sequence is executed. The CPU clock turned on when exiting wait mode by a peripheral function interrupt is the same CPU clock that was on when the WAIT instruction was executed. Table 6.3 Interrupts to Exit Wait Mode and Usage Conditions
Interrupt Serial I/O interrupt CM02=0 Can be used when operating with internal or external clock CM02=1 Can be used when operating with external clock Can be used (Do not use) Can be used in event counter mode Can be used when counting inputs from CNTR1 pin in timer mode Can be used (INT0 and INT3 can be used if there is no filter. Can be used
Key input interrupt Can be used A-D conversion interrupt Can be used in one-shot mode Timer X interrupt Timer Y interrupt INT interrupt Can be used in all modes Can be used in all modes Can be used
Voltage detection interrupt Can be used
Rev.0.91
2003 Sep 08
page 38 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
6.4 Power Control
6.4.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of power is consumed in this mode. If the voltage applied to Vcc pin is VRAM or more, the internal RAM is retained. However, the peripheral functions clocked by external signals keep operating. The following interrupts can be used to exit stop mode. * Key interrupt ______ ______ ______ * INT interrupt (INT0 and INT3 can be used only when there is no filter.) * Timer X interrupt (when counting external pulses in event counter mode) * Timer Y interrupt (when counting inputs from CNTR1 pin in timer mode) * Serial I/O interrupt (when external clock is selected) * Voltage detection interrupt * Entering Stop Mode The microcomputer is placed into stop mode by setting the CM10 bit of CM1 register to "1" (all clocks turned off). At the same time, the CM06 bit of CM0 register is set to "1" (divide-by-8 mode) and the CM15 bit of CM10 register is set to "1" (main clock oscillator circuit drive capability high). Before entering stop mode, set the OCD1 to OCD0 bits to "002" (oscillation stop detection function disable). * Pin Status in Stop Mode The status before wait mode is retained. * Exiting Stop Mode The microcomputer is moved out of stop mode by a hardware reset or peripheral function interrupt. When using a hardware reset to exit stop mode, set the ILVL2 to ILVL0 bits for the peripheral function interrupts to "0002" (interrupts disabled) before setting the CM10 bit to "1". When using a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit to "1". 1. In the ILVL2 to ILVL0 bits in the interrupt control register, set the interrupt priority level of the peripheral function interrupt to be used to exit stop mode. Also, for all of the peripheral function interrupts not used to exit stop mode, set the ILVL2 to ILVL0 bits to "0002". 2. Set the I flag to "1". 3. Enable the peripheral function whose interrupt is to be used to exit stop mode. In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an interrupt sequence is executed. The main clock divided by 8 of the clock which is used right before stop mode is used for the CPU clock when exiting stop mode by a peripheral function interrupt.
Rev.0.91
2003 Sep 08
page 39 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
6.4 Power Control
Figure 6.6 shows the state transition from normal operation mode to stop mode and wait mode. Figure 6.7 shows the state transition in normal operation mode.
Reset
CPU operation stopped
All oscillators stopped
CM10=1
WAIT instruction
Stop mode
Interrupt
er Int ru pt
Ring oscillator mode (divided-by-8 mode)
Wait mode
Interrupt WAIT instruction
CPU operation stopped
All oscillators stopped
Stop mode
CM10=1
Ring oscillator mode
Wait mode
Interrupt
All oscillators stopped
CM10=1 Interrupt
er Int ru pt
When detecting an oscillation stop
WAIT instruction Interrupt
CPU operation stopped
Stop mode
Medium-speed mode (divided-by-8 mode)
When detecting an oscillation stop
Wait mode
CPU operation stopped
All oscillators stopped
Stop mode
CM10=1
High-speed mode, medium-speed mode
WAIT instruction Interrupt
Wait mode
Normal mode
(Refer to the diagram of state transition in normal mode for details.) CM10: Bit in CM1 register
Figure 6.6 State Transition to Stop Mode and Wait Mode
Rev.0.91
2003 Sep 08
page 40 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
6.4 Power Control
Normal operation mode (Main clock is oscillating, ring oscillator 3 is oscillating) Medium-speed mode (divided-by-8 mode)
CPU clock: f(XIN)/8 CM06=1 CM06=1 CM06=0 1, 2 OCD2=1 OCD2=0 1
Ring oscillator mode (main clock is oscillating, ring oscillator 3 is oscillating) 8-division mode
CPU clock: f(RING)/8 CM06=1 CM06=0 1, 2
CM06=1
High-speed mode
CPU clock: f(XIN) CM06=0 CM17 to CM16=00 2
Medium-speed mode (divided-by-2 mode)
CPU clock: f(XIN)/2 CM06=0 CM17 to CM16=01 2
1-division mode 2
CPU clock: f(RING) CM06=0 CM17 to CM16=00 2
2-division mode 2
CPU clock: f(RING)/2 CM06=0 CM17 to CM16=012
Medium-speed mode (divided-by-4 mode)
CPU clock: f(XIN)/4 CM06=0 CM17 to CM16=102
Medium-speed mode (divided-by-16 mode)
CPU clock: f(XIN)/16 CM06=0 CM17 to CM16=112
4-division mode 2
CPU clock: f(RING)/4 CM06=0 CM17 to CM16=10 2
16-division mode 2
CPU clock: f(RING)/16 CM06=0 CM17 to CM16=11 2
Normal operation mode (main clock is oscillating, ring oscillator is stopped)
CM14=0
CM14=1
Ring oscillator mode (main clock is stopped, ring oscillator is oscillating) 3 CM05=0
CM05=1
Medium-speed mode (divided-by-8 mode)
CPU clock: f(XIN)/8 CM06=1
8-division mode
CPU clock: f(RING)/8 CM06=1
High-speed mode
CPU clock: f(XIN) CM06=0 CM17 to CM16=00 2
Medium-speed mode (divided-by-2 mode)
CPU clock: f(XIN)/2 CM06=0 CM17 to CM16=01 2
1-division mode 2
CPU clock: f(RING) CM06=0 CM17 to CM16=00 2
2-division mode 2
CPU clock: f(RING)/2 CM06=0 CM17 to CM16=01 2
Medium-speed mode (divided-by-4 mode)
CPU clock: f(XIN)/4 CM06=0 CM17 to CM16=10 2
Medium-speed mode (divided-by-16 mode)
CPU clock: f(XIN)/16 CM06=0 CM17 to CM16=11 2
4-division mode 2
CPU clock: f(RING)/4 CM06=0 CM17 to CM16=10 2
16-division mode 2
CPU clock: f(RING)/16 CM06=0 CM17 to CM16=112
Notes: 1. Switch clock after oscillation of main clock is sufficiently stable. 2. Change the CM17 to CM16 bits before changing CM06 bit. 3. Ring oscillator is selected by the HR01 bit in the HR0 register.
CM05, CM06: Bits in CM0 register CM14, CM16, CM17: Bits in CM1 register OCD2: Bit in OCD register
Figure 6.7 State Transition in Normal Operation Mode
Rev.0.91
2003 Sep 08
page 41 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
6.5 Oscillation Stop Detection Function
6.5 Oscillation Stop Detection Function
The oscillation stop detection function is such that main clock oscillation circuit stop is detected. The oscillation stop detection function can be enabled and disabled by the OCD1 to OCD0 bits in the OCD register. Table 6.4 lists the specifications of the oscillation stop detection function. Where the main clock corresponds to the CPU clock source and the OCD1 to OCD0 bits are "112" (oscillation stop detection function enabled), the system is placed in the following state if the main clock comes to a halt: * The low-speed ring oscillator starts oscillation, and the low-speed ring oscillator clock becomes the clock source for CPU clock and peripheral functions in place of the main clock * OCD register OCD2 bit = 1 (selecting ring oscillator clock) * OCD register OCD3 bit = 1 (main clock stopped) * CM1 register CM14 bit = 0 (low-speed ring oscillator oscillating) * Oscillation stop detection interrupt request occurs Table 6.4 Oscillation Stop Detection Function Specifications Item Specification Oscillation stop detectable clock and frequency bandwidth Enabling condition for oscillation stop detection function f(XIN) 2 MHz * Set OCD1 to OCD0 bits to "112" (oscillation stop detection function enabled) * Set HR01 bit in HR0 register to "0" (low-speed ring oscillator selected) Operation at oscillation stop detection Oscillation stop detection interrupt occurs
6.5.1 How to Use Oscillation Stop Detection Function * The oscillation stop detection interrupt shares the vector with the watchdog timer interrupt. If the oscillation stop detection and watchdog timer interrupts both are used, the interrupt source must be determined. Figure 6.5 shows how to determine the interrupt source with the oscillation stop detection interrupt processing program. * Where the main clock re-oscillated after oscillation stop, the clock source for the CPU clock and peripheral functions must be switched to the main clock in the program. Figure 6.8 shows the procedure for switching the clock source from the low-speed ring oscillator to the main clock. * To enter wait mode while using the oscillation stop detection function, set the CM02 bit to "0" (peripheral function clocks not turned off during wait mode). * Since the oscillation stop detection function is provided in preparation for main clock stop due to external factors, set the OCD1 to OCD0 bits to "002" (oscillation stop detection function disabled) where the main clock is stopped or oscillated in the program, that is where the stop mode is selected or the CM05 bit is altered. * This function cannot be used if the main clock frequency is 2 MHz or less. In that case, set the OCD1 to OCD0 bits to "002" (oscillation stop detection function disabled). * The HR01 bit in the HR0 register should be set to "0" (low-speed ring oscillator selected) before setting the OCD1 to OCD0 bits to "112" (oscillation stop detection function enabled). When the HR01 bit is set to "1" (high-speed ring oscillator selected), the OCD1 to OCD0 bits should be set to "002" (oscillation stop detection function disabled).
Rev.0.91 2003 Sep 08 page 42 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
6.5 Oscillation Stop Detection Function
Table 6.5 Determination of Interrupt Source (Oscillation Stop Detection or Watchdog Timer Interrupt) Generated Interrupt Source Oscillation stop detection ( (a) or (b) ) Watchdog timer Voltage detection Bit showing interrupt source (a) The OCD3 bit in the OCD register = 1 (b) The OCD1 to OCD0 bits in the OCD register = 112 and the OCD2 bit = 1 The D43 bit in the D4INT register = 1 The D42 bit in the D4INT register = 1
Switch to Main clock
Verify OCD3 bit
1(main clock stop)
0(main clock oscillating) Determine several times Determine several times that the main clock is supplied Set OCD1 to OCD0 bits to 002 (oscillation stop detection function disabled)
Set OCD2 bit to 0 (selecting main clock)
End OCD3 to OCD0 bits: Bits in OCD register
Figure 6.8 Switching Clock Source From Low-speed Ring Oscillator to Main Clock
Rev.0.91
2003 Sep 08
page 43 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
7. Protection
7. Protection
In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 7.1 shows the PRCR register. The following lists the registers protected by the PRCR register. * Registers protected by PRC0 bit: CM0, CM1, and OCD, HR0, HR1 registers * Registers protected by PRC1 bit: PM0 and PM1 registers * Registers protected by PRC2 bit: PD0 register * Registers protected by PRC3 bit: VCR2 and D4INT registers Set the PRC2 bit to "1" (write enabled) and then write to any address, and the PRC2 bit will be set to "0" (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to "1". Make sure no interrupts will occur between the instruction in which the PRC2 bit is set to "1" and the next instruction. The PRC0 and PRC1 bits are not automatically set to "0" by writing to any address. They can only be set to "0" in a program.
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol PRCR Bit symbol
PRC0
Address 000A16 Bit name
Protect bit 0
After reset 00XXX0002 Function
Enable write to CM0, CM1, OCD, HR0, HR1 registers 0 : Write protected 1 : Write enabled Enable write to PM0, PM1 registers 0 : Write protected 1 : Write enabled Enable write to PD0 register
RW
RW
PRC1
Protect bit 1
RW
PRC2
Protect bit 2 0 : Write protected 1 : Write enabled 1 Enable write to VCR2, D4INT registers 0 : Write protected 1 : Write enabled When write, should set to "0"
RW
PRC3
Protect bit 3
RW
(b5-b4) (b7-b6)
Reserved bit Reserved bit
RW
When read, its content is "0". RO Notes: 1. The PRC2 bit is set to "0" by writing to any address after setting it to "1". Other bits are not set to "0" by writing to any address, and must therefore be set to "0" in a program.
Figure 7.1 PRCR Register
Rev.0.91
2003 Sep 08
page 44 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
8. Processor Mode
8. Processor Mode
8.1 Types of Processor Mode
The processor mode is single-chip mode. Table 8.1 shows the features of the processor mode. Figure 8.1 shows the PM0 and PM1 register.
Table 8.1 Features of Processor Mode
Processor mode Single-chip mode Access space SFR, internal RAM, internal ROM Pins which are assigned I/O ports All pins are I/O ports or peripheral function I/O pins
Processor mode register 01
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol PM0
Address 000416
After reset 0016
Bit symbol
(b2-b0) PM03
Bit name
Reserved bit Software reset bit
Function
Must set to "0" Setting this bit to "1" resets the microcomputer. When read, its content is "0".
RW RW RW
(b7-b4)
Nothing is assigned. When write, set to "0". When read, its content is "0".
Notes: 1. Set the PRC1 bit in the PRCR register to "1" (write enable) before writing to this register.
Processor mode register 11
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
Symbol PM1
Address 000516
After reset 0016
Bit symbol
(b1-b0) PM12
Bit name
Reserved bit
Function
Must set to "0"
RW RW RW
WDT inerrupt/reset switch 0 : Watchdog timer interrupt 1 : Watchdog timer reset2 bit Nothing is assigned. When write, set to "0". When read, its content is "0". Reserved bit Must set to "0"
(b6-b3)
(b7) Notes: 1. Set the PRC1 bit in the PRCR register to "1" (write enable) before writing to this register. 2. PM12 bit is set to "1" by writing a "1" in a program. (Writing a "0" has no effect.)
RW
Figure 8.1 PM0 Register and PM1 Register
Rev.0.91 2003 Sep 08 page 45 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
9. Bus
9. Bus
During access, the ROM/RAM and the SFR have different bus cycles. Table 9.1 shows bus cycles for access space. The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word (16 bits) units, these spaces are accessed twice in 8-bit units. Table 9.2 shows bus cycles in each access space.
Table 9.1 Bus Cycles for Access Space Access space Bus cycle SFR 2 CPU clock cycles ROM/RAM 1 CPU clock cycles
Table 9.2 Access Unit and Bus Operation
Space Even address byte access SFR ROM/RAM
CPU clock
Address Even Data
CPU clock
Address Even Data
Data
Add address byte access
Data CPU clock
CPU clock
Address Odd Data
Address
Odd Data
Data
Even address word access
Data CPU clock
CPU clock
Address Even Data Even+1 Data
Address
Even Data
Even+1 Data
Data
Add address word access
Data CPU clock
CPU clock
Address Odd Data Odd+1 Data
Address
Odd Data
Odd+1 Data
Data
Data
Rev.0.91
2003 Sep 08
page 46 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
10.1 Interrupt Overview
10. Interrupt
10.1 Interrupt Overview
10.1.1 Type of Interrupts Figure 10.1 shows types of interrupts.
Software (Non-maskable interrupt)
Hardware
Watchdog timer Oscillation stop detection Special Voltage detection (Non-maskable interrupt) Single step2 Address match Peripheral function1 (Maskable interrupt)
Notes: 1. Peripheral function interrupts are generated by the peripheral functions built in the microcomputer system. 2. Avoid using this interrupt because this is a dedicated interrupt for development support tools only. Figure 10.1 Interrupts
* Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. * Non-maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level.
Rev.0.91
2003 Sep 08
page 47 of 184

Interrupt

Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction

Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
10.1 Interrupt Overview
10.1.2 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are nonmaskable interrupts. * Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. * Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag set to "1" (the operation resulted in an overflow). The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB * BRK Interrupt A BRK interrupt occurs when executing the BRK instruction. * INT Instruction Interrupt An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63 can be specified for the INT instruction. Because software interrupt Nos. 4 to 31 are assigned to peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the INT instruction. In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is cleared to "0" (ISP selected) before executing an interrupt sequence. The U flag is restored from the stack when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not change state during instruction execution, and the SP then selected is used.
Rev.0.91
2003 Sep 08
page 48 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
10.1 Interrupt Overview
10.1.3 Hardware Interrupts Hardware interrupts are classified into two types -- special interrupts and peripheral function interrupts. (1) Special Interrupts Special interrupts are non-maskable interrupts. * Watchdog Timer Interrupt Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize the watchdog timer. For details about the watchdog timer, refer to Chapter 11, "Watchdog Timer." * Oscillation Stop Detection Interrupt Generated by the oscillation stop detection function. For details about the oscillation stop detection function, refer to Chapter 6, "Clock Generation Circuit." * Voltage Detection Interrupt Generated by the voltage detection circuit. For details about the voltage detection circuit, refer to Section 5.2, "Voltage Detection Circuit." * Single-step Interrupt Do not normally use this interrupt because it is provided exclusively for use by development support tools. * Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMAD0 to RMAD1 register that corresponds to one of the AIER register's AIER0 or AIER1 bit which is "1" (address match interrupt enabled). For details about the address match interrupt, refer to Section 10.4, "Address Match Interrupt." (2) Peripheral Function Interrupts Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal functions. The interrupt sources for peripheral function interrupts are listed in Table 10.2. "Relocatable Vector Tables". For details about the peripheral functions, refer to the description of each peripheral function in this manual.
Rev.0.91
2003 Sep 08
page 49 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
10.1 Interrupt Overview
10.1.4 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector. Figure 10.2 shows the interrupt vector.
MSB
LSB Low address Mid address 0000 High address 0000
Vector address (L)
Vector address (H)
0000
Figure 10.2 Interrupt Vector * Fixed Vector Tables The fixed vector tables are allocated to the addresses from 0FFDC16 to 0FFFF16. Table 10.1 lists the fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed vectors are used by the ID code check function. For details, refer to Section 17.3, "Functions to Prevent Flash Memory from Rewriting." Table 10.1 Fixed Vector Tables Vector addresses Remarks Reference Address (L) to address (H) Undefined instruction 0FFDC16 to 0FFDF16 Interrupt on UND instruction R8C series software Overflow 0FFE016 to 0FFE316 Interrupt on INTO instruction manual If the contents of address BRK instruction 0FFE416 to 0FFE716 0FFE716 is FF16, program execution starts from the address shown by the vector in the relocatable vector table. Address match 0FFE816 to 0FFEB16 Address match interrupt 1 Single step 0FFEC16 to 0FFEF16 * Watchdog timer 0FFF016 to 0FFF316 *Watchdog timer * Oscillation stop *Clock generation circuit detection *Voltage detection circuit * Voltage detection (Reserved) 0FFF416 to 0FFF716 (Reserved) 0FFF816 to 0FFFB16 Reset 0FFFC16 to 0FFFF16 Reset Note: Do not normally use this interrupt because it is provided exclusively for use by development support tools. Interrupt source
Rev.0.91
2003 Sep 08
page 50 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
10.1 Interrupt Overview
* Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 10.2 lists interrupts and vector tables located in the relocatable vector table.
Table 10.2 Interrupt and Vector Tables in Relocatable Vector Tables
Interrupt source BRK instruction 2 (Reserved) Key input interrupt A-D (Reserved) Compare 2 UART0 transmit UART0 receive UART1 transmit UART1 receive INT2 Timer X Timer Y Timer Z INT1 INT3 Timer C Compare 1 INT0 (Reserved) (Reserved) Software interrupt 2 +128 to +131 (0080 16 to 008316) to +252 to +255 (00FC 16 to 00FF16) +64 to +67 (0040 16 to 004316) +68 to +71 (0044 16 to 004716) +72 to +75 (0048 16 to 004B16) +76 to +79 (004C 16 to 004F16) +80 to +83 (0050 16 to 005316) +84 to +87 (0054 16 to 005716) +88 to +91 (0058 16 to 005B16) +92 to +95 (005C 16 to 005F16) +96 to +99 (0060 16 to 006316) +100 to +103 (0064 16 to 006716) +104 to +107 (0068 16 to 006B16) +108 to +111 (006C 16 to 006F16) +112 to +115 (0070 16 to 007316) +116 to +119 (0074 16 to 007716) +52 to +55 (0034 16 to 003716) +56 to +59 (0038 16 to 003B16) Vector address 1 Address (L) to address (H) +0 to +3 (0000 16 to 000316) Software interrupt number 0 1 to 12 13 14 15 16 17 18 19 20 21 22 23 24 25 INT interrupt 26 27 28 29 30 31 32 to 63 R8C/Tiny Series software manual Timer C Timer C INT interrupt INT interrupt Timer X Timer Y Timer Z Serial I/O Timer C Reference R8C/Tiny Series software manual Key input interrupt A-D converter
Notes: 1. Address relative to address in INTB. 2. These interrupts cannot be disabled using the I flag.
Rev.0.91
2003 Sep 08
page 51 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
10.1 Interrupt Overview
10.1.5 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use the FLG register's I flag, IPL, and each interrupt control register's ILVL2 to ILVL0 bits to enable/ disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control register. Figure 10.3 shows the interrupt control registers.
Rev.0.91
2003 Sep 08
page 52 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
10.1 Interrupt Overview
Interrupt control register2
Symbol KUPIC ADIC CMP2IC S0TIC, S1TIC S0RIC, S1RIC INT2IC TXIC TYIC TZIC INT1IC INT3IC TCIC CMP1IC Address 004D16 004E16 005016 005116, 005316 005216, 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 After reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002
b7
b6
b5
b4
b3
b2
b1
b0
Bit symbol
ILVL0
Bit name
Interrupt priority level select bit
b2 b1 b0
Function
000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7
RW RW
ILVL1
RW
ILVL2
RW
IR
Interrupt request bit
0 : Interrupt not requested 1 : Interrupt requested
RW1
(b7-b4)
Nothing is assigned. When write, set to "0". When read, its content is indeterminate.
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol INT0IC
Address 005D16
After reset XX00X0002
Bit symbol
ILVL0
Bit name
Interrupt priority level select bit
b2 b1 b0
Function
0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Must always be set to "0"
RW RW
ILVL1
RW
ILVL2
RW
IR
Interrupt request bit Polarity select bit3, 4
RW1
POL
RW RW
Reserved bit
(b7-b6)
Nothing is assigned. When write, set to "0". When read, its content is indeterminate.
Notes: 1. Only "0" can be written to the IR bit. (Do not write "1"). 2. To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. Refer to the paragraph 1.2.6 "Changing Interrupt Control Registers" in the Usage Notes Reference Book. 3. If the INTOPL bit in the INTEN register is set to "1" (both edges), set the POL bit to "0 " (selecting falling edge). 4. The IR bit may be set to "1" (interrupt requested) when the POL bit is rewritten. Refer to the paragraph 1.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book.
Figure 10.3 Interrupt Control Registers
Rev.0.91
2003 Sep 08
page 53 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
10.1 Interrupt Overview
* I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to "1" (enabled) enables the maskable interrupt. Setting the I flag to "0" (disabled) disables all maskable interrupts. * IR Bit The IR bit is set to "1" (interrupt requested) when an interrupt request is generated. Then, when the interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is cleared to "0" (= interrupt not requested). The IR bit can be cleared to "0" in a program. Note that do not write "1" to this bit.
* ILVL2 to ILVL0 Bits and IPL Interrupt priority levels can be set using the ILVL2 to ILVL0 bits. Table 10.3 shows the settings of interrupt priority levels and Table 10.4 shows the interrupt priority levels enabled by the IPL. The following are conditions under which an interrupt is accepted: * I flag = 1 * IR bit = 1 * interrupt priority level > IPL The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one another. Table 10.4 Interrupt Priority Levels Enabled by IPL
IPL 0002 Lowest 0012 0102 0112 1002 1012 1102 Highest 1112 Enabled interrupt priority levels
Table 10.3 Settings of Interrupt Priority Levels
ILVL2 to ILVL0 bits Interrupt priority level Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Priority order
0002 0012 0102 0112 1002 1012 1102 1112
Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled
Rev.0.91
2003 Sep 08
page 54 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
10.1 Interrupt Overview
* Interrupt Sequence An interrupt sequence -- what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed -- is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. The CPU behavior during the interrupt sequence is described below. Figure 10.4 shows time required for executing the interrupt sequence. (1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading the address 0000016. Then it clears the IR bit for the corresponding interrupt to "0" (interrupt not requested). (2) The FLG register immediately before entering the interrupt sequence is saved to the CPU's internal temporary register(Note). (3) The I, D and U flags in the FLG register become as follows: The I flag is cleared to "0" (interrupts disabled). The D flag is cleared to "0" (single-step interrupt disabled). The U flag is cleared to "0" (ISP selected). However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is executed. (4) The CPU's internal temporary register (Note) is saved to the stack. (5) The PC is saved to the stack. (6) The interrupt priority level of the accepted interrupt is set in the IPL. (7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC. After the interrupt sequence is completed, the processor resumes executing instructions from the start address of the interrupt routine. Note: This register cannot be used by user.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CPU clock
Address bus
Address 000016
Indeterminate
SP-2 SP-1 SP-4 SP-2 contents
SP-3
VEC
VEC+1
VEC+2
PC
SP-4 contents SP-3 contents
VEC contents VEC+1 contents VEC+2 contents
Data bus
Interrupt information
Indeterminate SP-1 contents
RD
Indeterminate
WR The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready to accept instructions.
Figure 10.4 Time Required for Executing Interrupt Sequence
Rev.0.91 2003 Sep 08 page 55 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
10.1 Interrupt Overview
* Interrupt Response Time Figure 10.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when the instruction then executing is completed (see #a in Figure 10.5) and a time during which the interrupt sequence is executed (20 cycles, see #b in Figure 10.5).
Interrupt request generated
Interrupt request acknowledged Time
Instruction (a)
Interrupt sequence 20 cycles (b)
Instruction in interrupt routine
Interrupt response time
(a) A time from when an interrupt request is generated till when the instruction then executing is completed. The length of this time varies with the instruction being executed. The DIVX instruction requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register). (b) 21 cycles for address match and single-step interrupts.
Figure 10.5 Interrupt Response Time
* Variation of IPL when Interrupt Request is Accepted When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in Table 10.5 is set in the IPL. Shown in Table 10.5 are the IPL values of software and special interrupts when they are accepted.
Table 10.5 IPL Level That Is Set to IPL When A Software or Special Interrupt Is Accepted Interrupt sources Watchdog timer, oscillation stop detection, voltage detection Software, address match, single-step Level that is set to IPL 7 Not changed
Rev.0.91
2003 Sep 08
page 56 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
10.1 Interrupt Overview
* Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits in the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits in the PC are saved. Figure 10.6 shows the stack status before and after an interrupt request is accepted. The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Address MSB
Stack LSB
Address MSB
Stack LSB [SP] New SP value
m-4 m-3 m-2 m-1 m m+1 Content of previous stack Content of previous stack [SP] SPvalue before interrupt occurs
m-4 m-3 m-2 m-1 m m+1 FLGH
PCL PCM FLGL PCH
Content of previous stack Content of previous stack
Stack status before interrupt request is acknowledged
Stack status after interrupt request is acknowledged
Figure 10.6 Stack Status Before and After Acceptance of Interrupt Request The registers are saved in four steps, 8 bits at a time. Figure 10.7 shows the operation of the saving registers. Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated by the U flag. Otherwise, it is the ISP.
Address
Stack
Sequence in which order registers are saved
[SP] - 5 [SP] - 4 [SP] - 3 [SP] - 2 [SP] - 1 [SP] Finished saving registers in four operations. FLGH PCL PCM FLGL PCH
(3) (4)
Saved, 8 bits at a time
(1) (2)
Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4.
Figure 10.7 Operation of Saving Register
Rev.0.91 2003 Sep 08 page 57 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
10.1 Interrupt Overview
* Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request. Return the other registers saved by a program within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.
* Interrupt Priority If two or more interrupt requests are generated while executing one instruction, the interrupt request that has the highest priority is accepted. For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the highest priority interrupt accepted. The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 10.8 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine.
Reset > WDT/Oscillation stop detection/Voltage detection > Peripheral function > Single step > Address match
Figure 10.8 Hardware Interrupt Priority
Rev.0.91
2003 Sep 08
page 58 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
10.1 Interrupt Overview
* Interrupt Priority Resolution Circuit The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those requested. Figure 10.9 shows the circuit that judges the interrupt priority level.
Priority level of each interrupt Compare 1 INT3 Timer Z Timer X INT0 Timer C INT1 Timer Y UART1 reception UART0 reception Compare 2 A-D conversion INT2 UART1 transmission UART0 transmission Key input IPL
Level 0 (default value)
Highest
Priority of peripheral fucntion interrupts (if priority levels are same)
Lowest
Interrupt request level resolution output signal
I flag Address match1 Watchdog timer Oscillation stop detection Voltage detection Notes: 1. For development support tool only
Interrupt request accepted
Figure 10.9 Interrupts Priority Select Circuit
Rev.0.91
2003 Sep 08
page 59 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
______
R8C/11 Group
10.2 INT Interrupt
______
10.2 INT Interrupt
________
10.2.1 INT0 Interrupt _______ INT0 interrupt is triggered by an INT0 input. When using INT0 interrupts, the INT0EN bit in the INTEN register must be set to "1" (enabling). The edge polarity is selected using the INT0PL bit in the INTEN register and the POL bit in the INT0IC register. The IR bit may be set to "1" (interrupt requested) after changing the INT0PL or POL bit. The IR bit must be set to "0" (interrupt not requested) after changing the INT0PL and POL bits. Inputs can be passed through a digital filter with three different sampling clocks. Figure 10.10 shows the INTEN and INT0F registers.
External input enable register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
0
0
Symbol INTEN
Bit symbol
Address 009616 Bit name
After reset 0016 Function 0 : Disabled 1 : Enabled 0 : One edge 1 : Both edges Must set to "0" RW RW
INT0EN INT0PL
INT0 input enable bit 1 INT0 input polarity select bit 2 Reserved bit
RW RW
(b7-b2) Notes: 1. This bit must be set while the INT0STG bit in the PUM register is set to "0" (one-shot trigger disabled). 2. When setting the INT0PL bit to "1" (selecting both edges), the POL bit in the INT0IC must be set to "0" (selecting falling edge). 3. The IR bit in the INT0IC register may be set to "1" (interrupt requested) when the INT0PL bit is rewritten. Refer to the paragraph 19.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book.
INT0 input filter select register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol INT0F
Bit symbol
Address 001E16 Bit name INT0 input filter select bit
After reset XXXXX0002 Function
b1 b0
RW RW RW RW
INT0F0 INT0F1
0 0 1 1
0 : No filter 1 : Filter with f1 sampling 0 : Filter with f8 sampling 1 : Filter with f32 sampling
(b2)
Reserved bit
Must set to "0"
(b7-b3)
Nothing is assigned.
When write, set to "0". If read, it content is indeterminate.
Figure 10.10 INTEN Register and INT0F Register
Rev.0.91
2003 Sep 08
page 60 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
______
R8C/11 Group
10.2 INT Interrupt
_______
10.2.2 INT0 Input Filter _______ The INT0 input has a digital filter which can be sampled by one of three sampling clocks. The sampling clock is selected using the INT0F1 to INT0F0 bits in the INT0F register. The IR bit in the INT0IC register is set to "1" (interrupt requested) when the sampled input level matches three times. When the INT0F1 to INT0F0 bits are set to "012", "102", or "112", the P4_5 bit in the P4 register indicates the filtered value. _____ Figure 10.11 shows the INT0 input filter configuration. Figure 10.12 shows an operation example of _____ INT0 input filter.
f1 f8 f32 INT0 Port P45 direction register
INT0F1 to INT0F0 =012 =102 =112
Sampling clock INT0EN
Other than INT0F1 to INT0F0 =002
Digital filter (input level matches 3x)
INT0 interrupt P4_5 bit
=002
INT0F0, INT0F1: Bits in INT0F register INT0EN: Bit in INTEN register
______
Figure 10.11 INT0 Input Filter
P45 input
Sampling timing
P4_5 in P4 register
IR bit in INT0IC register
This is an operation example when the INT0F1 to INT0F0 bits in the INT0F register is set to "012", "012", or "012" (passing digital filter).
Set to "0" in program
______
Figure 10.12 Operation Example of INT0 Input Filter
Rev.0.91
2003 Sep 08
page 61 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
______
R8C/11 Group
10.2 INT Interrupt
______
______
10.2.3 INT1 Interrupt and INT2 Interrupt ______ ______ INT1 interrupts are triggered by INT1 inputs. The edge polarity is selected with the R0EDG bit in the ______ ______ TXMR register. The INT1 pin can be used only when the Timer X is in timer mode because the INT1 pin shares the same pin with the CNTR0 pin. ______ ______ INT2 interrupts are triggered by INT2 inputs. The edge polarity is selected with the R1EDG bit in the ______ ______ TYZMR register. The INT2 pin can be used only when the Timer Y is in timer mode because the INT2 pin shares the same pin with the CNTR1 pin. ______ _____ Figure 10.13 shows the TXMR and TYZMR registers when using INT1 and INT2 interrupts.
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
0000
00
Symbol TXMR
Address 008B16
After reset 0016
Bit symbol
TXMOD0 TXMOD1 R0EDG TXS TXOCNT TXMOD2
Bit name
Operation mode select bit 0, 1
b1 b0
Function
0 0 : Timer mode or pulse period measurement mode 3
RW RW RW
INT1/CNTR0 polarity 0 : Rising edge switching bit 1, 2 1 : Falling edge Timer X count start flag 0 : Stops counting 1 : Starts counting
RW RW RW RW RW RW
Must set to "0" in timer mode Operation mode select bit 2 0 : Other than pulse period measurement mode 3
TXEDG TXUND
Must set to "0" in timer mode Must set to "0" in timer mode
Notes: 1. The IR bit in the INT1IC may be set to "1" (interrupt requested) when the R0EDG bit is rewritten. Refer to the paragraph 19.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book. 2. This bit is used to select the polarity of INT1 interrupt in timer mode. 3. When using INT1 interrupts, should select timer mode.
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol TYZMR
Address 008016
After reset 0016
Bit symbol
TYMOD0
Bit name
Timer Y operation mode bit
Function
0 : Timer mode 1
RW RW
R1EDG TYWC
INT2/CNTR1 polarity 0 : Rising edge 1 : Falling edge switching bit 2 Timer Y write control bit Timer Y count start flag Timer Z-related bit 0 : Write to reload register and counter simultaneously 1 : Write to reload register 0 : Stops counting 1 : Starts counting
RW RW RW RW RW
TYS TZMOD0 TZMOD1
TZWC
RW RW
TZS Notes: 1. When using INT2 interrupts, must set to timer mode. 2. The IR bit in the INT2IC may be set to "1" (interrupt requested) when the R1EDG bit is rewritten. Refer to the paragraph 19.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book.
______ ______
Figure 10.13 TXMR Register and TYZMR Register when INT1 and INT2 Interrupt Used
Rev.0.91 2003 Sep 08 page 62 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
______
R8C/11 Group
10.2 INT Interrupt
______
10.2.4 INT3 Interrupt _____ ______ INT3 interrupts are triggered by INT3 inputs. The TCC07 bit in the TCC0 register should be se to "0" ______ _______ (INT3). The INT3 input has a digital filter which can be sampled by one of three sampling clocks. The sampling clock is selected using the TCC11 to TCC10 bits in the TCC1 register. The IR bit in the INT3IC register is set to "1" (interrupt requested) when the sampled input level matches three times. The P3_3 bit in the P3 register indicates the previous value before filtering regardless of values set in the TCC11 to TCC10 bits.
_____
When setting the TCC07 bit to "1" (fRING128), INT3 interrupts are triggered by fRING128 clock. The IR bit in the INT3IC register is set to "1" (interrupt requested) every fRING128 clock cycle or every half fRING128 clock cycle. Figure 10.14 shows the TCC0 and TCC1 registers.
Rev.0.91
2003 Sep 08
page 63 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
______
R8C/11 Group
10.2 INT Interrupt
Timer C control register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol TCC0
Address 009A16
After reset 0016
Bit symbol
TCC00
Bit name
Timer C control bit Timer C count source select bit1
Function
0 : Count stop 1 : Count start
b2 b1
RW RW RW RW RW RW RW
TCC01 TCC02 TCC03 TCC04
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fRING-fast
b4 b3
INT3 interrupt and capture polarity select bit 1, 2
0 0 : Rising edge 0 1 : Falling edge 1 0 : Both edges 1 1 : Avoid this setting Must set to "0"
Reserved bit (b6-b5) TCC07 INT3 interrupt/capture input switching bit 1, 2
0 : INT3 1 : fRING128
RW
Notes: 1. Change this bit when TCC00 bit is set to "0" (count stop). 2. The IR bit in the INT3IC may be set to "1" (interrupt requested) when the TCC03, TCC04, or TCC07 bit is rewritten. Refer to the paragraph 19.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book.
Timer C control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TCC1
Address 009B16
After reset 0016
Bit symbol
TCC10 TCC11 TCC12
Bit name
INT3 input filter select bit 1
b1 b0
Function
0 0 1 1 0: No filter 1: Filter with f 1 sampling 0: Filter with f 8 sampling 1: Filter with f 32 sampling
RW RW RW RO
Timer C counter reload select bit 2, 3 Compare 0/Capture select bit
0: No reload (free-run) 1: Set TC register to "0000 16" at compare 1 match 0: Capture (input capture mode) 2 1: Compare 0 output (output compare mode)
b5 b4
TCC13
RW
TCC14
Compare 0 output mode select bit 3
TCC15
0 0: CMP0 output remains unchanged even when compare 0 signal matched 0 1: CMP0 output is reversed when compare 0 signal is matched 1 0: CMP0 output is set to low when compare 0 signal is matched 1 1: CMP0 output is set to high when compare 0 signal is matched
RW
TCC16
Compare 1 output mode select bit 3
b7 b6
RW
TCC17
0 0: CMP1 output remains unchanged even when compare 1 signal matched 0 1: CMP1 output is reversed when compare 1 signal is matched 1 0: CMP1 output is set to low when compare 1 signal is matched 1 1: CMP1 output is set to high when compare 1 signal is matched
Notes: 1. Input is recognized only when the same value from INT3 pin is sampled three times in succession. 2. The TCC00 bit in the TCC0 register should be set to "0" (count stop) when rewriting the TCC13 bit. 3. The TCC12 and TCC14 to TCC17 should be set to "0" when the TCC13 bit is "0" (input capture mode).
Figure 10.14 TCC0 Register and TCC1 Register
Rev.0.91 2003 Sep 08 page 64 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
10.3 Key Input Interrupt
10.3 Key Input Interrupt
_____ _____
A key input interrupt is generated on an input edge of any of the K10 to K13 pins. Key input interrupts can _____ be used as a key-on wakeup function to exit wait or stop mode. KIi input can be enabled or disabled selecting with the KIiEN (i=0 to 3) bit in the KIEN register. The edge polarity can be rising edge or falling _____ edge selecting with the KIiPL bit in the KIEN register. Note, however, that while input on any KIi pin which has had the KIiPL bit set to "0" (falling edge) is pulled low, inputs on all other pins of the port are not _____ detected as interrupts. Similarly, while input on any KIi pin which has had the KIiPL bit set to "1" (rising edge) is pulled high, inputs on all other pins of the port are not detected as interrupts. Figure 10.15 shows a block diagram of the key input interrupt.
PU02 bit in PUR0 register Pull-up transistor
KUPIC register
PD1_3 bit in PD1 register KI3EN bit PD1_3 bit KI3PL=0
KI3 Pull-up transistor KI2 KI2 input KI2PL=1 polarity select bit Pull-up transistor KI1 KI1PL=1 KI1 input polarity select bit KI0PL=0 KI0 input KI0PL=1 polarity select bit KI0EN bit PD1_0 bit KI1PL=0 KI0EN, KI1EN, KI2EN, KI3EN, KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register KI1EN bit PD1_1 bit KI3 input KI3PL=1 polarity select bit KI2PL=0 KI2EN bit PD1_2 bit
Interrupt control circuit
Key input interrupt request
Pull-up transistor KI0
Figure 10.15 Key Input Interrupt
Key input enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol KIEN
Bit symbol
Address 009816 Bit name
After reset 0016 Function 0 : Disabled 1 : Enabled 0 : Falling edge 1 : Rising edges 0 : Disabled 1 : Enabled 0 : Falling edge 1 : Rising edges 0 : Disabled 1 : Enabled 0 : Falling edge 1 : Rising edges 0 : Disabled 1 : Enabled 0 : Falling edge 1 : Rising edges RW RW RW RW RW RW RW RW RW
KI0EN KI0PL KI1EN KI1PL KI2EN KI2PL KI3EN KI3PL
KI0 input enable bit KI0 input polarity select bit KI1 input enable bit KI1 input polarity select bit KI2 input enable bit KI2 input polarity select bit KI3 input enable bit KI3 input polarity select bit
Notes: 1. The IR bit in the KUPIC register may be set to "1" (interrupt requested) when the KIEN register is rewritten. Refer to the paragraph 19.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book.
Figure 10.16 KIEN Register
Rev.0.91 2003 Sep 08 page 65 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
10.4 Address Match Interrupt
10.4 Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0, 1). Set the start address of any instruction in the RMADi register. Use the AIER0 and AIER1 bits in the AIER register to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL. The value of the PC that is saved to the stack when an address match interrupt is acknowledged varies depending on the instruction at the address indicated by the RMAD i register (see the paragraph "register saving" for the value of the PC). Not appropriate return address is pushed on the stack. There are two ways to return from the address match interrupt as follows: * Change the content of the stack and use a REIT instruction. * Use an instruction such as POP to restore the stack as it was before an interrupt request was acknowledged. And then use a jump instruction. Table 10.6 lists the value of the PC that is saved to the stack when an address match interrupt is acknowledged. Figure 10.17 shows the AIER, and RMAD1 to RMAD0 registers. Table 10.6 Value of PC Saved to Stack when Address Match Interrupt Acknowledged Address indicated by RMADi register (i=0,1) PC value savedNote * 16-bit operation code instruction Address indicated by * Instruction shown below among 8-bit operation code instructions RMADi register + 2 ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B:S #IMM8,dest STNZ.B:S #IMM8,dest STZX.B:S #IMM81,#IMM82,dest CMP.B:S #IMM8,dest PUSHM src POPM dest JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (However, dest = A0 or A1) * Instructions other than the above Address indicated by RMADi register + 1 Note: See the paragraph "saving registers" for the PC value saved. Table 10.7 Relationship Between Address Match Interrupt Sources and Associated Registers Address match interrupt sources Address match interrupt enable bit Address match interrupt register Address match interrupt 0 AIER0 RMAD0 Address match interrupt 1 AIER1 RMAD1
Rev.0.91
2003 Sep 08
page 66 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
10.4 Address Match Interrupt
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AIER Bit symbol
Address 000916 Bit name Address match interrupt 0 enable bit Address match interrupt 1 enable bit
After reset XXXXXX002 Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
RW RW RW
AIER0 AIER1
(b7-b2)
Nothing is assigned. When write, set to "0". When read, their contents are indeterminate.
Address match interrupt register i (i = 0, 1)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol RMAD0 RMAD1
Address 001216 to 001016 001616 to 001416
After reset X0000016 X0000016
Function Address setting register for address match interrupt
Setting range 0000016 to FFFFF16
RW RW
(b7-b4)
Nothing is assigned. When write, set to "0". When read, its content is indeterminate.
Figure 10.17 AIER Register and RMAD0 to RMAD1 Registers
Rev.0.91
2003 Sep 08
page 67 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
11. Watchdog Timer
11. Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be performed when the watchdog timer underflows after reaching the terminal count can be selected using the PM12 bit in the PM1 register. The PM12 bit can only be set to "1" (reset). Once this bit is set to "1", it cannot be set to "0" (watchdog timer interrupt) in a program. Refer to Section 5.1.5, "Watchdog Timer Reset" for details. The divide-by-N value for the prescaler can be chosen to be 16 or 128 with the WDC7 bit in the WDC register. The period of watchdog timer can be calculated as given below. The period of watchdog timer is, however, subject to an error due to the prescaler.
Watchdog timer period =
Prescaler dividing (16 or 128) X Watchdog timer count (32768) CPU clock
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog timer period is approx. 32.8 ms. Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start counting by writing to the WDTS register. After that, the watchdog timer is initialized by writing to the WDTR register and the counting continues. In stop mode and wait mode, the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or state are released. Figure 11.1 shows the block diagram of the watchdog timer. Figure 11.2 shows the watchdog timerrelated registers.
Prescaler
WDC7 = 0
PM12 = 0
1/16 1/128
Watchdog timer interrupt request
Watchdog timer
WDC7 = 1 PM12 = 1
CPU clock
Watchdog timer Reset
Write to WDTS register RESET
Set to "7FFF16"
Figure 11.1 Watchdog Timer Block Diagram
Rev.0.91
2003 Sep 08
page 68 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
11. Watchdog Timer
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol WDC Bit symbol (b4-b0) (b5) (b6) WDC7
Address 000F16 Bit name
After reset 000XXXXX2 Function RW RO RW RW RW
High-order bit of watchdog timer Reserved bit Reserved bit Prescaler select bit Must set to "0" Must set to "0" 0 : Divided by 16 1 : Divided by 128
Watchdog timer reset register
b7 b0
Symbol WDTR
Address 000D16
After reset Indeterminate RW WO
Function The watchdog is initialized after a write instruction to this register. The watchdog timer value is always initialized to "7FFF16" regardless of whatever value is written.
Watchdog timer start register
b7 b0
Symbol WDTS
Address 000E16
After reset Indeterminate RW WO
Function The watchdog timer starts counting after a write instruction to this register.
Figure 11.2 WDC Register, WDTR Register, and WDTS Register
Rev.0.91
2003 Sep 08
page 69 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12. Timers
12. Timers
The microcomputer has three 8-bit timers and one 16-bit timer. The three 8-bit timers are Timer X, Timer Y, and Timer Z and each one has an 8-bit prescaler. The 16-bit timer is Timer C and has input capture and output compare. All these timers function independently. The count source for each timer is the operating clock that regulates the timing of timer operations such as counting and reloading. Table 12.1 lists functional comparison.
Table 12.1 Functional Comparison Item Configuration Timer X 8-bit timer with 8-bit prescaler Count Count source Down *f1 *f2 *f8 *f32 Function Timer mode Pulse output mode Event counter mode Pulse width measurement mode Pulse period measurement mode Programmable waveform generation mode Programmable one-shot generation mode Programmable wait one-shot generation mode Input capture mode Output compare mode Input pin Output pin Related interrupt provided provided provided provided provided not provided not provided not provided not provided not provided CNTR0 CNTR0 __________ CNTR0 Timer X int _____ INT1 int Timer Y 8-bit timer with 8-bit prescaler Down *f1 *f8 *fRING *Input from CNTR1 pin provided not provided provided1 not provided not provided provided not provided not provided not provided not provided CNTR1 CNTR1 Timer Y int _____ INT2 int Timer Z 8-bit timer with 8-bit prescaler Down *f1 *f2 *f8 *Timer Y underflow provided not provided not provided not provided not provided provided provided provided not provided not provided _____ INT0 TZOUT Timer Z int _____ INT0 int Timer C 16-bit free-run timer Up *f1 *f8 *f32 *fRING-fast not provided not provided not provided not provided not provided not provided not provided not provided provided provided TCIN CMP00 to CMP02 CMP10 to CMP12 Timer C int _____ INT3 int compare 0 int compare 1 int Timer stop provided provided provided provided
Note: Select the input from the CNTR1 pin as a count source of timer mode.
Rev.0.91
2003 Sep 08
page 70 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.1 Timer (Timer X)
12.1 Timer X
The Timer X is an 8-bit timer with an 8-bit prescaler. Figure 12.1 shows the block diagram of Timer X. Figures 12.2 and 12.3 show the Timer X-related registers. The Timer X has five operation modes listed as follows: * Timer mode: * Pulse output mode: * Event counter mode: The timer counts an internal count source (clock source). The timer counts an internal count source and outputs the pulses whose polarity is inverted at the timer the timer underflows. The timer counts external pulses.
* Pulse width measurement mode: The timer measures an external pulse's pulse width. * Pulse period measurement mode:The timer measures an external pulse's period.
Peripheral data bus TXCK1 to TXCK0 =002
f1 f8 =012 f32 =102 =112 f2
TXMOD1 to TXMOD0 =002 or 012 =112
Reload register
Reload register
Counter =102 TXS bit PREX register
Counter TX register
Timer X interrupt
INT1/CNTR0
Polarity switching TXMOD1 to TXMOD0 bits=01 2 R0EDG =1 Q Toggle flip-flop CK Q TXOCNT bit R0EDG=0 Write to TX register TXMOD1 to TXMOD0 bits=01 2 CLR
INT1 interrupt
CNTR0
Figure 12.1 Timer X Block Diagram
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TXMR
Address 008B16
After reset 0016
Bit symbol
TXMOD0
Bit name
Operation mode select bit 0, 1
b1 b0
Function
0 0 : Timer mode or pulse period measurement mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode Function varies with each operation mode 0 : Stops counting 1 : Starts counting Function varies with each operation mode 0 : Except in pulse period measurement mode 1 : Pulse period measurement mode Function varies with each operation mode. Function varies with each operation mode.
RW RW RW RW RW RW RW RW RW
TXMOD1 INT1/CNTR0 polarity switching bit1 Timer X count start flag P30/CNTR0 select bit Operation mode select bit 2 Active edge reception flag Timer X under flow flag
R0EDG
TXS TXOCNT TXMOD2 TXEDG TXUND
Notes: 1. The IR bit in the INT1IC register may be set to "1" (interrupt requested) when the R0EDG bit is rewritten. Refer to the paragraph 19.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book.
Figure 12.2 TXMR Register
Rev.0.91 2003 Sep 08 page 71 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.1 Timer (Timer X)
Prescaler X Register
b7 b0
Symbol PREX
Address 008C16
After reset FF16
Mode Timer mode Pulse output mode
Function Internal count source is counted Internal count source is counted
Setting range 0016 to FF16 0016 to FF16 0016 to FF16
RW RW RW RW
Event counter mode Externally input pulses are counted Pulse width of externally input Pulse width measurement mode pulses is measured (Internal count source is counted) Pulse period of externally input Pulse period measurement mode pulses is measured (Internal count source is counted)
0016 to FF16
RW
0016 to FF16
RW
Timer X Register
b7 b0
Symbol TX
Address 008D16
After reset FF16
Function Underflow of Prescaler X is counted
Setting range 0016 to FF16
RW RW
Timer count source setting register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol TCSS Bit symbol TXCK0 TXCK1 TYCK0 TYCK1 TZCK0 TZCK1 Reserved bit (b7-b6)
Address 008E16 Bit name Timer X count source select bit1
After reset 0016 RW RW RW RW RW RW RW RW
Function
b1 b0
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : f2
b3 b2
Timer Y count source select bit1
0 0 : f1 0 1 : f8 1 0 : fRING 1 1 : Selects input from CNTR1 pin
b5 b4
Timer Z count source select bit1
0 0 : f1 0 1 : f8 1 0 : Selects Timer Y underflow 1 1 : f2 Must be set to "0"
Notes: 1. Avoid switching a count source, while a counter is in progress. Timer counter must be stopped before switching a count source.
Figure 12.3 PREX Register, TX Register, and TCSS Register
Rev.0.91 2003 Sep 08 page 72 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.1 Timer (Timer X)
12.1.1 Timer Mode In this mode, the timer counts an internally generated count source (See "Table 12.2 Timer Mode Specifications"). Figure 12.4 shows the TXMR register in timer mode. Table 12.2 Timer Mode Specifications Item
Count source Count operation f1, f2, f8, f32 * Down-count * When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1)(m+1) n: set value of PREX register, m: set value of TX register Write "1" (count start) to TXS bit in TXMR register Write "0" (count stop) to TXS bit in TXMR register When Timer X underflows [Timer X interruption] Programmable I/O port, or INT1 interrupt input Programmable I/O port Count value can be read by reading TX register Same applies to PREX register. Value written to TX register is written to both reload register and counter. Same applies to PREX register.
Specification
Divide ratio Count start condition Count stop condition Interrupt request generation timing INT1/CNTR0 pin function CNTR0 pin function Read from timer Write to timer
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
0000
00
Symbol TXMR
Address 008B16
After reset 0016
Bit symbol
TXMOD0 TXMOD1 R0EDG TXS TXOCNT TXMOD2
Bit name
Operation mode select bit 0, 1
b1 b0
Function
0 0 : Timer mode or pulse period measurement mode
RW RW RW
INT1/CNTR0 polarity 0 : Rising edge switching bit 1, 2 1 : Falling edge Timer X count start flag 0 : Stops counting 1 : Starts counting
RW RW RW RW RW RW
Must set to "0" in timer mode Operation mode select bit 2 0 : Other than pulse period measurement mode
TXEDG TXUND
Must set to "0" in timer mode Must set to "0" in timer mode
Notes: 1. The IR bit in the INT1IC register may be set to "1" (interrupt requested) when the R0EDG bit is rewritten. Refer to the paragraph 19.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book. 2. This bit is used to select the polarity of INT1 interrupt in timer mode.
Figure 12.4 TXMR Register in Timer Mode
Rev.0.91
2003 Sep 08
page 73 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.1 Timer (Timer X)
12.1.2 Pulse Output Mode In this mode, the timer counts an internally generated count source, and outputs from the CNTR0 pin a pulse whose polarity is inverted each time the timer underflows (See "Table 12.3 Pulse Output mode Specifications"). Figure 12.5 shows TXMR register in pulse output mode. Table 12.3 Pulse Output Mode Specifications Item
Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing INT1/CNTR0 pin function CNTR0 pin function Read from timer Write to timer Select function
Specification
f1, f2, f8, f32 * Down-count * When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1)(m+1) n: set value of PREX register, m: set value of TX register Write "1" (count start) to TXS bit in TXMR register Write "0" (count stop) to TXS bit in TXMR register * When Timer X underflows [Timer X interruption] * Rising (R0EDG=0) or falling (R0EDG=1) of CNTR0 output [INT1 interrupt] Pulse output Programmable I/O port or inverted output of CNTR0 Count value can be read by reading TX register. Same applies to PREX register. Value written to TX register is written to both reload register and counter. Same applies to PREX register. * Inverted pulse output function The polarity of CNTR0 output pulse can be reversed with TXOCNT bit _____ * INT1/CNTR0 polarity switching function Polarity level at starting of pulse output can be selected with R0EDG bit
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
000
01
Symbol TXMR
Address 008B16
After reset 0016
Bit symbol
TXMOD0 TXMOD1 R0EDG TXS TXOCNT TXMOD2
Bit name
Operation mode select bit 0, 1
b1 b0
Function
0 1 : Pulse output mode
RW RW RW RW RW RW RW RW RW
INT1/CNTR0 polarity 0: CNTR0 output starts at "H" switching bit 1 1: CNTR0 output starts at "L" Timer X count start flag P30/CNTR0 select bit 0 : Stops counting 1 : Starts counting 0 : Port P30 1 : CNTR0 output
Must set to "0" in pulse output mode Must set to "0" in pulse output mode Must set to "0" in pulse output mode
TXEDG TXUND
Notes: 1. The IR bit in the INT1IC register may be set to "1" (interrupt requested) when the R0EDG bit is rewritten. Refer to the paragraph 19.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book.
Figure 12.5 TXMR Register in Pulse Output Mode
Rev.0.91 2003 Sep 08 page 74 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.1 Timer (Timer X)
12.1.3 Event Counter Mode In this mode, the timer counts an external signal fed to INT1/CNTR0 pin (See "Table 12.4 Event Counter Mode Specifications"). Figure 12.6 shows TXMR register in event counter mode. Table 12.4 Event Counter Mode Specifications Item
Count source Count operation
Specification
External signals fed to CNTR0 pin (Active edge is selected by program) * Down count * When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1)(m+1) n: set value of PREX register, m: set value of TX register Write "1" (count start) to TXS bit in TXMR register Write "0" (count stop) to TXS bit in TXMR register * When Timer X underflows [Timer X interrupt] * CNTR0 input count edges [INT1 interrupt] Count source input Programmable I/O port Count value can be read by reading TX register Same applies to PREX register. Value written to TX register is written to both reload register and counter. Same applies to PREX register. * INT1/CNTR0 polarity switching function Active edge of count source can be selected with R0EDG.
Divide ratio Count start condition Count stop condition Interrupt request generation timing INT1/CNTR0 pin function CNTR0 pin function Read from timer Write to timer Select function
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
0000
10
Symbol TXMR
Address 008B16
After reset 0016
Bit symbol
TXMOD0 TXMOD1 R0EDG TXS TXOCNT TXMOD2
Bit name
Operation mode select bit 0, 1
b1 b0
Function
1 0 : Event counter mode
RW RW RW
INT1/CNTR0 polarity 0 : Rising edge switching bit 1 1 : Falling edge Timer X count start flag 0 : Stops counting 1 : Starts counting
RW RW RW RW RW RW
Must set to "0" in event counter mode Must set to "0" in event counter mode Must set to "0" in event counter mode Must set to "0" in event counter mode
TXEDG TXUND
Notes: 1. The IR bit in the INT1IC register may be set to "1" (interrupt requested) when the R0EDG bit is rewritten. Refer to the paragraph 19.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book.
Figure 12.6 TXMR Register in Event Counter Mode
Rev.0.91 2003 Sep 08 page 75 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.1 Timer (Timer X)
12.1.4 Pulse Width Measurement Mode In this mode, the timer measures the pulse width of an external signal fed to INT1/CNTR0 pin (See "Table 12.5 Pulse Width Measurement Mode Specifications"). Figure 12.7 shows the TXMR register in pulse width measurement mode. Figure 12.8 shows an operation example in pulse width measurement mode. Table 12.5 Pulse Width Measurement Mode Specifications Item
Count source Count operation f1, f2, f8, f32 * Down-count * Continuously counts the selected signal only when the measurement pulse is "H" level, or conversely only "L" level. * When the timer underflows, it reloads the reload register contents before continuing counting Write "1" (count start) to TXS bit in TXMR register Write "0" (count stop) to TXS bit in TXMR register * When Timer X underflows [Timer X interruption] * Rising or falling of CNTR0 input (end of measurement period) [INT1 interrupt] Measurement pulse input Programmable I/O port Count value can be read by reading TX register Same applies to PREX register. Value written to TX register is written to both reload register and counter. Same applies to PREX register. _____ * INT1/CNTR0 polarity switching function Active edge of count source can be selected with R0EDG.
Specification
Count start condition Count stop condition Interrupt request generation timing INT1/CNTR0 pin function CNTR0 pin function Read from timer Write to timer Select function
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
0000
11
Symbol TXMR
Address 008B16
After reset 0016
Bit symbol
TXMOD0 TXMOD1 R0EDG TXS TXOCNT TXMOD2
Bit name
Operation mode select bit 0, 1
b1 b0
Function
1 1 : Pulse width measurement mode
RW RW RW
INT1/CNTR0 polarity 0 : Measures "H" level width switching bit 1 1 : Measures "L" level width Timer X count start flag 0 : Stops counting 1 : Starts counting
RW RW RW RW RW RW
Must set to "0" in pulse width measurement mode Must set to "0" in pulse width measurement mode Must set to "0" in pulse width measurement mode Must set to "0" in pulse width measurement mode
TXEDG TXUND
Notes: 1. IThe IR bit in the INT1IC register may be set to "1" (interrupt requested) when the R0EDG bit is rewritten. Refer to the paragraph 19.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book.
Figure 12.7 TXMR Register in Pulse Width Measurement Mode
Rev.0.91 2003 Sep 08 page 76 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.1 Timer (Timer X)
n = high-level: the contents of TX register, low-level: the contents of PREX register FFFF16
Counter contents (hex)
Count start
Underflow
n Count stop Count stop
Count restart 000016 Time Set to "1" by program TXS bit in TXMR register "1" "0"
Measurement pulse "H" (CNTR0 pin input) "L" Cleared to "0" when interrupt request is accepted, or cleared by program IR bit in INT1IC register "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by program IR bit in TXIC register "1" "0"
Conditions: "H" level width of measurement pulse is measured. (R0EDG=1)
Figure 12.8 Operation Example in Pulse Width Measurement Mode
Rev.0.91
2003 Sep 08
page 77 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.1 Timer (Timer X)
12.1.5 Pulse Period Measurement Mode In this mode, the timer measures the pulse period of an external signal fed to INT1/CNTR0 pin (See "Table 12.6 Pulse Period Measurement Mode Specifications"). Figure 12.9 shows the TXMR register in pulse period measurement mode. Figure 12.10 shows an operation example in pulse period measurement mode. Table 12.6 Pulse Period Measurement Mode Specifications Item
Count source Count operation f1, f2, f8, f32 * Down-count * After an active edge of measurement pulse is input, contents in the read-out buffer is retained in the first underflow of prescaler X. Then the timer X reloads contents in the reload register in the second underflow of prescaler X and continues counting. Write "1" (count start) to TXS bit in TXMR register Write "0" (count stop) to TXS bit in TXMR register * When Timer X underflows or reloads [Timer X interrupt] _____ * Rising or falling of CNTR0 input (end of measurement period) [INT1 interrupt] Measurement pulse input1 Programmable I/O port Contents in the read-out buffer can be read by reading TX register. The value retained in the read-out buffer is released by reading TX register. Value written to TX register is written to both reload register and counter.
Specification
Count start condition Count stop condition Interrupt request generation timing INT1/CNTR0 pin function CNTR0 pin function Read from timer Write to timer Select function
Same applies to PREX register. _____ * INT1/CNTR0 polarity switching function Measurement period of input pulse can be selected with R0EDG bit. Note: The period of input pulse must be longer than twice the period of prescaler X. Longer pulse for H width and L width than the prescaler X period must be input. If shorter pulse than the period is input to the CNTR0 pin, the input may be disabled.
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
10
00
Symbol TXMR
Address 008B16
After reset 0016
Bit symbol
TXMOD0 TXMOD1 R0EDG
Bit name
Operation mode select bit 0, 1 INT1/CNTR0 polarity switching bit 1 Timer X count start flag
b1 b0
Function
0 0 : Pulse period measurement mode 0: Measures a measurement pulse from one rising edge to the next rising edge 1: Measures a measurement pulse from one falling edge to the next falling edge 0 : Stops counting 1 : Starts counting
RW RW RW
RW
TXS TXOCNT TXMOD2 TXEDG 2 TXUND 2
RW RW RW RW RW
Must set to "0" in pulse period measurement mode Operation mode select bit 2 Active edge reception flag Timer X underflow flag 1 : Pulse period measurement mode 0 : No active edge 1 : Active edge found 0 : No under flow 1 : Under flow found
Notes: 1. The IR bit in the INT1IC register may be set to "1" (interrupt requested) when the R0EDG bit is rewritten. Refer to the paragraph 19.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book. 2. TXEDG and TXUND bits are set to "0" by writing a "0" in a program. (Writing a "1" has no effect.)
Figure 12.9 TXMR Register in Pulse Period Measurement Mode
Rev.0.91 2003 Sep 08 page 78 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.1 Timer (Timer X)
Underflow signal of prescaler X
Set to "1" by program
TXS bit in TXMR "1" register "0"
Starts counting
CNTR0 pin input
"1" "0"
Timer X reloads 0F16
Timer X reloads
Timer X reloads 0116 0016 0F16 0E16
Timer X contents Contents of read-out buffer1
0E16 0D16 0F16 0E16 0D16 0C16 0B16 0A16 0916 0F16 0E16 0D16 Retained Retained 0D16 0B16 0A16 0916 0D16 Timer X read (Note 3)
0F16
0E16
0116 0016 0F16 0E16
TXEDG bit in TXMR register
(Note 2)
"1" "0"
Timer X read (Note 3) (Note 2)
Cleared to "0" by program (Note 4)
TXUND bit in TXMR register
(Note 6)
"1" "0"
Cleared to "0" by program (Note 5)
IR bit in TXIC register
"1" "0"
Cleared to "0" when interrupt request is accepted, or cleared by program
IR bit in INT1IC register
"1" "0"
Cleared to "0" when interrupt request is accepted, or cleared by program
Conditions: A period from one rising edge to the next rising edge of measurement pulse is measured (R0EDG=0) with TX register initial value=0F16.
Notes: 1. The contents of the read-out buffer can be read when the TX register is read in pulse period measurement mode. 2. After an active edge of measurement pulse is input, the TXEDG bit in the TXMR register is set to "1" (active edge found) when the prescaler X underflows for the second time. 3. The TX register should be read before the next active edge is input after the TXEDG bit is set to "1" (active edge found). The contents in the read-out buffer is retained until the TX register is read. If the TX register is not read before the next active edge is input, the measured result of the previous period is retained. 4. When set to "0" by program, use a MOV instruction to write "0" to the TXEDG in the TXMR register. At the same time, write "1" to the TXUND bit. 5. When set to "0" by program, use a MOV instruction to write "0" to the TXUND in the TXMR register. At the same time, write "1" to the TXEDG bit. 6. The TXUND and TXEDG bits are both set to "1" if the timer underflows and reloads on an active edge simultaneously. In this case, the validity of the TXUND bit should be determined by the contents of the read-out buffer.
Figure 12.10 Operation Example in Pulse Period Measurement Mode
Rev.0.91
2003 Sep 08
page 79 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.2 Timer (Timer Y)
12.2 Timer Y
Timer Y is an 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Y Primary and Timer Y Secondary. Figure 12.11 shows a block diagram of Timer Y. Figures 12.12 to 12.14 show the TYZMR, PREY, TYSC, TYPR, TYZOC, PUM, and YCSS registers. The Timer Y has two operation modes as follows: * Timer mode: The timer counts an internal count source (clock source). * Programmable waveform generation mode: The timer outputs pulses of a given width successively.
Peripheral data bus TYSC register TYPR register Reload register Reload register
TYCK1 to TYCK0 =002 f1 =012 f8 =102 fRING =112 TYS=1
Reload register
Counter PREY register
Counter
Timer Y interrupt
INT2 interrupt Polarity switching TYOPL=1 TYMOD0=1 INT2/CNTR1 P3_2 bit in P3 register TYOCNT=1 TYOPL=0 TYOCNT=0 Q Q Toggle flip-flop CLR CK
Write to TYZMR register TYMOD0 bit=1
Figure 12.11 Timer Y Block Diagram
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TYZMR
Address 008016
After reset 0016
Bit symbol
TYMOD0 R1EDG TYWC
Bit name
Timer Y operation mode bit
Function
0 : Timer mode 1 : Programmable waveform generation mode
RW RW RW
INT2/CNTR1 polarity 0 : Rising edge 1 : Falling edge switching bit 1 Timer Y write control bit Timer Y count start flag Timer Z operation mode bit Function varies depending on the operation mode 0 : Stops counting 1 : Starts counting
b5 b4
RW RW RW RW
TYS TZMOD0 TZMOD1
0 0 : Timer mode 0 1 : Programmable waveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable wait one-shot generation mode Function varies depending on the operation mode 0 : Stops counting 1 : Starts counting
TZWC
Timer Z write control bit Timer Z count start flag
RW
TZS
RW
Notes: 1. The IR bit in the INT2IC register may be set to "1" (interrupt requested) when the R1EDG bit is rewritten. Refer to the paragraph 19.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book.
Figure 12.12 TYZMR Register
Rev.0.91 2003 Sep 08 page 80 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.2 Timer (Timer Y)
Prescaler Y register
b7 b0
Symbol PREY
Address 008116
After reset FF16
Mode Timer mode
Function Internal count source or CNTR1 input is counted
Setting range 0016 to FF16 0016 to FF16
RW RW RW
Programmable Internal count source is counted waveform generation mode
Timer Y secondary register
b7 b0
Symbol TYSC
Address 008216
After reset FF16
Mode Timer mode Disabled
Function
Setting range
RW
Programmable Underflow of Prescaler Y is waveform generation counted1 mode
0016 to FF16
WO2
Notes: 1. The values of TYPR register and TYSC register are reloaded to the counter alternately for counting. 2. The count value can be read out by reading the TYPR register even when the secondary period is being counted.
Timer Y primary register
b7 b0
Symbol TYPR
Address 008316
After reset FF16
Mode Timer mode
Function Underflow of Prescaler Y is counted
Setting range 0016 to FF16 0016 to FF16
RW RW RW
Programmable Underflow of Prescaler Y is waveform generation counted1 mode
Notes: 1. The values of TYPR register and PYSC register are reloaded to the counter alternately for counting.
Timer Y, Z output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TYZOC
Address 008A16
After reset 0016
Bit symbol
TZOS
Bit name Timer Z one-shot start bit1
Timer Y programmable waveform generation output switching bit2 Timer Z programmable waveform generation output switching bit2
Function
0 : Stops one-shot 1 : Starts one-shot 0 : Outputs programmable waveform 1 : Outputs the value of P32 port register 0 : Outputs programmable waveform 1 : Outputs the value of P31 port register
RW RW
TYOCNT
RW
TZOCNT
RW
(b7-b3)
Nothing is assigned. When write, set to "0". When read, its content is "0".
Notes: 1. This bit is set to "0" when the output of one-shot waveform is completed. The TZOS bit should be set to "0" if the one-shot waveform output is terminated by setting the TYS bit in the TYZMR to "0" during the waveform output. 2. This bit is enabled only when operating in programmable waveform generation mode.
Figure 12.13 PREY Register, TYSC Register, TYPR Register, and TYZOC Register
Rev.0.91 2003 Sep 08 page 81 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.2 Timer (Timer Y)
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
Symbol PUM Bit symbol (b3-b0) TYOPL
Address 008416 Bit name Reserved bit Timer Y output level latch Timer Z output level latch INT0 pin one-shot trigger control bit2 (Timer Z)
After reset 0016
Function Must set to "0" Function varies depending on the operation mode
RW RW
RW
TZOPL
Function varies depending on the operation mode
RW
INOSTG
0 : INT0 pin one-shot trigger invalid 1 : INT0 pin one-shot trigger valid
RW
INOSEG
INT0 pin one-shot trigger 0 : Edge trigger at falling edge polarity select bit1 1 : Edge trigger at rising edge (Timer Z)
RW
Notes: 1. The INOSEG bit is valid only when the INT0PL bit in the INTEN register is "0" (one-edge). 2. The INOSGT bit must be set to "1" after the INT0EN bit in the INTEN register and the INOSEG bit in the PUM register are set.
Timer count source setting register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol TCSS Bit symbol TXCK0 TXCK1 TYCK0 TYCK1 TZCK0 TZCK1 Reserved bit (b7-b6)
Address 008E16 Bit name Timer X count source select bit1
After reset 0016 RW RW RW RW RW RW RW RW
Function
b1 b0
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : f2
b3 b2
Timer Y count source select bit1
0 0 : f1 0 1 : f8 1 0 : fRING 1 1 : Selects input from CNTR1 pin
b5 b4
Timer Z count source select bit1
0 0 : f1 0 1 : f8 1 0 : Selects Timer Y underflow 1 1 : f2 Must be set to "0"
Notes: 1. Avoid switching a count source, while a counter is in progress. Timer counter must be stopped before switching a count source.
Figure 12.14 PUM Register and TCSS Register
Rev.0.91
2003 Sep 08
page 82 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.2 Timer (Timer Y)
12.2.1 Timer Mode In this mode, the timer counts an internally generated count source (see "Table 12.7 Timer Mode Specifications"). An external signal input to the CNTR1 pin can be counted. The TYSC register is unused in timer mode. Figure 12.15 shows the TYZMR and PUM registers in timer mode. Table 12.7 Timer Mode Specifications Item
Count source Count operation
Specification
f1, f8, fRING, external signal fed to CNTR1 pin * Down-count * When the timer underflows, it reloads the reload register contents before continuing counting (When the Timer Y underflows, the contents of the Timer Y primary reload register is reloaded.)
Divide ratio Count start condition Count stop condition Interrupt request generation timing INT2/CNTR1 pin function Read from timer Write to timer1
fi/(n+1)(m+1) n: set value in PREY register, m: set value in TYPR register Write "1" (count start) to TYS bit in TYZMR register Write "0" (count stop) to TYS bit in TYZMR register * When Timer Y underflows [Timer Y interrupt] * Rising or falling of INT2/CNTR1 input [INT2 interrupt] Programmable I/O port, count source input or INT2 interrupt input Count value can be read out by reading TYPR register. Same applies to PREY register. Value written to TYPR register is written to both reload register and counter or written to only reload register. Selected by program. Same applies to PREY register. * Event counter function When setting TYCK1 to TYCK0 bits to "112", an external signal fed to CNTR1 pin is counted. * INT2/CNTR1 switching bit Active edge of count source is selected by R1EDG bit.
Select function
Notes: 1. The IR bit in the TYIC register is set to "1" (interrupt requested) if you write to the TYPR or PREY register while both of the following conditions are met. Conditions: * TYWC bit in TYZMR register is "0" (write to reload register and counter simultaneously) * TYS bit is "1" (count start) To write to the TYPR or PREY register in the above state, disable interrupts before writing.
Rev.0.91
2003 Sep 08
page 83 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.2 Timer (Timer Y)
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol TYZMR
Address 008016
After reset 0016
Bit symbol
TYMOD0
Bit name
Timer Y operation mode bit INT2/CNTR1 polarity switching bit 1 Timer Y write control bit 2 Timer Y count start flag Timer Z-related bit
Function
0 : Timer mode 0 : Rising edge 1 : Falling edge 0 : Write to reload register and counter simultaneously 1 : Write to reload register 0 : Stops counting 1 : Starts counting
RW RW
R1EDG TYWC
RW RW RW RW RW
TYS TZMOD0 TZMOD1
TZWC
RW RW
TZS
Notes: 1. The IR bit in the INT2IC register may be set to "1" (interrupt requested) when the R1EDG bit is rewritten. Refer to the paragraph 1.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book. 2. When TYS bit= 1 (starts counting), the value set in the TYWC bit is valid. If TYWC bit=0, the timer Y count value is written to both reload register and counter. If TYWC bit=1, the timer Y count value is written to the reload register only. When TYS bit=0 (stops counting), the timer Y count value is written to both reload register and counter regardless of how the TYWC bit is set.
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
Symbol PUM Bit symbol (b3-b0) TYOPL
Address 008416 Bit name Reserved bit Timer Y output level latch Timer Z-related bits
After reset 0016
Function Must set to "0" Invalid in timer mode
RW RW
RW
TZOPL
RW INOSTG
RW
INOSEG
RW
Figure 12.15 TYZMR Register and PUM Register in Timer Mode
Rev.0.91
2003 Sep 08
page 84 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.2 Timer (Timer Y)
12.2.2 Programmable Waveform Generation Mode In this mode, an signal output from the TYOUT pin is inverted each time the counter underflows, while the values in the TYPR register and TYSC register are counted alternately (see "Table 12.8 Programmable Waveform Generation Mode Specifications"). A counting starts by counting the set value in the TYPR register. Figure 12.16 shows the TYZMR register in programmable waveform generation mode. Figure 12.17 shows the operation example. Table 12.8 Programmable Waveform Generation Mode Specifications Item Specification
Count source Count operation f1, f8, fRING * Down count * When the timer underflows, it reloads the contents of primary reload register and secondary reload register alternately before continuing counting. Period Count start condition Count stop condition fi/(n+1)((m+1)+(p+1)) n: set value in PREY register, m: set value in TYPR register, p: set value in TYSC register Write "1" (count start) to TYS bit in TYZMR register Write "0" (count stop) to TYS bit in TYZMR register
Interrupt request generation timing In half of count source, after Timer Y underflows during secondary period (at the same time as the CNTR1 output change) [Timer Y interrupt]. INT2/CNTR1 pin functions Read from timer Write to timer Select function Pulse output1 Count value can be read out by reading TYPR register. Same applies to PREY register2. Value written to TYPR register is written to only reload register. Same applies to TYSC register and PREY register3. * Output level latch select function The output level during primary and secondary periods is selected by the TYOPL bit. * Programmable waveform generation output switching function When the TYOCNT bit in the TYZOC register is set to "0", the output from TYOUT is inverted synchronously when Timer Y underflows during the secondary period. And when set to "1", a value in the P3_2 bit is output from TYOUT synchronously when Timer Y underflows during the secondary period4.
Notes:
1. When the counting stopped, the output level is that in the secondary period. 2. Even when counting the secondary period, read out the TYPR register. 3. The set value in the TYPR register and TYSC register are made effective by writing a value to the TYPR register. The written values are reflected to the waveform output from the next primary period after writing to the TYPR register. 4. The output is switched in sync with timer Y underflow in the secondary period.
Rev.0.91
2003 Sep 08
page 85 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.2 Timer (Timer Y)
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol TYZMR
Address 008016
After reset 0016
Bit symbol
TYMOD0
Bit name
Timer Y operation mode bit
Function
1 : Programmable waveform generation mode
RW RW
R1EDG TYWC
INT2/CNTR1 polarity 0 : Rising edge 1 : Falling edge switching bit 1 Timer Y write control bit Timer Y count start flag Timer Z-related bit Must set to "1" in programmable waveform generation mode. 2 0 : Stops counting 1 : Starts counting
RW RW RW RW RW
TYS TZMOD0 TZMOD1
TZWC
RW RW
TZS Notes: 1. The IR bit in the INT2IC register may be set to "1" (interrupt requested) when the R1EDG bit is rewritten. Refer to the paragraph 19.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book. 2. When TYS bit= 1 (starts counting), the timer Y count value is written to the reload register only. When TYS bit=0 (stops counting), the timer Y count value is written to both reload register and counter .
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol PUM Bit symbol (b3-b0) TYOPL
Address 008416 Bit name Reserved bit Timer Y output level latch
After reset 0016
Function Must set to "0" 0 : Outputs "H" for primary period Outputs "L" for secondary period Outputs "L" when the timer is stopped 1 : Outputs "L" for primary period Outputs "H" for secondary period Outputs "H" when the timer is stopped
RW RW RW
TZOPL
Timer Z-related bits
RW
INOSTG
RW
INOSEG
RW
Figure 12.16 TYZMR Register and PUM Register in Programmable Waveform Generation Mode
Rev.0.91
2003 Sep 08
page 86 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.2 Timer (Timer Y)
Set to "1" by program
"1" TYS bit in TYZMR register "0"
Count starts
Count source
Prescaler Y underflow signal
Timer Y secondary reloads Timer Y primary reloads
Contents of Timer Y
0116
0016
0216
0116
0016
0116
0016
0216
Set to "0" when interrupt request is accepted, or set by program
IR bit in TYIC "1" register "0"
Set to "0" by program
TYOPL bit in PUM register
"1" "0"
Waveform output started
Waveform output inverted
Waveform output inverted
CNTR1 pin output
"H" "L"
Primary period Secondary period Primary period
Conditions: PREY=0116, TYPR=0116, TYSC=0216 TYZOC register TYOCNT bit = 0
Figure 12.17 Timer Y Operation Example in Programmable Waveform Generation Mode
Rev.0.91
2003 Sep 08
page 87 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.3 Timer (Timer Z)
12.3 Timer Z
Timer Z is an 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Z Primary and Timer Z Secondary. Figure 12.18 shows a block diagram of Timer Z. Figures 12.19 to 12.21 show the TYZMR, PREZ, TZSC, TZPR, TYZOC, PUM, and TCSS registers. Timer Z has the following four operation modes. * Timer mode: The timer counts an internal count source (clock source) or Timer Y underflow. * Programmable waveform generation mode: The timer outputs pulses of a given width successively. * Programmable one-shot generation mode: The timer outputs one-shot pulse.
* Programmable wait one-shot generation mode: The timer outputs delayed one-shot pulse.
Peripheral data bus TZSC register TZPR register Reload register
TZCK1 to TZCK0 =002 f1 =012 f8 =102 Timer Y underflow =112 f2
Reload register
Reload register
Counter PREZ register
Counter
Timer Z interrupt
TZMOD1 to TZMOD0=102, 112 TZS TZOS INT0 interrupt Polarity select INOSEG INT0EN TZOCNT=0 TZOUT PD3_1 bit in PD3 register TZOCNT=1 TZOPL=0 TZOPL=1
INT0
Digital filter
Input polarity selected to be one edge or both edges INT0PL
TZMOD1 to TZMOD0=012, 102, 112
Q
Toggle flip-flop CLR
CK
Q
Write to TYZMR register TZMOD1 to TZMOD0 bits=012, 102, 112
Figure 12.18 Timer Z Block Diagram
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TYZMR
Address 008016
After reset 0016
Bit symbol
TYMOD0 R1EDG TYWC
Bit name
Timer Y operation mode bit
Function
0 : Timer mode 1 : Programmable waveform generation mode
RW RW RW
INT2/CNTR1 polarity 0 : Rising edge 1 : Falling edge switching bit 1 Timer Y write control bit Timer Y count start flag Timer Z operation mode bit Function varies depending on the operation mode 0 : Stops counting 1 : Starts counting
b5 b4
RW RW RW RW
TYS TZMOD0 TZMOD1
0 0 : Timer mode 0 1 : Programmable waveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable wait one-shot generation mode Function varies depending on the operation mode 0 : Stops counting 1 : Starts counting
TZWC
Timer Z write control bit Timer Z count start flag
RW
TZS
RW
Notes: 1. The IR bit in the INT2IC register may be set to "1" (interrupt requested) when the R1EDG bit is rewritten. Refer to the paragraph 19.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book.
Figure 12.19 TYZMR Register
Rev.0.91
2003 Sep 08
page 88 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.3 Timer (Timer Z)
Prescaler Z register
b7 b0
Symbol PREZ
Address 008516
After reset FF16
Mode Timer mode Programmable waveform generation mode Programmable one-shot generation mode
Function Internal count source or Timer Y underflow is counted Internal count source or Timer Y underflow is counted Internal count source or Timer Y underflow is counted
Setting range 0016 to FF16
RW RW
0016 to FF16
RW
0016 to FF16
RW
Programmable wait Internal count source or Timer Y one-shot generation underflow is counted mode
0016 to FF16
RW
Timer Z Secondary register
b7 b0
Symbol TZSC
Address 008616
After reset FF16
Mode Timer mode Programmable waveform generation mode Programmable one-shot generation mode Invalid
Function
Setting range
RW
Underflow of Prescaler Z is counted1 Invalid
0016 to FF16
WO2
Programmable wait Underflow of Prescaler Z is one-shot generation counted mode (One-shot width is counted)
0016 to FF16
WO
Notes: 1. Each value in the TZPR register and TZSC register is reloaded to the counter alternately for counting. 2. The count value can be read out by reading the TZSC register even when the secondary period is being counted.
Timer Z Primary register
b7 b0
Symbol TZPR
Address 008716
After reset FF16
Mode Timer mode Programmable waveform generation mode Programmable one-shot generation mode
Function Underflow of Prescaler Z is counted Underflow of Prescaler Z is counted1 Underflow of Prescaler Z is counted (One-shot width is counted)
Setting range 0016 to FF16
RW RW
0016 to FF16
RW
0016 to FF16
RW
Programmable wait Underflow of Prescaler Z is one-shot generation counted mode (Wait period is counted)
0016 to FF16
RW
Notes: 1. Each value in the TZPR register and TZSC register is reloaded to the counter alternately for counting.
Timer Y, Z output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TYZOC
Address 008A16
After reset 0016
Bit symbol
TZOS
Bit name Timer Z one-shot start bit1
Timer Y programmable waveform generation output switching bit2 Timer Z programmable waveform generation output switching bit2
Function
0 : Stops one-shot 1 : Starts one-shot 0 : Outputs programmable waveform 1 : Outputs the value of P32 port register 0 : Outputs programmable waveform 1 : Outputs the value of P31 port register
RW RW
TYOCNT
RW
TZOCNT
RW
(b7-b3)
Nothing is assigned. When write, set to "0". When read, its content is "0".
Notes: 1. This bit is set to "0" when the output of one-shot waveform is completed. The TZOS bit should be set to "0" if the one-shot waveform output is terminated by setting the TYS bit in the TYZMR to "0" during the waveform output. 2. This bit is enabled only when operating in programmable waveform generation mode.
Figure 12.20 PREZ Register, TZSC Register, TZPR Register, and TYZOC Register
Rev.0.91 2003 Sep 08 page 89 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.3 Timer (Timer Z)
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
Symbol PUM Bit symbol (b3-b0) TYOPL
Address 008416 Bit name Reserved bit Timer Y output level latch Timer Z output level latch INT0 pin one-shot trigger control bit2 (Timer Z)
After reset 0016
Function Must set to "0" Function varies depending on the operation mode
RW RW
RW
TZOPL
Function varies depending on the operation mode
RW
INOSTG
0 : INT0 pin one-shot trigger invalid 1 : INT0 pin one-shot trigger valid
RW
INOSEG
INT0 pin one-shot trigger 0 : Edge trigger at falling edge polarity select bit1 1 : Edge trigger at rising edge (Timer Z)
RW
Notes: 1. The INOSEG bit is valid only when the INT0PL bit in the INTEN register is "0" (one-edge). 2. The INOSGT bit must be set to "1" after the INT0EN bit in the INTEN register and the INOSEG bit in the PUM register are set.
Timer count source setting register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol TCSS Bit symbol TXCK0 TXCK1 TYCK0 TYCK1 TZCK0 TZCK1 Reserved bit (b7-b6)
Address 008E16 Bit name Timer X count source select bit1
After reset 0016 RW RW RW RW RW RW RW RW
Function
b1 b0
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : f2
b3 b2
Timer Y count source select bit1
0 0 : f1 0 1 : f8 1 0 : fRING 1 1 : Selects input from CNTR1 pin
b5 b4
Timer Z count source select bit1
0 0 : f1 0 1 : f8 1 0 : Selects Timer Y underflow 1 1 : f2 Must be set to "0"
Notes: 1. Avoid switching a count source, while a counter is in progress. Timer counter must be stopped before switching a count source.
Figure 12.21 PUM Register and TCSS Register
Rev.0.91
2003 Sep 08
page 90 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.3 Timer (Timer Z)
12.3.1 Timer Mode In this mode, the timer counts an internally generated count source or Timer Y underflow (see "Table 12.9 Timer Mode Specifications"). The TZSC register is unused in timer mode. Figure 12.22 shows the TYZMR register and PUM register in timer mode. Table 12.9 Timer Mode Specifications Item
Count source Count operation f1, f2, f8, Timer Y underflow * Down-count * When the timer underflows, it reloads the reload register contents before continuing counting (When the Timer Z underflows, the contents of the Timer Z primary reload register is reloaded.) Divide ratio Count start condition Count stop condition Interrupt request generation timing TZOUT pin function INT0 pin function Read from timer Write to timer1 fi/(n+1)(m+1) n: set value in PREZ register, m: set value in TZPR register Write "1" (count start) to TZS bit in TYZMR register Write "0" (count stop) to TZS bit in TYZMR register * When Timer Z underflows [Timer Z interrupt] * Rising, falling, or both edges of INT0 pin input [INT0 interrupt] Programmable I/O port Programmable I/O port, or external interrupt input pin Count value can be read out by reading TZPR register. Same applies to PREZ register. Value written to TZPR register is written to both reload register and counter or written to reload register only. Selected by program. Same applies to PREZ register. Notes: 1. The IR bit in the TZIC register is set to "1" (interrupt requested) if you write to the TZPR or PREZ register while both of the following conditions are met. * TZWC bit in TYZMR register is set to "0" (write to reload register and counter simultaneously) * TZS bit in TYZMR register is set to "1" (count start) To write to the TZPR or PREZ register in the above state, disable interrupts before the writing.
Specification
Rev.0.91
2003 Sep 08
page 91 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.3 Timer (Timer Z)
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol TYZMR
Address 008016
After reset 0016
Bit symbol
TYMOD0 R1EDG
Bit name
Timer Y-related bit
Function
RW RW RW RW RW
TYWC
TYS
b5 b4
TZMOD0 TZMOD1
Timer Z operation mode bit
0 0 : Timer mode
RW
RW Timer Z write control bit 1 Timer Z count start flag 0 : Write to reload register and counter 1 : Write to reload register only 0 : Stops counting 1 : Starts counting RW
TZWC
TZS
RW
Notes: 1. When TZS bit=1 (starts counting), the value set in the TZWC bit is valid. If TZWC bit=0, the timer Z count value is written to both reload register and counter. If TZWC bit=1, the timer Z count value is written to the reload register only. When TZS bit=0 (stops counting), the timer Z count value is written to both reload register and counter regardless of how the TZWC bit is set.
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
000
0000
Symbol PUM Bit symbol (b3-b0) TYOPL
Address 008416 Bit name Reserved bit
After reset 0016 RW RW
Function Must set to "0"
Timer Y-related bit
RW Must set to "0" in timer mode
TZOPL
Timer Z output level latch INT0 pin one-shot trigger control bit
RW
INOSTG
Must set to "0" in timer mode
RW
INOSEG
INT0 pin one-shot trigger Must set to "0" in timer mode polarity select bit
RW
Figure 12.22 TYZMR Register and PUM Register in Timer Mode
Rev.0.91
2003 Sep 08
page 92 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.3 Timer (Timer Z)
12.3.2 Programmable Waveform Generation Mode In this mode, an signal output from the TZOUT pin is inverted each time the counter underflows, while the values in the TZPR register and TZSC register are counted alternately (see "Table 12.10 Programmable Waveform Generation Mode Specifications"). A counting starts by counting the value set in the TZPR register. Figure 12.23 shows TYZMR and PUM registers in this mode. The Timer Z operates in the same way as the Timer Y in this mode. See Figure 12.17 (Timer Y operation ex ample in programmable waveform generation mode ). Table 12.10 Programmable Waveform Generation Mode Specifications Item Specification
Count source Count operation f1, f2, f8, Timer Y underflow * Down-count * When the timer underflows, it reloads the contents of primary reload register and secondary reload register alternately before continuing counting. fi/(n+1)((m+1)+(p+1)) n: set value in PREZ register, m: set value in TZPR register, p: set value in TZSC register Write "1" (count start) to the TZS bit in the TYZMR register
Period Count start condition
Count stop condition Write "0" (count stop) to the TZS bit in the TYZMR register Interrupt request generation timing In half of count source, after Timer Z underflows during secondary period (at the same TZOUT pin function
_____
time as the TZout output change) [Timer Z interrupt]. Pulse output1 Programmable I/O port, or external interrupt input pin Count value can be read out by reading TZPR register. Same applies to PREZ register2. Value written to TZPR register is written to reload register only. Same applies to TZSC register and PREZ register3. * Output level latch select function The output level during primary and secondary periods is selected by the TZOPL bit. * Programmable waveform generation output switching function When the TZOCNT bit in the TYZOC register is set to "0", the output from TZOUT is inverted synchronously when the Timer Z underflows during the secondary period. And when set to "1", a value in the P3_1 bit is output from TZOUT synchronously when the Timer Z underflows during the secondary period4.
INT0 pin functions Read from timer Write to timer Select function
Notes: 1. When the counting stopped, the output level is that in the secondary period. 2. Even when counting the secondary period, read out the TZPR register. 3. The set value in the TZPR register and TZSC register are made effective by writing a value to the TZPR register. The set values are reflected to the waveform output beginning with the next primary period after writing to the Timer Z primary register. 4. The output is switched in sync with timer Z underflow in the secondary period.
Rev.0.91
2003 Sep 08
page 93 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.3 Timer (Timer Z)
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
101
Symbol TYZMR
Address 008016
After reset 0016
Bit symbol
TYMOD0 R1EDG
Bit name
Timer Y-related bit
Function
RW RW RW RW RW
TYWC
TYS
b5 b4
TZMOD0 TZMOD1
Timer Z operation mode bit
0 1 : Programmable waveform generation mode
RW
RW Timer Z write control bit Set to "1" in programmable waveform generation mode 1 RW
TZWC
Timer Z count 0 : Stops counting TZS start flag 1 : Starts counting Notes: 1. When TZS bit= 1 (starts counting), the timer Y count value is written to the reload register only. When TZS bit=0 (stops counting), the timer Y count value is written to both reload register and counter .
RW
1 Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
00
00
00
Symbol PUM Bit symbol (b3-b0) TYOPL TZOPL
Address 008416 Bit name Reserved bit Timer Y-related bit Timer Z output level latch
After reset 0016 RW RW RW 0 : Outputs "H" for primary period Outputs "L" for secondary period Outputs "L" when the timer is stopped 1 : Outputs "L" for primary period Outputs "H" for secondary period Outputs "H" when the timer is stopped Must set to "0" in programmable waveform generation mode Must set to "0" in programmable waveform generation mode
Function Must set to "0"
RW
INOSTG
INT0 pin one-shot trigger control bit INT0 pin one-shot trigger polarity select bit
RW RW
INOSEG
Figure 12.23 TYZMR Register and PUM Register in Programmable Waveform Generation Mode
Rev.0.91
2003 Sep 08
page 94 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.3 Timer (Timer Z)
12.3.3 Programmable One-shot Generation Mode In this mode, upon program command or external trigger input (input to the INT0 pin), the microcomputer outputs the one-shot pulse from the TZOUT pin (see "Table 12.11 Programmable One-shot Generation Mode Specifications"). When a trigger occurs, the timer starts operating from the point only once for a given period equal to the set value in the TZPR register. The TZSC is unused in this mode. Figure 12.24 shows the TYZMR register and PUM register in this mode. Figure 12.25 shows an operation example in this mode. Table 12.11 Programmable One-shot Generation Mode Specifications Item
Count source Count operation f1, f2, f8, Timer Y underflow * Downcounts set value in TZPR register * When the timer underflows, it reloads the contents of reload register before stopping counting. * When a counting stops, the timer reloads the contents of the reload register before it Divide ratio Count start condition Count stop condition stops. fi/(n+1)(m+1) n: set value in PREZ register, m: set value in TZPR register * Set TZOS bit in TYZOC register to "1" (start one-shot) 1 * Input active trigger to INT0 pin2 * When reloading is completed after count value was set to "0016" * When TZS bit in TYZMR register is set to "0" (stop counting) * When TZOS bit in TYZOC register is set to "0" (stop one-shot) Interrupt request generation timing In half cycles of count source, after the timer underflows (at the same time as the TZout output ends) [Timer Z interrupt].
_______
Specification
TZOUT pin function INT0 pin function
Pulse output Programmable I/O port, external interrupt input pin, or external trigger input pin Count value can be read out by reading TZPR register. Same applies to PREZ register. Value written to TZPR register is written to reload register only3. Same applies to PREZ register. * Output level latch select function Output level for one-shot pulse waveform is selected by TZOPL bit. * INT0 pin one-shot trigger control function and polarity select function Trigger input from INT0 pin can be set to active or inactive by INOSTG bit. Also, an active trigger's polarity can be selected by INOSEG bit.
Read from timer Write to timer Select function
Notes: 1. The TZS bit in the TYZMR register must be set to "1" (start counting). _______ 2. The TZS bit must be set to "1" (start counting), the INT0EN bit in the INTEN register to "1" (enabling INT0 input), and _____ the INOSTG bit in the PUM register to "1" (enabling INT0 one-shot trigger).
Rev.0.91
2003 Sep 08
page 95 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.3 Timer (Timer Z)
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
110
Symbol TYZMR
Address 008016
After reset 0016
Bit symbol
TYMOD0 R1EDG
Bit name
Timer Y-related bit
Function
RW RW RW RW RW
TYWC
TYS
b5 b4
TZMOD0 TZMOD1
Timer Z operation mode bit
1 0 : Programmable one-shot generation mode
RW
RW Timer Z write control bit Timer Z count start flag Set to "1" in programmable one-shot generation mode 1 RW
TZWC
0 : Stops counting 1 : Starts counting Notes: 1. When TZS bit= 1 (starts counting), the timer Y count value is written to the reload register only. TZS
RW
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
00
00
Symbol PUM Bit symbol (b3-b0) TYOPL TZOPL
Address 008416 Bit name Reserved bit Timer Y-related bit Timer Z output level latch
After reset 0016 Function Must set to "0" RW RW RW 0 : Outputs "H" level one-shot pulse. Outputs "L" when the timer is stopped. 1 : Outputs "L" level one-shot pulse Outputs "H" when the timer is stopped. 0 : INT0 pin one-shot trigger disabled 1 : INT0 pin one-shot trigger enabled 2 0 : Edge trigger at falling edge 1 : Edge trigger at rising edge
RW
INOSTG
INT0 pin one-shot trigger control bit 2 INT0 pin one-shot trigger polarity select bit 1
RW
INOSEG
RW
Notes: 1. The INOSEG bit is valid only when the INT0PL bit in the INTEN register is set to "0" (one-edge). 2. The INOSGT bit must be set to "1" after the INT0EN bit the INOSEG register and the INOSEG bit in the PUM register are set. When setting the INOSTG bit to "1" (INT0 pin one-shot trigger enabled), the INT0F0 and INT0F1 bits in the INT0F register must be set. The INOSTG bit must be set to "0" (INT0 pin one-shot trigger disabled) after the TZS bit in the TYZMR register is set to "0" (count stop).
Figure 12.24 TYZMR Register and PUM Register in Programmable One-shot Generation Mode
Rev.0.91
2003 Sep 08
page 96 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.3 Timer (Timer Z)
Set to "1" by program
"1" TZS bit in TYZMR register "0"
Set to "1" by program Set to "0" when counting completed Set to "1" by INT0 pin input trigger
TZOS bit in TYZOC register
"1" "0"
Count source
Prescaler Z underflow signal
INT0 pin input
"1" "0"
Count starts Timer Z Count primary starts reloads Timer Z primary reloads
Contents of Timer Z
0116
0016
0116
0016
0116
Set to "0" when interrupt request i s accepted, or set to "0" by program
IR bit in TZIC "1" register "0"
Set to "0" by program
TZOPL bit in PUM register
"1" "0"
Waveform output starts
Waveform output ends
Waveform output starts
Waveform output ends
TZout pin output
"H" "L"
Conditions: PREZ=0116, TZPR=0316 PUM register TZOPL bit=0, INOSTG bit=1 (INT0 one-shot trigger enabled) INOSEG bit=1 (edge trigger at rising edge)
Figure 12.25 Operation Example in Programmable One-shot Generation Mode
Rev.0.91
2003 Sep 08
page 97 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.3 Timer (Timer Z)
12.3.4 Programmable Wait One-shot Generation Mode In this mode, upon program or external trigger input (input to the INT0 pin), the microcomputer outputs the one-shot pulse from the TZOUT pin after waiting for a given length of time (see "Table 12.12 Programmable Wait One-shot Generation Mode Specifications"). When a trigger occurs, from this point, the timer starts outputting pulses only once for a given length of time equal to the set value in the TZSC register after waiting for a given length of time equal to the set value in the TZPR register. Figure 12.26 shows the TYZMR and PUM registers in this mode. Figure 12.27 shows an operation example in this mode. Table 12.12 Programmable Wait One-shot Generation Mode Specifications Item
Count source Count operation f1, f2, f8, Timer Y underflow * Downcounts set value in Timer Z primary * When a counting of TZPR register underflows, the timer reloads the contents of TZSC register before continuing counting. * When a counting of TZSC register underflows, the timer reloads the contents of TZPR register before stopping counting. * When a counting stops, the timer reloads the contents of the reload register before it Wait time One-shot pulse output time Count start condition Count stop condition stops. fi/(n+1)(m+1) n: set value in PREZ register, m: set value in TZPR register
Specification
fi/(n+1)(p+1) n : set value in PREZ, p: set value in TZSC register * Set TZOS bit in TYZOC register to "1" (start one-shot)1 * Input active trigger to INT0 pin2 * When reloading is completed after Timer Z underflows during secondary period (at the same time as the TZout output ends) [Timer Z interrupt] * When TZS bit in TYZMR register is set to "0" (stop counting)
_______
Interrupt request generation timing TZOUT pin function
_______
* When TZOS bit in TYZOC register is set to "0" (stop one-shot) I n half cycles of count source, after count value at counting TZSC register is set "0016" (at the same time as the TZout output change) [Timer Z interrupt] Pulse output Programmable I/O port, external interrupt input pin, or external trigger input pin Count value can be read out by reading TZPR register. Same applies to PREZ register. Value written to TZPR register and PREZ register are written to reload register only 3. Same applies to TZSC register. * Output level latch select function Output level for one-shot pulse waveform is selected by TZOPL bit. _______ * INT0 pin one-shot trigger control function and polarity select function
_______
INT0 pin function Read from timer Write to timer Select function
Trigger input from INT0 pin can be set to active or inactive by INOSTG bit. Also, an active trigger's polarity can be selected by INOSEG bit. Notes: 1. The TZS bit in the TYZMR register must be set to "1" (start counting). _______ 2. The TZS bit must be set to "1" (start counting), the INT0EN bit in the INTEN register to "1" (enabling INT0 input), and _____ the INOSTG bit in the PUM register to "1" (enabling INT0 one-shot trigger). 3. The set values are reflected beginning with the next one-shot pulse after writing to the TZPR register.
Rev.0.91
2003 Sep 08
page 98 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.3 Timer (Timer Z)
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
111
Symbol TYZMR
Address 008016
After reset 002
Bit symbol
TYMOD0 R1EDG
Bit name
Timer Y-related bit
Function
RW RW RW RW RW
TYWC
TYS
b5 b4
TZMOD0 TZMOD1
Timer Z operation mode bit
1 1 : Programmable wait one-shot generation mode
RW
RW Timer Z write control bit Timer Z count start flag Must set to "1" in programmable wait one-shot generation mode 0 : Stops counting 1 : Starts counting RW
TZWC
TZS
RW
Notes: 1. When the TZS bit is set to "0" (stop counting), the timer reloads the content of the reload register before it stops. Read out the count value before you stop the timer. 1
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
00
00
Symbol PUM Bit symbol (b3-b0) TYOPL TZOPL
Address 008416 Bit name Reserved bit Timer Y-related bit Timer Z output level latch
After reset 0016 Function Must set to "0" RW RW RW 0 : Outputs "H" level one-shot pulse. Outputs "L" when the timer is stopped. 1 : Outputs "L" level one-shot pulse Outputs "H" when the timer is stopped. 0 : INT0 pin one-shot trigger disabled 1 : INT0 pin one-shot trigger enabled 2 0 : Edge trigger at falling edge 1 : Edge trigger at rising edge
RW
INOSTG
INT0 pin one-shot trigger control bit 2 INT0 pin one-shot trigger polarity select bit 1
RW
INOSEG
RW
Notes: 1. The INOSEG bit is valid only when the INT0PL bit in the INTEN register is set to "0" (one-edge). 2. The INOSGT bit must be set to "1" after the INT0EN bit the INOSEG register and the INOSEG bit in the PUM register are set. When setting the INOSTG bit to "1" (INT0 pin one-shot trigger enabled), the INT0F0 and INT0F1 bits in the INT0F register must be set. The INOSTG bit must be set to "0" (INT0 pin one-shot trigger disabled) after the TZS bit in the TYZMR register is set to "0" (count stop).
Figure 12.26 TYZMR Register and PUM Register in Programmable Wait One-shot Generation Mode
Rev.0.91
2003 Sep 08
page 99 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.3 Timer (Timer Z)
Set to "1" by program
TZS bit TYZMR "1" register "0"
Set to "1" by program, or set to "1" by INT0 pin input trigger
Set to "0" when counting completed
"1" TZOS bit in TYZOC register "0"
Count source
Prescaler Z underflow signal
INT0 pin input
"1" "0"
Count starts Timer Z secondary reloads Timer Z primary reloads
Contents of Timer Z
0116
0016
0216
0116
0016
0116
Set to "0" when interrup request is accepted, or set by program
IR bit in TZIC "1" register "0"
Set to "0" by program
TZOPL bit in PUM register
"1" "0"
Wait starts
Waveform output starts
Waveform output ends
TZout pin output
"H" "L"
Conditions: PREZ=0116, TZSC=0216 PUM register TZOPL bit=0, INOSTG bit=1 (INT0 one-shot trigger enabled) INOSEG bit= 1 (edge trigger at rising edge)
Figure 12.27 Operation Example in Programmable Wait One-shot Generation Mode
Rev.0.91
2003 Sep 08
page 100 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.4 Timer (Timer C)
12.4 Timer C
Timer C is a 16-bit timer. Figure 12.28 shows a block diagram of Timer C. Figure 12.29 shows a block diagram of PWM waveform generation unit. Figure 12.30 shows a block diagram of PWM waveform output unit. The Timer C has two modes: input capture mode and output compare mode. Figures 12.31 shows TC, TM0, TM1, and TCC0 registers. Figure 12.32 shows TCC1 and TCOUT registers.
f1 f8 f32 INT3/TCIN
TCC11 to TCC10 =012 =102 =112 Other than 002 =002 TCC07=0
Digital filter
Edge detection
TCC07=1
INT3 interrupt
fRING128
Transfer signal
Upper 8 bits Lower 8 bits Capture and compare 0 register TM0 register Compare circuit 0
Data bus
Compare 0 interrupt
f32 fRING-fast
TCC02 to TCC01 =002 f1 =012 f8 =102
=112
TCC00
Upper 8 bits Lower 8 bits Counter TC register TCC12
=0
Timer C interrupt
TCC12 =1 Timer C counter reset signal
Compare circuit 1
Compare 1 interrupt
Upper 8 bits Lower 8 bits Compare register 1 TM1 register TCC01 to TCC02, TCC07: Bits in TCC0 register TCC10 to TCC12: Bits in TCC1 register
Figure 12.28 Timer C Block Diagram
Rev.0.91
2003 Sep 08
page 101 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.4 Timer (Timer C)
TCC14 TCC15 Compare 0 interrupt signal Compare 1 interrupt signal TCC16 TCC17 H L Reverse TCC17 to TCC16 =112 =102 =012 T D Latch R Reset
Q
PWM output (internal signal)
Reverse L H
TCC15 to TCC14 =012 =102 =112
TCC14 to TCC17: Bits in TCC1 register
Figure 12.29 CMP Waveform Generation Unit
CMP output (internal signal)
TCOUT6=0 TCOUT0=1 inverted TCOUT6=1
PD1_0 TCOUT0 CMP00
P1_0
TCOUT0=0
Figure 12.30 CMP Waveform Output Unit
Rev.0.91
2003 Sep 08
page 102 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.4 Timer (Timer C)
Timer C register
(b15) b7 (b8) b0 b7 b0
Symbol TC
Address 009116-009016
After reset 000016
Function Internal count source is counted "000 16" can be read out by reading when TCC00 bit = 0 (stops counting) Count value can be read out by reading when TCC00 bit = 1 (start counting)
RW RO
Capture and compare 0 register
(b15) b7 (b8) b0 b7 b0
Symbol TM0 Mode Input capture mode Output compare mode
Address 009D16-009C16 Function
After reset Indeterminate RW RO RW
When active edge of measurement pulse is input, the value of Timer C is stored The value compared with Timer C is stored
Compare 1 register
(b15) b7 (b8) b0 b7 b0
Symbol TM1 Mode Output compare mode1
Address 009F16-009E16 Function
After reset Indeterminate RW RW
The value compared with Timer C is stored
Notes: 1. Disabled when the TCC13 bit in the TCC1 register is set to "0" (input capture mode).
Timer C control register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol TCC0
Address 009A16
After reset 0016
Bit symbol
TCC00
Bit name
Timer C control bit Timer C count source select bit1
Function
0 : Count stop 1 : Count start
b2 b1
RW RW RW RW RW RW RW
TCC01 TCC02 TCC03 TCC04
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fRING-fast
b4 b3
INT3 interrupt and capture polarity select bit 1, 2
0 0 : Rising edge 0 1 : Falling edge 1 0 : Both edges 1 1 : Avoid this setting Must set to "0"
Reserved bit (b6-b5) TCC07 INT3 interrupt/capture input switching bit 1, 2
0 : INT3 1 : fRING128
RW
Notes: 1. Change this bit when TCC00 bit is set to "0" (count stop). 2. The IR bit in the INT3IC may be set to "1" (interrupt requested) when the TCC03, TCC04, or TCC07 bit is rewritten. Refer to the paragraph 19.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book.
Figure 12.31 TC Register, TM0 Register, TM1 Register, TCC0 Register
Rev.0.91 2003 Sep 08 page 103 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.4 Timer (Timer C)
Timer C control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TCC1
Address 009B16
After reset 0016
Bit symbol
TCC10 TCC11 TCC12
Bit name
INT3 input filter select bit 1
b1 b0
Function
0 0 1 1 0: No filter 1: Filter with f 1 sampling 0: Filter with f 8 sampling 1: Filter with f 32 sampling
RW RW RW RO
Timer C counter reload select bit 2, 3 Compare 0/Capture select bit
0: No reload (free-run) 1: Set TC register to "0000 16" at compare 1 match 0: Capture (input capture mode) 2 1: Compare 0 output (output compare mode)
b5 b4
TCC13
RW
TCC14
Compare 0 output mode select bit 3
TCC15
0 0: CMP0 output remains unchanged even when compare 0 signal matched 0 1: CMP0 output is reversed when compare 0 signal is matched 1 0: CMP0 output is set to low when compare 0 signal is matched 1 1: CMP0 output is set to high when compare 0 signal is matched
RW
TCC16
Compare 1 output mode select bit 3
b7 b6
RW
TCC17
0 0: CMP1 output remains unchanged even when compare 1 signal matched 0 1: CMP1 output is reversed when compare 1 signal is matched 1 0: CMP1 output is set to low when compare 1 signal is matched 1 1: CMP1 output is set to high when compare 1 signal is matched
Notes: 1. Input is recognized only when the same value from INT3 pin is sampled three times in succession. 2. The TCC00 bit in the TCC0 register should be set to "0" (count stop) when rewriting the TCC13 bit. 3. The TCC12 and TCC14 to TCC17 should be set to "0" when the TCC13 bit is "0" (input capture mode).
Timer C output control register1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TCOUT
Address 00FF16
After reset 0016
Bit symbol
TCOUT0 TCOUT1 TCOUT2 TCOUT3 TCOUT4 TCOUT5 TCOUT6
Bit name
CMP output enable bit 0 CMP output enable bit 1 CMP output enable bit 2 CMP output enable bit 3 CMP output enable bit 4 CMP output enable bit 5 CMP output reverse bit 0
Function
0: Disable CMP output from CMP0 0 1: Enable CMP output from CMP0 0 0: Disabe CMP output from CMP0 1 1: Enable CMP output from CMP0 1 0: Disable CMP output from CMP0 2 1: Enable CMP output from CMP0 2 0: Disable CMP output from CMP1 0 1: Enable CMP output from CMP1 0 0: Disable CMP output from CMP1 1 1: Enable CMP output from CMP1 1 0: Disable CMP output from CMP1 2 1: Enable CMP output from CMP1 2 0: Not reverse CMP output from CMP00 to CMP02 1: Reverse CMP output from CMP 00 to CMP02 0: Not reverse CMP output from CMP10 to CMP12 1: Reverse CMP output from CMP10 to CMP12
RW RW RW RW RW RW RW
RW
TCOUT7
CMP output reverse bit 1
RW
Notes: 1. Invalid when the TCC13 bit in the TCC1 register is set to "0" (input capture mode).
Figure 12.32 TCC1 Register and TCOUT Register
Rev.0.91 2003 Sep 08 page 104 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.4 Timer (Timer C)
12.4.1 Input Capture Mode This mode uses an edge input to TCIN pin or the fRING128 clock as trigger to latch the timer value and generates an interrupt request. The TCIN input has a digital filter and this prevents an error caused by noise or so on from occurring. Table 12.13 shows specifications in input capture mode. Figure 12.33 shows an operation example of input capture mode.
Table 12.13 Input Capture Mode Specifications Item
Count source Count operation f1, f8, f32, fRING-fast * Count up
Specification
Count start condition Counter stop condition Interrupt request generation timing ______ INT3/TCIN pin function Counter value reset timing Read from timer1
* Transfer value in TC register to TM0 register at active edge of measurement pulse * Value in TC register is set to "000016" when a counting stops TCC00 bit in TCC0 register is set to "1" (count start) TCC00 bit in TCC0 register is set to "0" (count stop)
_____
* When active edge of measurement pulse is input [INT3 interrupt]2 * When Time C overflows [Timer C interrupt] I/O port or measurement pulse input When TCC00 bit in TCC0 register is set to "0" (capture disabled) * Count value can be read out by reading TC register. * Count value at measurement pulse active edge input can be read out by reading TM0 register. Write to TC register and TM0 register is disabled
_____
Write to timer Select function
* INT3/TCIN polarity select function Measurement pulse active edge is selected by TCC03 to TCC04 bits * Digital filter function Digital filter sampling frequency is selected by TCC11 to TCC10 bits * Trigger select function TCIN input or fRING128 is selected by TCC07 bit.
Notes: 1. TC register and TM0 register must be read in 16-bit units. 2. The INT3 interrupt is acknowledged by digital filter delay and one count source delay (max.)
Rev.0.91
2003 Sep 08
page 105 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.4 Timer (Timer C)
FFFF16
Overflow
Counter contents (hex)
Count start
Measurement value 2
Measurement value 1
Measurement value 3
000016
Set to "1" by program TCC00 bit in TCC0 "1" register "0"
Time Set to "0" by program
The delay caused by digital filter count source cycle (max.)
Measurement pulse "H" (TCIN pin input) "L"
Transmit Transmit (Measurement (Measurement value 1) value 2)
Transmit (Measurement value 3)
Transmit timing from Timer C counter to TM0 register Indeterminate TM0 register Measurement value 1 Measurement value 2 Measurement value 3 Indeterminate
Set to "0" when interrupt request is accepted, or set by program IR bit in INT3IC "1" register "0" Set to "0" when interrupt request is accepted, or set by program IR bit in TCIC "1" register "0" Conditions: TCC0 register TCC04 to TCC03 bits=012 (capture input polarity is set for falling edge), TCC07=0 (INT3/TCIN input as capture input trigger)
Figure 12.33 Operation Example of Timer C in Input Capture Mode
Rev.0.91
2003 Sep 08
page 106 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.4 Timer (Timer C)
12.4.2 Output Compare Mode In this mode, an interrupt request is generated when the value of TC register matches the value of TM0 or TM1 register. Table 12.14 shows specifications in output compare mode. Figure 12.34 shows an operation example of output compare mode. Table 12.14 Output Compare Mode Specifications Item
Count source Count operation Count start condition Counter stop condition Waveform output start condition Waveform output stop condition Interrupt request generation timing
______
Specification
f1, f8, f32, fRING-fast * Count up * Value in TC register is set to "000016" when a counting stops TCC00 bit in TCC0 register is set to "1" (count start) TCC00 bit in TCC0 register is set to "0" (count stop) When "1" (CMP output enabled) is written to TCOUT0 to TCOUT5 bits.2 When "0" (CMP output disabled) is written to TCOUT0 to TCOUT5 bits. * When a match occurs in compare circuit 0 [compare 0 interrupt] * When a match occurs in compare circuit 1 [compare 1 interrupt] * When Time C overflows [Timer C interrupt] I/O port
INT3/TCIN pin function
P10 to P12 pins and P30 to I/O port or CMP output2 P32 pins function Counter value reset timing When TCC00 bit in TCC0 register is set to "0" (count stop) Read from timer1 * Value in compare register can be read out by reading TM0 register and TM1 register. Write to timer * Count value can be read out by reading TC register. * Write to TC register is disabled. * Values written to TM0 register and TM1 register are stored in compare register at the following timings: - When TM0 and TM1 registers are written if TCC00 bit is "0" (count stop) - When counter overflows if TCC00 bit is "1" (in counting) and TCC12 bit in TCC1 register is "0" (free-run) - When compare 1 matches counter if TCC00 bit is "1" and TCC12 bit is "1" (set TC Select function register to "000016" at compare 1 match) * Timer C counter reload select function Counter value in TC register at match occurrence in compare circuit 1 is set or not set to "000016" selected by TCC12 bit in TCC1 register. * Output level at match occurrence in compare circuit 0 can be selected by TCC15 to TCC14 bits in TCC1 register. Similarly, output level at match occurrence in compare circuit 1 can be selected by TCC17 to TCC16 bits in TCC1 register. * Whether output is reversed or not can be selected by TCOUT1 to TCOUT0 bits in TCOUT register. Notes: 1. TC, TM0, and TM1 registers should be accessed in 16-bit units. 2. These pins function as the CMP output pin only when the P1_i bit in the P1 register and the P3_i bit in the P3 register are set to "1" (high). (i=0 to 2)
Rev.0.91
2003 Sep 08
page 107 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
12.4 Timer (Timer C)
Match Set value in TM1 register
Counter content (hex)
Count start Set value in TM0 register
Match
Match
000016 Time Set to "1" by program
TCC00 bit in TCC0 register
"1" "0" Set to "0" when interrupt request is accepted, or set by program
IR bit in CMP0IC register
"1" "0" Set to "0" when interrupt request is accepted, or set by program
IR bit in CMP1IC register
"1" "0"
"1" CMP00 output "0"
CMP10 output
"1" "0"
The above applies to the following conditions. TCC12 bit in TCC1 register=1 (TC register is set to "0000 16" at Compare 1 match occurrence ) TCC13 bit in TCC1 register=1 (Compare 0 output selected) TCC15 to TCC14 bits in TCC1 register =11 2 (CMP output level is set to high at Compare 0 match occurrence) TCC17 to TCC16 bits in TCC1 register=10 2 (CMP output level is set to low at Compare 1 match occurrence) TCOUT6 bit in TCOUT register=0 (not reversed) TCOUT7 bit in TCOUT register =1 (reversed) TCOUT0 bit in TCOUT register=1 (CMP0 0 output enabled) TCOUT4 bit in TCOUT register=1 (CMP1 0 output enabled) P1_0 bit in P1 register=1 (high) P3_0 bit in P3 register=1 (high)
Figure 12.34 Operation Example of Timer C in Output Compare Mode
Rev.0.91
2003 Sep 08
page 108 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
13. Serial I/O
13. Serial I/O
Serial I/O is configured with two channels: UART0 to UART1. UART0 and UART1 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 13.1 shows a block diagram of UARTi (i=0, 1). Figure 13.2 shows a block diagram of the UARTi transmit/receive. UART0 has two modes: clock synchronous serial I/O mode, and clock asynchronous serial I/O mode (UART mode). UART1 has only one mode, clock asynchronous serial I/O mode (UART mode). Figures 13.3 to 13.5 show the UARTi-related registers.
Main clock or ring oscillator clock
1/8 1/4
f1SIO f8SIO f32SIO
(UART0)
RxD0 1/16 CLK1 to CLK0=002 UART reception Clock synchronous type U0BRG register 1/(n0+1) External 1/16 UART transmission Clock synchronous type Transmission control circuit Transmit clock Reception control circuit Receive clock Transmit/ receive unit TxD0
f1SIO =012 f8SIO f32SIO =102
Internal
Clock synchronous type (when internal clock is selected) 1/2
CKDIR=0
Clock synchronous type CKDIR=1 (when external clock is selected)
Clock synchronous type (when internal clock is selected) CLK0 CLK polarity reversing circuit
(UART1)
TXD1EN
RxD1 UART reception 1/16 CLK1 to CLK0=002 Reception control circuit
TxD10
f1SIO =012 f8SIO f32SIO =102
Internal
U1BRG register
UART transmission 1/(n1+1) 1/16
Reception control circuit
Transmit/ receive unit
TXD1SEL=1 TxD11 TXD1SEL=0
Transmission control circuit
Transmission control circuit
To P00
Figure 13.1 UARTi (i=0, 1) Block Diagram
Rev.0.91
2003 Sep 08
page 109 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
13. Serial I/O
Clock synchronous type Clock PRYE=0 synchronous PAR type disabled UART (7 bits) UART (8 bits) UART (7 bits)
UARTi receive register
1SP
RxDi
SP 2SP
SP
PAR
UART PAR enabled PRYE=1
UART (9 bits)
Clock synchronous type UART (8 bits) UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiRB register
MSB/LSB conversion circuit
Data bus high-order bits Data bus low-order bits
MSB/LSB conversion circuit
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiTB register
UART (8 bits) UART (9 bits) PRYE=0 PAR enabled
PAR
UART (9 bits) UART
Clock synchronous type
2SP SP SP 1SP
TxDi
PAR Clock disabled synchronous PRYE=1 type UART (7 bits) UART (8 bits) Clock synchronous type UART (7 bits)
UARTi transmit register
"0"
i=0, 1 SP: Stop bit PAR: Parity bit Note: Clock synchronous type is provide in UART0 only.
Figure 13.2 UARTi Transmit/Receive Unit
Rev.0.91
2003 Sep 08
page 110 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
13. Serial I/O
UARTi transmit buffer register1, 2 (i=0, 1)
(b15) b7 (b8) b0 b7 b0
Symbol U0TB U1TB
Address 00A316-00A216 00AB16-00AA16
After reset Indeterminate Indeterminate
Function Transmit data Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Notes: 1. When transfer data length is 9-bit long, write high-byte first then low-byte. 2. Use MOV instruction to write to this register.
RW WO
UARTi receive buffer register1 (i=0, 1)
(b15) b7 (b8) b0 b7 b0
Symbol U0RB U1RB
Address 00A716-00A616 00AF16-00AE16
After reset Indeterminate Indeterminate
Bit symbol (b7-b0) (b8) (b11-b9) OER FER PER SUM
Bit name Receive data (D 7 to D0) Receive data (D 8)
Function
RW RO RO
Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Overrun error flag 2 Framing error flag 2 Parity error flag 2 Error sum flag 2 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found RO RO RO
RO
Notes: 1. Be sure to read UiRB register in 16-bit unit. 2. All of the SUM, PER, FER and OER bits are set to "0" (no error) when the SMD2 to SMD0 bits in the UiMR register are set to "000 2" (serial I/O disabled) or the RE bit in the UiC1 register is set to "0" (reception disabled). The SUM bit is set to "0" (no error) when all of the PER, FER and OER bits are set to "0" (no error). The PER and FER bits are set to "0" even when the higher byte of the UiRB register is read.
UARTi baud rate generation register1, 2 (i=0, 1)
b7 b0
Symbol U0BRG U1BRG
Address 00A116 00A916
After reset Indeterminate Indeterminate
Function Assuming that set value = n, UiBRG divides the count source by n + 1 Notes: 1. Write to this register while serial I/O is neither transmitting nor receiving. 2. Use MOV instruction to write to this register.
Setting range 0016 to FF16
RW WO
Figure 13.3 U0TB and U1TB Registers, U0RB and U1RB Registers, and U0BRG and U1BRG Registers
Rev.0.91
2003 Sep 08
page 111 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
13. Serial I/O
UARTi transmit/receive mode register (i=0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
0 Bit symbol SMD0 SMD1 SMD2
Symbol U0MR U1MR Bit name Serial I/O mode select bit2
Address 00A016 00A816
After reset 0016 0016 Function RW RW RW RW RW RW RW RW RW
b2 b1 b0
0 0 0 : Serial I/O disabled 0 0 1 : Clock synchronous serial I/O mode 1 0 0 : UART mode transfer data 7 bits long 1 0 1 : UART mode transfer data 8 bits long 1 1 0 : UART mode transfer data 9 bits long Must not be set except above 0 : Internal clock 1 : External clock1 0 : One stop bit 1 : Two stop bits
CKDIR Internal/external clock select bit3 STPS PRY Stop bit length select bit
Odd/even parity select bit Effective when PRYE = 1 0 : Odd parity 1 : Even parity Parity enable bit 0 : Parity disabled 1 : Parity enabled
PRYE
Must set to "0" Reserved bit (b7) Notes: 1. Must set the P1_6 bit in the PD1 register to "0" (input). 2. For the U1MR register, the SMD2 to SMD0 bits must not be set except the followings: "0002", "1002", "1012", or "1102". 3. Must set the CKDIR bit to "0" (internal clock) in UART1.
UARTi transmit/receive control register 0 (i=0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol U0C0 U1C0 Bit symbol CLK0 CLK1 Bit name BRG count source select bit
Address 00A416 00AC16
After reset 0816 0816 Function RW RW RW
b1 b0
0 0 : f1SIO is selected 0 1 : f8SIO is selected 1 0 : f32SIO is selected 1 1 : Avoid this setting Must set to "0"
(b2) TXEPT
Reserved bit
RW
Transmit register empty flag
0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed)
RO
(b4)
Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0 : TxDi pin is CMOS output 1 : TxDi pin is N-channel open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge
NCH CKPOL
Data output select bit
RW
CLK polarity select bit
RW
UFORM Transfer format select bit 0 : LSB first 1 : MSB first
RW
Figure 13.4 U0MR and U1MR Registers and U0C0 and U1C0 Registers
Rev.0.91
2003 Sep 08
page 112 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
13. Serial I/O
UARTi transmit/receive control register 1 (i=0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0C1 U1C1 Bit symbol TE TI RE RI
Address 00A516 00AD16
After reset 0216 0216 Function
Bit name Transmit enable bit Transmit buffer empty flag Receive enable bit1 Receive complete flag2
RW
0 : Transmission disabled 1 : Transmission enabled 0 : Data present in UiTB register 1 : No data present in UiTB register 0 : Reception disabled 1 : Reception enabled 0 : No data present in UiRB register 1 : Data present in UiRB register
RW RO RW RO
(b7-b4)
Nothing is assigned. When write, set "0". When read, its content is "0".
Notes: 1. As for the UART1, set the TXD1EN bit in the UCON register before setting this bit to reception enabled. 2. The RI bit is set to "0" when the higher byte of the UiRB register is read.
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol UCON
Address 00B016
After reset 0016
Bit symbol U0IRS
Bit name UART0 transmit interrupt cause select bit UART1 transmit interrupt cause select bit UART0 continuous receive mode enable bit Reserved bit
Function 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enable Must set to "0" 0 : I/O port P00 1 : TxD11 0 : RxD1 1 : TxD10
RW
RW
U1IRS
RW RW RW RW
U0RRM
(b4-b3)
TXD1SEL Port TxD11 switching bit
TXD1EN
TxD10/RxD1 select bit
RW
(b7)
Nothing is assigned. When write, set "0". When read, its content is "0".
Notes 1. For P37, select "0" (RxD1) for data receive, and "1" (TxD10) for data transfer. Set the PD3_7 bit in the PD3 register to "0" (input mode) when receiving.
Figure 13.5 U0C1 and U1C1 Registers and UCON Register
Rev.0.91
2003 Sep 08
page 113 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
13.1 Clock Synchronous Serial I/O Mode
13.1 Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. This mode can be selected with UART0. Table 13.1 lists the specifications of the clock synchronous serial I/O mode. Table 13.2 lists the registers used in clock synchronous serial I/O mode and the register values set. Table 13.1 Clock Synchronous Serial I/O Mode Specifications
Item Transfer data format Transfer clock * Transfer data length: 8 bits * CKDIR bit in U0MR register is set to "0" (internal clock): fi/ 2(n+1) fi=f1SIO, f8SIO, f32SIO n=setting value in UiBRG register: 0016 to FF16 * CKDIR bit is set to "1" (external clock ): input from CLK0 pin * Before transmission can start, the following requirements must be met1
_ _
Specification
Transmission start condition
TE bit in U0C1 register is set to "1" (transmission enabled) TI bit in U0C1 register is set to "0" (data present in U0TB register)
Reception start condition
* Before reception can start, the following requirements must be met1 _ RE bit in U0C1 register is set to "1" (reception enabled)
_ _
TE bit in U0C1 register is set to "1" (transmission enabled) TI bit in U0C1 register is set to "0" (data present in the U0TB register)
Interrupt request generation timing
* For transmission, one of the following conditions can be selected _ U0IRS bit is set to "0" (transmit buffer empty): when transferring data from
_
U0TB register to UART0 transmit register (at start of transmission) U0IRS bit is set to "1" (transfer completed): when serial I/O finished sending data
from UARTi transmit register * For reception When transferring data from the UART0 receive register to the U0RB register (at completion of reception) Error detection * Overrun error2 This error occurs if serial I/O started receiving the next data before reading the U0RB register and received the 7th bit of the next data * CLK polarity selection Transfer data input/output can be chosen to occur synchronously with the rising or the falling edge of the transfer clock * LSB first, MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected * Continuous receive mode selection Reception is enabled immediately by reading the U0RB register Notes:
Select function
1. When an external clock is selected, the conditions must be met while if the U0C0 register0 CKPOL bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the CKPOL bit in the U0C0 register is set to "1" (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. 2. If an overrun error occurs, the value of U0RB register will be indeterminate. The IR bit of S0RIC register does not change.
Rev.0.91
2003 Sep 08
page 114 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
13.1 Clock Synchronous Serial I/O Mode
Table 13. 2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register U0TB U0RB U0BRG U0MR U0C0 Bit 0 to 7 0 to 7 OER 0 to 7 SMD2 to SMD0 CKDIR CLK1 to CLK0 TXEPT NCH CKPOL UFORM U0C1 TE TI RE RI UCON U0IRS U0RRM TXDISEL TXDIEN Function Set transmission data Reception data can be read Overrun error flag Set a transfer rate Set to "0012" Select the internal clock or external clock Select the count source for the U0BRG register Transmit register empty flag Select TxD0 pin output mode Select the transfer clock polarity Select the LSB first or MSB first Set this bit to "1" to enable transmission/reception Transmit buffer empty flag Set this bit to "1" to enable reception Reception complete flag Select the source of UART0 transmit interrupt Set this bit to "1" to use continuous receive mode Set to "0" Set to "0"
Notes: 1. Not all register bits are described above. Set those bits to "0" when writing to the registers in clock synchronous serial I/O mode.
Table 13.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note that for a period from when the UART0 operation mode is selected to when transfer starts, the TxD0 pin outputs an "H". (If the Nch bit is set to "1", this pin is in a high-impedance state.) Table 13.3 Pin Functions
Pin name TxD0 (P14) RxD0 (P15) CLK0 (P16) Function Serial data output Serial data input Transfer clock output Transfer clock input Method of selection (Outputs dummy data when performing reception only) PD1 register PD1_5 bit=0 (P15 can be used as an input port when performing transmission only) U0MR register CKDIR bit=0 U0MR register CKDIR bit=1 PD1 register PD1_6 bit=0
Rev.0.91
2003 Sep 08
page 115 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
13.1 Clock Synchronous Serial I/O Mode
* Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
U0C1 register "1" TE bit "0" U0C1 register "1" TI bit
"0"
Write data to U0TB register
Transferred from U0TB register to UART0 transmit register
TCLK
Stopped pulsing because the TE bit = 0
CLK0
TxD0 U0C0 register "1" TXEPT bit
"0"
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
S0TIC register "1" IR bit
"0"
Set to "0" when interrupt request is accepted, or set by a program Tc = TCLK = 2(n + 1) / fi fi: frequency of U0BRG count source (f1SIO, f8SIO, f32SIO) n: value set to U0BRG register The above timing diagram applies to the case where the register bits are set as follows: * U0MR register CKDIR bit = 0 (internal clock) * U0C0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) * U0IRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty):
* Example of receive timing (when external clock is selected)
U0C1 register RE bit U0C1 register TE bit U0C1 register TI bit
"1" "0" "1" "0" "1" "0"
Write dummy data to U0TB register
Transferred from U0TB register to UART0 transmit register
1 / fEXT
CLK0
Receive data is taken in
RxD0 U0C1 register RI bit S0RIC register IR bit
"1" "0" "1" "0"
D0 D1 D2 D3 D4 D5 D6 D7
Transferred from UART0 receive register to U0RB register
D0 D1 D2
D3 D4 D5
Read out from U0RB register
Set to "0" when interrupt request is accepted, or set by a program The above timing diagram applies to the case where the register bits are set as follows: * U0MR register CKDIR bit = 1 (external clock) * U0C0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) Make sure the following conditions are met when input to the CLK0 pin before receiving data is high: * U0C1 register TE bit = 1 (transmit enabled) * U0C1 register RE bit = 1 (receive enabled) * Write dummy data to the U0TB register fEXT: frequency of external clock
Figure 13.6 Transmit and Receive Operation
Rev.0.91 2003 Sep 08 page 116 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
13.1 Clock Synchronous Serial I/O Mode
13.1.1 Polarity Select Function Figure 13.7 shows the polarity of the transfer clock. Use the CKPOL bit in the U0C0 register to select the transfer clock polarity.
(1) When the U0C0 register CKPOL bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock)
CLK01 TXD0 RXD0 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
(2) When the U0C0 register CKPOL bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock)
CLK02 TXD0 RXD0 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Notes: 1. When not transferring, the CLK0 pin outputs a high signal. 2. When not transferring, the CLK0 pin outputs a low signal.
Figure 13.7 Transfer Clock Polarity 13.1.2 LSB First/MSB First Select Function Figure 13.8 shows the transfer format. Use the UFORM bit in the U0C0 register to select the transfer format.
(1) When U0C0 register UFORM bit = 0 (LSB first)
CLK0 TXD0 RXD0 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
(2) When U0C0 register UFORM bit = 1 (MSB first)
CLK0 TXD0 RXD0 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
Note: This applies to the case where the CKPOL bit in the U0C0 register is set to "0" (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock).
Figure 13.8 Transfer Format
Rev.0.91 2003 Sep 08 page 117 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
13.1 Clock Synchronous Serial I/O Mode
13.1.3 Continuous Receive Mode The unit is configured to continuous receive mode by setting the U0RRM bit in the UCON register to "1" (enabling continuous receive mode). In this mode, reading the U0RB register enables data reception without resetting dummy data to the U0TB register. When the U0RRM bit is set to "1", avoid writing dummy data to U0TB register in a program.
Rev.0.91
2003 Sep 08
page 118 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
13.2 Clock Asynchronous Serial I/O (UART) Mode
13.2 Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 13.4 lists the specifications of the UART mode. Table 13.5 lists the registers and settings for UART mode.
Table 13.4 UART Mode Specifications
Item Transfer data format Specification * Character bit (transfer data): selectable from 7, 8 or 9 bits * Start bit: 1 bit * Parity bit: selectable from odd, even, or none * Stop bit: selectable from 1 or 2 bits * UiMR(i=0, 1) register CKDIR bit = 0 (internal clock) : fj/ 16(n+1) fj=f1SIO, f8SIO, f32SIO n=setting value in UiBRG register: 0016 to FF16 * CKDIR bit = "1" (external clock) : fEXT/16(n+1) fEXT: input from CLKi pin n=setting value in UiBRG register: 0016 to FF16 * Before transmission can start, the following requirements must be met _ TE bit in UiC1 register= 1 (transmission enabled) _ TI bit in UiC1 register = 0 (data present in UiTB register) * Before reception can start, the following requirements must be met _ RE bit in UiC1 register= 1 (reception enabled) _ Start bit detection * For transmission, one of the following conditions can be selected _ UiIRS bit = 0 (transmit buffer empty): when transferring data from UiTB register to UARTi transmit register (at start of transmission) _ UiIRS bit =1 (transfer completed): when serial I/O finished sending data from UARTi transmit register * For reception When transferring data from UARTi receive register to UiRB register (at completion of reception) * Overrun error1 This error occurs if serial I/O started receiving the next data before reading UiRB register and received the bit one before the last stop bit of the next data * Framing error This error occurs when the number of stop bits set is not detected * Parity error This error occurs when if parity is enabled, the number of 1's in parity and character bits does not match the number of 1's set * Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered * TXD10, RXD1 selection (UART) P37 pin can be used as RxD1 pin or TxD10 pin in UART1. Select by a program. * TxD11 pin selection (UART1) P00 pin can be used as TxD11 pin in UART1 or port P00. Select by a program.
Transfer clock
Transmission start condition
Reception start condition
Interrupt request generation timing
Error detection
Select function
Notes: 1. If an overrun error occurs, the value of U0RB register will be indeterminate. The IR bit in the S0RIC register does not change.
Rev.0.91
2003 Sep 08
page 119 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
13.2 Clock Asynchronous Serial I/O (UART) Mode
Table 13.5 Registers to Be Used and Settings in UART Mode
Register UiTB UiRB UiBRG UiMR Bit 0 to 8 0 to 8 --SMD2 to SMD0 Function Set transmission data1 Reception data can be read1 Set a transfer rate Set these bits to `1002' when transfer data is 7 bits long Set these bits to `1012' when transfer data is 8 bits long Set these bits to `1102' when transfer data is 9 bits long CKDIR STPS PRY, PRYE UiC0 CLK0, CLK1 TXEPT NCH UFORM UiC1 TE TI RE RI UCON U0IRS, U1IRS U0RRM TXD1SEL TXD1EN Select the internal clock or external clock2 Select the stop bit Select whether parity is included and whether odd or even Select the count source for the UiBRG register Transmit register empty flag Select TxDi pin output mode LSB first or MSB first can be selected when transfer data is 8 bits long. Set this bit to "0" when transfer data is 7 or 9 bits long. Set this bit to "1" to enable transmission Transmit buffer empty flag Set this bit to "1" to enable reception Reception complete flag Select the source of UART0/UART1 transmit interrupt Set to "0" Select output pin for UART1 transfer data Select TxD10 or RxD1 to be used
OER,FER,PER,SUM Error flag
Notes: 1. The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long; bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long. 2. An external clock can be selected in UART0 only.
Table 13.6 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an "H". (If the Nchannel open-drain output is selected, this pin is in a high-impedance state.) Table 13.6 I/O Pin Functions
Pin name TxD0 (P14) RxD0 (P15) CLK0 (P16) Function Serial data output Serial data input Transfer clock output Transfer clock input TxD10/RxD1 (P37) TxD11 (P00) Serial data output Serial data input Serial data output Method of selection (Cannot be used as a port when performing reception only) PD1 register PD1_5 bit=0 (Can be used as an input port when performing transmission only) U0MR register CKDIR bit=0 U0MR register CKDIR bit=1 PD1 register PD1_6 bit=0 TXD1EN=1 TXD1EN=0, PD3 register PD3_7 bit=0 Serial data output, TXD1SEL=1
Rev.0.91
2003 Sep 08
page 120 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
13.2 Clock Asynchronous Serial I/O (UART) Mode
* Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock UiC1 register "1" TE bit
"0"
Write data to UiTB register
UiC1 register "1" TI bit
"0"
Transferred from UiTB register to UARTi transmit register Start bit TxDi UiC0 register "1" TXEPT bit
"0" ST D0 D1 D2 D3 D4 D5 D6 D7
Parity Stop bit bit
P SP ST D0 D1 D2 D3 D4 D5 D6 D7
Stopped pulsing because the TE bit = "0"
P SP ST D0 D1
SiTIC register "1" IR bit
"0"
Set to "0" when interrupt request is accepted, or set by a program Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT The above timing diagram applies to the case where the register bits fj: frequency of UiBRG count source (f1SIO, f8SIO, f32SIO) are set as follows: * UiMR register PRYE bit = 1 (parity enabled) fEXT: frequency of UiBRG count source (external clock) * UiMR register STPS bit = 0 (1 stop bit) n: value set to UiBRG * UiIRS bit = 1 (an interrupt request occurs when transmit completed): i: 0, 1
* Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock UiC1 register "1" TE bit UiC1 register "1" TI bit
"0"
"0"
Write data to UiTB register
Start bit TxDi UiC0 register "1" TXEPT bit SiRIC register "1" IR bit
Transferred from UiTB register to UARTi Stop Stop transmit register bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
"0"
"0"
Set to "0" when interrupt request is accepted, or set by a program The above timing diagram applies to the case where the register bits are set as follows: * UiMR register PRYE bit = 0 (parity disabled) * UiMR register STPS bit = 1 (2 stop bits) * UiIRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty) Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj: frequency of UiBRG count source (f1SIO, f8SIO, f32SIO) fEXT: frequency of UiBRG count source (external clock) n: value set to UiBRG i: 0, 1
Figure 13.9 Transmit Operation
Rev.0.91
2003 Sep 08
page 121 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
13.2 Clock Asynchronous Serial I/O (UART) Mode
* Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG count source UiC1 register RE bit RxDi "1" "0" Start bit Sampled "L" Receive data taken in Transfer clock UiC1 register RI bit SiRIC register IR bit Reception triggered when transfer clock "1" is generated by falling edge of start bit "0" "1" "0" Set to "0" when interrupt request is accepted, or set by a program The above timing diagram applies to the case where the register bits are set as follows: * UiMR register PRYE bit = 0 (parity disabled) * UiMR register STPS bit = 0 (1 stop bit) i = 0, 1 Transferred from UARTi receive register to UiRB register
Stop bit
D0
D1
D7
(GA 13 UM60)
Figure 13.10 Receive Operation 13.2.1 TxD10/RxD1 Select Function (UART1) P37 can be used as TxD10 output pin or RxD1 input pin by selecting with the TXD1EN bit in the UCON register. P37 is used as TxD10 output pin if the TXD1EN bit is set to "1" (TxD10) and used as RxD1 input pin if set to "0" (RxD1). 13.2.2 TxD11 Select Function (UART1) P00 can be used as TxD11 output pin or a port by selecting with the TXD1SEL bit in the UCON register. P00 is used as TxD11 output pin if the TXD1SEL bit is set to "1" (TxD11) and used as an I/O port if set to "0" (P00).
Rev.0.91
2003 Sep 08
page 122 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
14. A-D Converter
14. A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. The analog inputs share the pins with P00 to P07 and P10 to P13. Therefore, when using these pins, make sure the corresponding port direction bits are set to "0" (input mode). When not using the A-D converter, set the VCUT bit to "0" (Vref unconnected), so that no current will flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip. The result of A-D conversion is stored in the AD register. Table 14.1 shows the performance of the A-D converter. Figure 14.1 shows a block diagram of the A-D converter, and Figures 14.2 and 14.3 show the A-D converter-related registers. Table 14.1 Performance of A-D converter Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage1 0V to Vref AVCC = 5V fAD, divide-by-2 of fAD, divide-by-4 of fAD Operating clock AD2 AVCC = 3V divide-by-2 of fAD, divide-by-4 of fAD Resolution 8-bit or 10-bit (selectable) Integral nonlinearity error AVcc = Vref = 5V * 8-bit resolution 2 LSB * 10-bit resolution 3 LSB AVcc = Vref = 3.3 V * 8-bit resolution 2 LSB * 10-bit resolution 5 LSB Operating modes One-shot mode and repeat mode3 Analog input pins 12 pins (AN0 to AN11) A-D conversion start condition ADST bit in ADCON0 register is set to "1" (A-D conversion starts) Conversion speed per pin * Without sample and hold function 8-bit resolution: 49 AD cycles, 10-bit resolution: 59 AD cycles * With sample and hold function 8-bit resolution: 28 AD cycles, 10-bit resolution: 33 AD cycles Notes: 1. Does not depend on use of sample and hold function. 2. The frequency of AD must be 10 MHz or less. When Vcc is less than 4.2V, AD must be fAD/2 or less by dividing fAD. Without sample and hold function, the AD frequency should be 250 kHz or more. With the sample and hold function, the AD frequency should be 1 MHz or more. 3. In repeat mode, only 8-bit mode can be used.
Rev.0.91
2003 Sep 08
page 123 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
14. A-D Converter
CKS1=1 CKS0=1
AD
CKS1=0
fAD
VCUT=0
1/2
1/2
CKS0=0
A-D conversion rate selection
AVSS VREF
VCUT=1
Resistor ladder
Successive conversion register
ADCON0
AD register Vref Decoder
Data bus
VIN
Comparator
P07/AN0 P06/AN1 P05/AN2 P04/AN3 P03/AN4 P02/AN5 P01/AN6 P00/AN7
CH2,CH1,CH0=0002 CH2,CH1,CH0=0012 CH2,CH1,CH0=0102 CH2,CH1,CH0=0112 CH2,CH1,CH0=1002 CH2,CH1,CH0=1012 CH2,CH1,CH0=1102 CH2,CH1,CH0=1112 ADGSEL0=1 ADGSEL0=0
P10/AN8 P11/AN9 P12/AN10 P13/AN11
CH2,CH1,CH0=1002 CH2,CH1,CH0=1012 CH2,CH1,CH0=1102 CH2,CH1,CH0=1112
CH0 to CH2, ADGSEL0, CKS0: Bits in ADCON0 register CKS1, VCUT: Bits in ADCON1 register
Figure 14.1 A-D Converter Block Diagram
Rev.0.91
2003 Sep 08
page 124 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
14. A-D Converter
A-D control register 01
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol ADCON0 Bit symbol
CH0
Address 00D616 Bit name
After reset 00000XXX2 Function
See Note 4. RW RW RW
Analog input pin select bit
CH1
CH2 MD A-D operation mode select bit 2 0 : One-shot mode 1 : Repeat mode
RW RW RW
ADGSEL0 (b5) ADST CKS0
A-D input group select bit 4 0: Port P0 group selected (AN 0 to AN7) 1: Port P1 group selected (AN 8 to AN11) Reserved bit A-D conversion start flag Frequency select bit 0 3 Must set to "0" 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
RW RW RW
Notes: 1. If the ADCON register is rewritten during A-D conversion, the conversion result is indeterminate. 2. When changing A-D operation mode, set analog input pin again. 3. This bit is valid when the CKS1 bit in the ADCON1 register is set to "0". 4. The analog input pin can be selected by a combination of the CH2 to CH0 bits and ADGSEL0 bit as follows: CH2 to CH0 0002 0012 0102 0112 1002 1012 1102 1112 ADGSEL0=0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 ADGSEL0=1 Avoid these settings
A-D control register 11
b7 b6 b5 b4 b3 b2 b1 b0
00
000
Symbol ADCON1 Bit symbol
(b2-b0) BITS CKS1 VCUT (b6-b7)
Address 00D716 Bit name
After reset 0016 Function
Must set to "0" 0 : 8-bit mode 1 : 10-bit mode 0 : CKS0 bit in ADCON0 register is valid 1 : fAD is selected 0 : Vref not connected 1 : Vref connected Must set to "0" RW RW RW RW RW
Reserved bit 8/10-bit mode select bit2 Frequency select bit 1 3 Vref connect bit 4 Reserved bit
RW Notes: 1. If the ADCON1 register is rewritten during A-D conversion, the conversion result is indeterminate. 2. In repeat mode, the BITS bit must be set to "0" (8-bit mode). 3. The AD frequency must be 10 MHz or less. 4. If the VCUT bit is reset from "0" (Vref unconnected) to "1" (Vref connected), wait for 1 s or more before starting A-D conversion.
Figure 14.2 ADCON0 Register and ADCON1 Register
Rev.0.91 2003 Sep 08 page 125 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
14. A-D Converter
A-D control register 21
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
00D416
After reset
0016
000
Bit symbol
SMP
Bit name
A-D conversion method select bit Reserved bit
Function
0 : Without sample and hold 1 : With sample and hold Must set to "0"
RW RW RW
(b3-b1) (b7-b4)
Nothing is assigned. When write, write "0". When read, its content is "0".
Notes: 1. If the ADCON2 register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D register
(b15) b7 (b8) b0 b7
Symbol
AD
Address 00C116-00C016
b0
After reset Indeterminate
Function
When BITS bit in ADCON1 register is set to "1" (10-bit mode) Eight low-order bits of A-D conversion result Two high-order bits of A-D conversion result When BITS bit in ADCON1 register is set to "0" (8-bit mode) A-D conversion result When read, its content is indeterminate.
RW
RO RO
Nothing is assigned. When write, set to "0". When read, its content is "0".
Figure 14.3 ADCON2 Register and AD Register
Rev.0.91
2003 Sep 08
page 126 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
14. One-shot mode
14.1 One-shot Mode In one-shot mode, the input voltage on one selected pin is A-D converted once. Table 14.2 lists the specifications of one-shot mode. Figure 14.4 shows the ADCON0 and ADCON1 registers in oneshot mode. Table 14.2 One-shot Mode Specifications Specification Input voltage on one pin selected by CH2 to CH0 and ADGSEL0 bit is A-D converted once. Start condition Set ADST bit to "1" Stop condition * Completion of A-D conversion (ADST bit is set to "0") * Set ADST bit to "0" Interrupt request generation timing End of A-D conversion Input pin One of AN0 to AN11, as selected Reading of result of A-D converter Read A-D register Function Item
Rev.0.91
2003 Sep 08
page 127 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
14. One-shot mode
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol ADCON0 Bit symbol
CH0
Address 00D616 Bit name
After reset 00000XXX2 Function
RW RW RW
Analog input pin select bit2 See Note 4
CH1
CH2 MD ADGSEL0 A-D operation mode select bit2 0 : One-shot mode
RW RW RW
A-D input group select bit4 0: Port P0 group selected (AN0 to AN7) 1: Port P1 group selected (AN8 to AN11) Reserved bit A-D conversion start flag Frequency select bit 03 Must set to "0" 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
(b5) ADST CKS0
RW RW RW
Notes: 1. If the ADCON0 register is rewritten during A-D conversion, the conversion result is indeterminate. 2. When changing A-D operation mode, set analog input pin again. 3. This bit is valid when the CKS1 bit in the ADCON1 register is set to "0". 4. The analog input pin can be selected by a combination of the CH2 to CH0 bits and ADGSEL0 bit as follows: CH2 to CH0 0002 0012 0102 0112 1002 1012 1102 1112 ADGSEL0=0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 ADGSEL0=1 Avoid these settings
A-D control register 11
b7 b6 b5 b4 b3 b2 b1 b0
001
000
Symbol ADCON1 Bit symbol
(b2-b0) BITS CKS1 VCUT (b6-b7)
Address 00D716 Bit name
After reset 0016 Function
Must set to "0" 0 : 8-bit mode 1 : 10-bit mode RW RW RW RW RW
Reserved bit 8/10-bit mode select bit
Frequency select bit 12 0 : CKS0 bit in ADCON0 register is valid 1 : fAD is selected Vref connect bit3 Reserved bit 1 : Vref connected Must set to "0"
RW Notes: 1. If the ADCON1 register is rewritten during A-D conversion, the conversion result is indeterminate. 2. The AD frequency must be 10 MHz or less. 3. If the VCUT bit is reset from "0" (Vref unconnected) to "1" (Vref connected), wait for 1 s or more before starting A-D conversion.
Figure 14.4 ADCON0 Register and ADCON1 Registers in One-shot Mode
Rev.0.91 2003 Sep 08 page 128 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
14. Repeat mode
14.2 Repeat Mode In repeat mode, the input on one selected pin is A-D converted repeatedly. Table 14.3 lists the specifications of repeat mode. Figure 14.5 shows the ADCON0 and ADCON1 registers in repeat mode. Table 14.3 Repeat Mode Specifications Item Specification Function Input voltage on one pin selected by CH2 to CH0 and ADGSEL0 bits is A-D converted repeatedly Start condition Set ADST bit to "1" Stop condition Set ADST bit to "0" Interrupt request generation timing None generated Input pin One of AN0 to AN11, as selected Reading of result of A-D converter Read AD register
Rev.0.91
2003 Sep 08
page 129 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
14. Repeat mode
A-D control register 01
b7 b6 b5 b4 b3 b2 b1 b0
0
1
Symbol ADCON0 Bit symbol
CH0
Address 00D616 Bit name
After reset 00000XXX2 Function
RW RW RW
Analog input pin select bit2 See Note 4
CH1
CH2 MD A-D operation mode select bit 2 1 : Repeat mode
RW RW
ADGSEL0 (b5) ADST CKS0
A-D input group select bit4 0: Port P0 group selected (AN0 to AN7) 1: Port P1 group selected (AN8 to AN11) Reserved bit A-D conversion start flag Frequency select bit 03 Must set to "0" 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
RW RW RW RW
Notes: 1. If the ADCON0 register is rewritten during A-D conversion, the conversion result is indeterminate. 2. When changing A-D operation mode, set analog input pin again. 3. This bit is valid when the CKS1 bit in the ADCON1 register is set to "0". 4. The analog input pin can be selected by a combination of the CH2 to CH0 bits and ADGSEL0 bit as follows: CH2 to CH0 0002 0012 0102 0112 1002 1012 1102 1112 ADGSEL0=0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 ADGSEL0=1 Avoid these settings
A-D control register 11
b7 b6 b5 b4 b3 b2 b1 b0
001
0000
Symbol ADCON1 Bit symbol
(b2-b0) BITS CKS1 VCUT
Address 00D716 Bit name
After reset 0016 Function
Must set to "0" 0 : 8-bit mode RW RW RW RW RW
Reserved bit 8/10-bit mode select bit2
Frequency select bit 13 0 : CKS0 bit in ADCON0 register is valid 1 : fAD is selected Vref connect bit4 1 : Vref connected
Must set to "0" Reserved bit RW (b6-b7) Notes: 1. If the ADCON1 register is rewritten during A-D conversion, the conversion result is indeterminate. 2. In repeat mode, the BITS bit must be set to "0" (8-bit mode). 3. The fAD frequency must be 10 MHz or less. 4. If the VCUT bit is reset from "0" (Vref unconnected) to "1" (Vref connected), wait for 1 s or more before starting A-D conversion.
Figure 14.5 ADCON0 Register and ADCON1 Register in Repeat Mode
Rev.0.91 2003 Sep 08 page 130 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
14. Sample and Hold mode
14.3 Sample and Hold If the SMP bit in the ADCON2 register is set to "1" (with sample-and-hold), the conversion speed per pin is increased to 28 OAD cycles for 8-bit resolution or 33 OAD cycles for 10-bit resolution. Sampleand-hold is effective in all operation modes. Select whether or not to use the sample-and-hold function before starting A-D conversion.
Rev.0.91
2003 Sep 08
page 131 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
15. Programmable I/O Ports
15. Programmable I/O Ports
15. 1 Description
The programmable input/output ports (hereafter referred to as "I/O ports") consist of 22 lines P0, P1, P30 to P33, P37, and P45. Each port can be set for input or output every line by using a direction register, and can also be chosen to be or not be pulled high every 4 lines. The port P1 allows the drive capacity of its Nchannel output transistor to be set as necessary. The port P1 can be used as LED drive port if the drive capacity is set to "HIGH". P46 and P47 can be used as an input only port if the main clock oscillation circuit is not used. Figures 15.1 to 15.5 show the I/O ports. Figure 15.6 shows the I/O pins. Each pin functions as an I/O port or a peripheral function input/output. For details on how to set peripheral functions, refer to each functional description in this manual. If any pin is used as a peripheral function input, set the direction bit for that pin to "0" (input mode). Any pin used as an output pin for peripheral functions is directed for output no matter how the corresponding direction bit is set. 15.1.1 Port Pi Direction Register (PDi Register, i = 0, 1, 3, 4) Figure 15.6 shows the PDi register. This register selects whether the I/O port is to be used for input or output. The bits in this register correspond one for one to each port. 15.1.2 Port Pi Register (Pi Register, i = 0 to 4) Figure 15.7 shows the Pi register. Data input/output to and from external devices are accomplished by reading and writing to the Pi register. The Pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. For ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register, and data can be written to the port latch by writing to the Pi register. For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and data can be written to the port latch by writing to the Pi register. The data written to the port latch is output from the pin. The bits in the Pi register correspond one for one to each port. 15.1.3 Pull-up Control Register 0, Pull-up Control Register 1 (PUR0 and PUR1 Registers) Figure 15.8 shows the PUR0 and PUR1 registers. The PUR0 and PUR1 register bits can be used to select whether or not to pull the corresponding port high in 4 bit units. The port chosen to be pulled high has a pull-up resistor connected to it when the direction bit is set for input mode. 15.1.4 Port P1 Drive Capacity Control Register (DRR Register) Figure 15.8 shows the DRR register. The DRR register is used to control the drive capacity of the port P1 N-channel output transistor. The bits in this register correspond one for one to each port.
Rev.0.91
2003 Sep 08
page 132 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
15. Programmable I/O Ports
P00
Pull-up selection
Direction regiister "1" Output
Data bus
Port latch
Analog input
P01 to P07
Pull-up selection Direction register
Data bus
Port latch
Analog input
P10 to P12
Pull-up selection Direction register "1" Output
Data bus
Port latch
Select drive capacity Input to respective peripheral functions Analog Input
Figure 15.1 Programmable I/O Ports (1)
Rev.0.91 2003 Sep 08 page 133 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
15. Programmable I/O Ports
P13
Pull-up selection Direction register
Data bus
Port latch
Select drive capacity Input to respective peripheral functions Analog input
P14
Pull-up selection Direction register "1" Output
Data bus
Port latch
Select drive capacity
P15
Pull-up selection Direction register
Data bus
Port latch
Select drive capacity Input to respective peripheral functions
Figure 15.2 Programmable I/O Ports (2)
Rev.0.91
2003 Sep 08
page 134 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
15. Programmable I/O Ports
P16,P17
Pull-up selection Direction register "1" Output
Data bus
Port latch
Select drive capactiy Input to respective peripheral functions
P30, P31
Puu-up selection Direction register "1" Output
Data bus
Port latch
P32
Direction register
Pull-up selection
"1" Output Data bus Port latch
Input to respective peripheral functions
Figure 15.3 Programmable I/O Ports (3)
Rev.0.91 2003 Sep 08 page 135 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
15. Programmable I/O Ports
P33
Pull-up selection Direction register
Data bus
Port latch
Input to respective peripheral functions
Digital Filter
P37
Pull-up selection Direction register "1" Output
Data bus
Port latch
Input to respective peripheral functions
P45
Pull-up selection Direction register
Data bus
Port latch
Input to respective peripheral functions
Digital Filter
Figure 15.4 Programmable I/O Ports (4)
Rev.0.91 2003 Sep 08 page 136 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
15. Programmable I/O Ports
P46/XIN Data bus
Clocked inverter1
(Note 2) P47/XOUT Data bus
Notes: 1. When CM05=1, CM10=1, or CM13=0, the clocked inverter is cutoff. 2. When CM10 or CM13=0, the feedback resistor is unconnected.
Figure 15.5 Programmable I/O Port (4)
MODE MODE signal input (Note 1)
CNVSS CNVSS signal input (Note 1)
RESET RESET signal input (Note 1) Notes: 1. symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc.
Figure 15.6 I/O Pins
Rev.0.91 2003 Sep 08 page 137 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
15. Programmable I/O Ports
Port Pi direction register (i=0, 1, 3, 4)1, 2, 3
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PD0 PD1 PD3 PD4 Bit symbol
PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7
Address 00E216 00E316 00E716 00EA16 Bit name
Port Pi0 direction bit Port Pi1 direction bit Port Pi2 direction bit Port Pi3 direction bit Port Pi4 direction bit Port Pi5 direction bit Port Pi6 direction bit Port Pi7 direction bit
After reset 0016 0016 0016 0016 Function RW RW RW RW RW RW RW RW RW
0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port)
Notes: 1. The PD0 register must be written to by the next instruction after setting the PRC2 bit in the PRCR register to "1" (write enabled). 2. Nothing is assigned to the PD3_4 to PD3_6 bits in the PD3 register. When writing to the PD3_4 to PD3_6 bits, write "0" (input mode). When read, its content is "0". 3. Nothing is assigned to the PD4_0 to PD4_4, PD4_6 and PD4_7 bits in the PD4 register. When writing to the PD4_0 to PD4_4, PD4_6 and PD4_7 bits, write "0" (input mode). When read, its content is "0".
Figure 15.7 PD0 Register, PD1 Register, PD3 Register, and PD4 Register
Port Pi register (i=0, 1, 3, 4)1, 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P0 P1 P3 P4 Bit symbol
Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7
Address 00E016 00E116 00E516 00E816 Bit name
Port Pi0 bit Port Pi1 bit Port Pi2 bit Port Pi3 bit Port Pi4 bit Port Pi5 bit Port Pi6 bit Port Pi7 bit
After reset Indeterminate Indeterminate Indeterminate Indeterminate Function
The pin level on any I/O port which is set for input mode can be read by reading the corresponding bit in this register. The pin level on any I/O port which is set for output mode can be controlled by writing to the corresponding bit in this register 0 : "L" level 1 : "H" level (i = 0, 1, 3, 4)
RW RW RW RW RW RW RW RW RW
Notes: 1. Nothing is assigned to the P3_4 to P3_6 bits in the P3 register. When writing to the P3_4 to P3_6 bits, write "0" ("L" level). When read, its content is "0". 2. Nothing is assigned to the P4_0 to P4_4 bits in the P4 register. When writing to the P4_0 to P4_4 bits, write "0" ("L" level). When read, its content is "0".
Figure 15.8 P0 Register to P4 Register
Rev.0.91
2003 Sep 08
page 138 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
15. Programmable I/O Ports
Pull-up control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR0 Bit symbol
PU00 PU01 PU02 PU03 (b5-b4) PU06 PU07
Address 00FC16 Bit name
P00 to P03 pull-up1 P04 to P07 pull-up1 P10 to P13 pull-up1 P14 to P17 pull-up1
After reset 00XX00002 Function
0 : Not pulled high 1 : Pulled high1
RW RW RW RW RW
Nothing is assigned. When write, set to "0". When read, its content is indeterminate. P30 to P33 pull-up1 P37 pull-up1 0 : Not pulled high 1 : Pulled high1
RW RW
Notes: 1. The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high.
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR1 Bit symbol
(b0) PU11
Address 00FD16 Bit name
After reset XXXXXX0X2 Function RW
Nothing is assigned. When write, set to "0". When read, its content is indeterminate. P45 pull-up1 0 : Not pulled high 1 : Pulled high1
RW
(b7-b2)
Nothing is assigned. When write, set to "0". When read, its content is indeterminate.
Notes: 1. The P45 pin for which the PU11 bit is "1" (pulled high) and the PD4_5 bit is "0" (input mode) is pulled high.
Port P1 drive capacity control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DRR Bit symbol
DRR0 DRR1 DRR2 DRR3 DRR4 DRR5 DRR6 DRR7
Address 00FE16 Bit name
P10 drive capacity P11 drive capacity P12 drive capacity P13 drive capacity P14 drive capacity P15 drive capacity P16 drive capacity P17 drive capacity
After reset 0016 RW Set P1 N-channel output transistor RW drive capacity RW 0 : LOW RW
1 : HIGH
Function
RW RW RW RW RW
Figure 15.9 PUR0 Register, PUR1 Register, and DRR Register
Rev.0.91
2003 Sep 08
page 139 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
15. Programmable I/O Ports
15.2 Unassigned Pin Handling
Table 15.1 lists the handling of unassigned pins. Table 15.1 Unassigned Pin Handling
Pin name Ports P0, P1, P30 to P33, P45 Ports P46, P47 AVCC, VREF AVSS RESET3 Connection After setting for input mode, connect every pin to VSS via a resistor(pull-down); or after setting for output mode, leave these pins open1, 2. Connect to VCC via resistor (pull-up)2 Connect to VCC Connect to VSS Connect to VCC (pull-up)2
Notes: 1. When these ports are set for output mode and left open, they remain input mode until they are set for output mode by a program. The voltage level of these pins may be unstable and the power supply voltage may increase for the time the ports remain input mode. The content of the direction registers may change due to noise or runaway caused by noise. In order to enhance program reliability, set the direction registers periodically by a program. 2. Connect these unassigned pins to the microcomputer using the shortest wire length (within 2 cm) possible. 3. When power-on reset is used.
Rev.0.91
2003 Sep 08
page 140 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
16. Electrical Characteristics
16. Electrical Characteristics
Table 16.1 Absolute Maximum Ratings
Symbol
VCC AVCC VI VO Pd Topr Tstg Supply voltage Analog supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature Topr=25 C
Parameter
Condition
VCC=AVCC VCC=AVCC
Rated value
-0.3 to 6.5 -0.3 to 6.5 -0.3 to VCC+0.3 -0.3 to VCC+0.3 300 -20 to 85 / -40 to 85 (D version) -65 to 150
Unit
V V V V mW C C
Table 16.2 Recommended Operating Conditions
Symbol
VCC AVcc Vss AVss VIH VIL I OH (sum) I OH (peak) I OH (avg) I OL (sum) I OL (peak)
Parameter
Supply voltage Analog supply voltage Supply voltage Analog supply voltage "H" input voltage "L" input voltage Sum of all pins' IOH "H" peak all output currents (peak) "H" peak output current "H" average output current Sum of all pins' IOL "L" peak all output currents (peak) "L" peak output Except P10 to P17 current P10 to P17 "L" average output current Except P10 to P17 P10 to P17
Conditions
Min.
2.7 (NOTE3, 4)
Standard Typ.
5.0 VCC 0 0
Max.
5.5
Unit
V V V V
0.8VCC 0
VCC 0.2VCC -60.0 -10.0 -5.0 60 10
V V mA mA mA mA mA mA mA mA mA mA MHz MHz
Drive ability HIGH Drive ability LOW
30 10 5 15 5 20 10
I OL (avg)
f (XIN)
Drive ability HIGH Drive ability LOW Main clock input oscillation frequency 3.0V Vcc 5.5V 2.7V Vcc < 3.0V
0 0
Note 1: Referenced to VCC = AVCC = 2.7 to 5.5V at Topr = -20 to 85 C / -40 to 85 C unless otherwise specified. 2: The mean output current is the mean value within 100ms. 3: When using 10 bit resolution mode of A-D converter, set AVcc 4.2V. 4: When using sample & hold function of A-D converter, set AVcc 4.2V.
Rev.0.91
2003 Sep 08
page 141 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
16. Electrical Characteristics
Table 16.3 A-D Conversion Characteristics
Symbol
- - Resolution
Parameter Absolute accuracy
Measuring condition
Vref =VCC
Standard Unit Min. Typ. Max.
10 3 2 5 2 10 3.3 2.8 TBD 2.0 0 0.25 1.0 VCC Vref 10 10 40 Bit LSB LSB LSB LSB k s s s V V MHz MHz
10 bit mode 8 bit mode 10 bit mode 8 bit mode
f(XIN)=oAD=10 MHz, Vref=Vcc=5.0V f(XIN)=oAD=10 MHz, Vref=Vcc=5.0V f(XIN)=oAD=10 MHz, Vref=Vcc=3.3V f(XIN)=oAD=10 MHz, Vref=Vcc=3.3V
RLADDER tCONV tSAMP VREF VIA -
Ladder resistance Conversion time Sampling time Reference voltage Analog input voltage
VREF=VCC
10 bit mode 8 bit mode
f(XIN)=oAD=10 MHz, Vref=Vcc=5.0V f(XIN)=oAD=10 MHz, Vref=Vcc=5.0V
A-D operation Without sample & hold clock frequency2 With sample & hold
Note 1: Referenced to VCC=AVCC=2.7 to 5.5V at Topr = -20 to 85 C / -40 to 85 C unless otherwise specified. 2: When fAD is 10 MHz more, divide the fAD and make A-D operation clock frequency (OAD) lower than 10 MHz. 3: When the Vcc is less than 4.2V, divide the fAD and make A-D operation clock frequency (OAD) lower than fAD/2.
Table 16.4 Flash Memory Version Electrical Characteristics
Symbol
- - - - -
Parameter
Byte program time Block erase time Program, Erase Voltage Read Voltage Program, Erase Temperature
Measuring condition
Min.
Standard Typ.
75 400
Max
TBD TBD 5.5 5.5 60
Unit
s ms V V C
2.7 2.7 0
Note 1: Referenced to VCC1=AVcc=2.7 to 5.5V at Topr = 0 to 60 C unless otherwise specified.
Table 16.5 Voltage Detection Circuit Electrical Characteristics
Symbol
Vdet4 Voltage detection level Voltage detection interrupt request generating time2 Voltage detection circuit self consumption current td(E-A) Waiting time till voltage detection circuit operation starts3 VC27="1"
Parameter
Measuring condition
Min.
3.3
Standard Typ.
3.8 40 TBD
Max.
4.3
Unit
V V V
20
V
Note 1: The measureing condition is Vcc=AVcc=5.0 V and Topr=25 C. 2: This shows the time till the voltage detection interrupt request is generated since the voltage passes Vdet. 3: This shows the required time till the voltage detection circuit operates when setting to "1" again.
Rev.0.91
2003 Sep 08
page 142 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
16. Electrical Characteristics
Table 16.6 Power-on Reset Circuit Electrical Characteristics
Symbol Parameter
Power-on reset start time2 Power-on reset cancel operation start voltage Hardware reset 2 cancel operation start voltage Supply start up condition when using power-on reset circuit Intergradation time to 0V<2.7V Vcc<0.5V
Measuring condition
Min.
TBD 3.3 3.3
Standard Typ.
3.8 3.8
Max.
4.3 4.3 TBD
Unit
ms V V ms
Note 1: The measuring condition is Vcc=AVcc=5.0 V and Topr=25 C. 2: Keep Vcc<0.5V for over regulated time to execute the reset operation.
Table 16.7 High-speed Ring Oscillator Circuit Electrical Characteristics
Symbol Parameter
Settable high-speed ring oscillator minimum period High-speed ring oscillator adjusted unit
Measuring condition
Set "0016" in the HR1 register Differences when setting "0116" and "0016" in the HR register
Min.
Standard Typ.
TBD 1
Max.
Unit
ns ns
Note 1: The measuring condition is Vcc=AVcc=5.0 V and Topr=25 C.
Table 16.8 Power Circuit Timing Characteristics
Symbol
td(P-R) td(R-S)
Parameter
Time for internal power supply stabilization during powering-on2 STOP release time3
Measuring condition
Min.
Standard Typ.
Max.
2 150
Unit
ms s
Note 1: The measuring condition is Vcc=AVcc=2.7 to 5.0 V and Topr=25 C. 2: This shows the wait time untill the internal power supply generating circuit is stabilized during power-on. 3: This shows the time till BCLK starts from the interrupt acknowledgement to cancel stop mode.
Rev.0.91
2003 Sep 08
page 143 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
16. Electrical Characteristics
Table 16.9 Electrical Characteristics (1)
Symbol
"H" output voltage VOH XOUT "L" output voltage VOL P10 to P17 Except XOUT P10 to P17
[Vcc=5V]
Measuring condition
IOH=-5mA IOH=-200A Drive ability HIGH Drive ability LOW IOH= 5 mA IOH= 200 A Drive ability HIGH Drive ability LOW Drive ability HIGH Drive ability LOW IOH= 10 mA IOH= 5 mA IOH= 1 mA IOH=500A 0.2 IOH=-1 mA IOH=-500A
Parameter
Except XOUT
Min.
VCC-2.0 VCC-0.3 VCC-2.0 VCC-2.0
Standard Typ. Max.
VCC VCC VCC VCC 2.0 0.45 2.0 2.0 2.0 2.0 1.0
Unit
V V V V V V V V V V V
XOUT VT+-VTHysteresis INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, CNTRo, CNTR1, TCIN, RxD0, RxD1 RESET IIH IIL RPULLUP RfXIN fRING VRAM "H" input current "L" input current Pull-up resistance Feedback resistance
Low ring oscillator frequency
0.2 VI=5V VI=0V VI=0V 30 40 At stop mode 2.0 50 1.0 125
2.2 5.0
V A A k M kHz V
-5.0
167 250
XIN
RAM retention voltage
Note 1 : Referenced to VCC=AVCC=4.2 to 5.5V at Topr = -20 to 85 C / -40 to 85 C, f(BCLK)=20MHz unless otherwise specified.
Rev.0.91
2003 Sep 08
page 144 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
16. Electrical Characteristics
Table 16.10 Electrical Characteristics (2)
Symbol Parameter
[Vcc=5V]
Measuring condition
High-speed mode
XIN=20 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=100 kHz No division XIN=5 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=100 kHz No division XIN=20 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=100 kHz Division by 8 XIN=5 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=100 kHz Division by 8 Main clock off High-speed ring oscillator on=8 MHz Low-speed ring oscillator on=100 kHz No division Main clock off High-speed ring oscillator on=8 MHz Low-speed ring oscillator on=100 kHz Division by 8 Main clock off High-speed ring oscillator off Low-speed ring oscillator on=100 kHz Division by 8 Main clock off High-speed ring oscillator off Low-speed ring oscillator on=100 kHz At wait mode2 Peripheral clock operation Main clock off High-speed ring oscillator off Low-speed ring oscillator on=100 kHz At wait mode2 Peripheral clock off Main clock off High-speed ring oscillator off Low-speed ring oscillator off CM10="1" Peripheral clock off
Min.
Standard Typ.
9.0
Max.
TBD
Unit
mA
3.5
mA
Medium-speed mode
TBD
mA
TBD
mA
ICC
Power supply current (VCC1=4.2 to 5.5V) In single-chip mode, the output pins are open and other pins are VSS
High-speed ring oscillator mode
TBD
TBD
mA
TBD
mA
Low-speed ring oscillator mode Wait mode
0.8
mA
43
A
Wait mode
33
A
Stop mode
1.0
TBD
A
Note 1: The power supply current measuring is executed using the measuring program on frash memory. 2: Timer Y is operated with timer mode.
Rev.0.91
2003 Sep 08
page 145 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
16. Electrical Characteristics
Table 16.11 Electrical Characteristics (3)
Symbol
"H" output voltage VOH "L" output voltage VOL
[Vcc=3V]
Measuring condition
IOH=-1mA Drive ability HIGH Drive ability LOW IOH= 1 mA Drive ability HIGH Drive ability LOW Drive ability HIGH Drive ability LOW IOH= 2 mA IOH= 1 mA IOH= 0.1 mA IOH=50 A 0.2 IOH=-0.1 mA IOH=-50 A
Parameter
Except XOUT XOUT P10 to P17 Except XOUT P10 to P17 XOUT
Min.
VCC-0.5 VCC-0.5 VCC-0.5
Standard Typ. Max.
VCC VCC VCC 0.5 0.5 0.5 0.5 0.5 0.8
Unit
V V V V V V V V V
VT+-VT-
Hysteresis
INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, CNTRo, CNTR1, TCIN, RxD0, RxD1 RESET VI=3V VI=0V VI=0V XIN
0.2
IIH IIL RPULLUP RfXIN fRING-S VRAM
"H" input current "L" input current Pull-up resistance Feedback resistance
Low-speed ring oscillator frequency
1.8 4.0
V A A k M kHz V
-4.0
66 40 160 3.0 125 250 500
RAM retention voltage
At stop mode
2.0
Note 1 : Referenced to VCC=AVCC=2.7 to 3.3V at Topr = -20 to 85 C / -40 to 85 C, f(BCLK)=5MHz unless otherwise specified.
Rev.0.91
2003 Sep 08
page 146 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
16. Electrical Characteristics
Table 16.12 Electrical Characteristics (4)
Symbol Parameter
[Vcc=3V]
Measuring condition
High-speed mode
XIN=20 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=100 kHz No division XIN=5 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=100 kHz No division XIN=20 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=100 kHz Division by 8 XIN=5 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=100 kHz Division by 8 Main clock off High-speed ring oscillator on=8 MHz Low-speed ring oscillator on=100 kHz No division Main clock off High-speed ring oscillator on=8 MHz Low-speed ring oscillator on=100 kHz Division by 8 Main clock off High-speed ring oscillator off Low-speed ring oscillator on=100 kHz Division by 8 Main clock off High-speed ring oscillator off Low-speed ring oscillator on=100 kHz At wait mode2 Peripheral clock operation Main clock off High-speed ring oscillator off Low-speed ring oscillator on=100 kHz At wait mode2 Peripheral clock off Main clock off High-speed ring oscillator off Low-speed ring oscillator off CM10="1" Peripheral clock off
Min.
Standard Typ.
8.0
Max.
TBD
Unit
mA
3.0
mA
Medium-speed mode
TBD
mA
TBD
mA
ICC
Power supply current (VCC1=2.7 to 3.3V) In single-chip mode, the output pins are open and other pins are VSS
High-speed ring oscillator mode
TBD
TBD
mA
TBD
mA
Low-speed ring oscillator mode Wait mode
0.8
mA
TBD
A
Wait mode
TBD
A
Stop mode
1.0
TBD
A
Note 1: The power supply current measuring is executed using the measuring program on frash memory. 2: Timer Y is operated with timer mode.
Rev.0.91
2003 Sep 08
page 147 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17. Flash Memory Version
17. Flash Memory Version
17.1 Overview
The flash memory version has two modes--CPU rewrite and standard serial input/output--in which its flash memory can be operated on. Table 17.1 outlines the performance of flash memory version (see "Table 1.1 Performance" for the items not listed on Table 17.1).
Table 17.1 Flash Memory Version Performance
Item Flash memory operating mode Erase block Method for program Method for erasure Program, erase control method Protect method Number of commands Number of program and erasure Data Retention ROM code protection Specification 2 modes (CPU rewrite and standard serial I/O) See "Figure 17.1. Flash Memory Block Diagram" In units of byte Block erase Program and erase controlled by software command Blocks 0 and 1 protected by block 0, 1 program enable bit 5 commands 100 times 10 years Standard serial I/O mode is supported.
Table 17.2 Flash Memory Rewrite Modes Flash memory CPU rewrite mode rewrite mode Function User ROM area is rewritten by executing software commands from the CPU. EW0 mode: Can be rewritten in any area other than the flash memory EW1 mode: Can be rewritten in the flash memory Areas which User ROM area can be rewritten Operation Single chip mode mode ROM None programmer Standard serial I/O mode User ROM area is rewritten by using a dedicated serial programmer. Standard serial I/O mode 1: Clock sync serial I/O Standard serial I/O mode 2: UART User ROM area Boot mode Serial programmer
Rev.0.91
2003 Sep 08
page 148 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17. Memory Map
17.2 Memory Map
The ROM in the flash memory version is separated between a user ROM area and a boot ROM area (reserved area). Figure 17.1 shows the block diagram of flash memory. The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite and standard serial input/output modes. Block 1 and Block 0 are enabled for rewrite in CPU rewrite mode by setting the FMR02 bit in the FMR0 register to "1" (rewrite enabled). The rewrite program for standard serial I/O mode is stored in the boot ROM area before shipment.
0C00016 Block 1: 8 Kbytes1
0DFFF16 0E00016 Block 0: 8 Kbytes1 0E00016 8 Kbytes
0FFFF16 User ROM area
0FFFF16 Boot ROM area (reserved area)
Notes: 1. Block 1 and Block 0 are enabled for rewrite in CPU rewrite mode by setting the FMR02 bit in the FMR0 register to "1" (rewrite enabled).
Figure 17.1 Flash Memory Block Diagram
Rev.0.91
2003 Sep 08
page 149 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.3 Functions To Prevent Flash Memory from Rewriting
17.3 Functions To Prevent Flash Memory from Rewriting
To prevent the flash memory from being read or rewritten easily, standard serial input/output mode has an ID code check function. 17.3.1 ID Code Check Function Use this function in standard serial input/output mode. Unless the flash memory is blank, the ID codes sent from the programmer and the ID codes written in the flash memory are compared to see if they match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 00FFDF16, 00FFE316, 00FFEB16, 00FFEF16, 00FFF316, 00FFF716, and 00FFFB16. Prepare a program in which the ID codes are preset at these addresses and write it in the flash memory.
Address 00FFDF16 to 00FFDC16 ID1 00FFE316 to 00FFE016 00FFE716 to 00FFE416 00FFEB16 to 00FFE816 00FFEF16 to 00FFEC16 00FFF316 to 00FFF016 00FFF716 to 00FFF416 00FFFB16 to 00FFF816 00FFFF16 to 00FFFC16 ID3 ID4 ID5 ID6 ID7
(Note 1)
Undefined instruction vector
ID2
Overflow vector BRK instruction vector Address match vector Single step vector
Watchdog timer/Oscillation stop detection/Voltage detection vector
(Reserved) (Reserved) Reset vector
Notes: 1. When write to address 00FFFF16, write "FF16".
Figure 17.2 Address for ID Code Stored
4 bytes
Rev.0.91
2003 Sep 08
page 150 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.4 CPU Rewrite Mode
17.4 CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted onboard without having to use a ROM programmer, etc. Make sure the Program and the Block Erase commands are executed only on each block in the user ROM area. For interrupts requested during an erase operation in CPU rewrite mode, the R8C/11 flash module offers an "erase-suspend" feature which allow the erase operation to be suspended, and access made available to the flash. During CPU rewrite mode, the user ROM area be operated on in either Erase Write 0 (EW0) mode or Erase Write 1 (EW1) mode. Table 17.3 lists the differences between Erase Write 0 (EW0) and Erase Write 1 (EW1) modes. Table 17.3 EW0 Mode and EW1 Mode Item EW0 mode Operation mode Single chip mode Areas in which a User ROM area rewrite control program can be located Areas in which a Must be transferred to any area other rewrite control than the flash memory (e.g., RAM) program can be executed before being executed Areas which can be User ROM area rewritten
EW1 mode Single chip mode User ROM area
Can be executed directly in the user ROM area User ROM area However, this does not include the block in which a rewrite control program exists1 * Program, Block Erase command Cannot be executed on any block in which a rewrite control program exists * Read Status Register command Cannot be executed Read Array mode Hold state (I/O ports retain the state in which they were before the command was executed) Read the FMR0 register FMR00, FMR06, and FMR07 bits in a program
Software command limitations
None
Modes after Program or Erase CPU status during Auto Write and Auto Erase Flash memory status detection
Read Status Register mode Operating
Conditions for transferring to erase-suspend Notes: 1. Block 1 and Block 0 are enabled for rewrite by setting the FMR02 bit in the FMR0 register to "1" (rewrite enabled).
* Read the FMR0 register FMR00, FMR06, and FMR07 bits in a program * Execute the Read Status Register command to read the status register SR7, SR5, and SR4. Set the FMR40 and FMR41 bits in When an interrupt which is set for the FMR4 register to "1" by program. enabled occurs while the FMR40 bit in the FMR4 register is set to "1".
Rev.0.91
2003 Sep 08
page 151 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.4 CPU Rewrite Mode
17.4.1 EW0 Mode The microcomputer is placed in CPU rewrite mode by setting the FMR01 bit in the FMR0 register to "1" (CPU rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register's FMR11 bit = 0, EW0 mode is selected. Use software commands to control program and erase operations. Read the FMR0 register or status register to check the status of program or erase operation at completion. When moving to an erase-suspend, set the FMR40 bit to "1" (erase-suspend enabled ) and the FMR41 bit to "1" (suspend requested). Wait for td(SR-ES) and make sure that the FMR46 bit is set to "1" (auto-erase inactive) before accessing the user ROM space. The erase operation resumes by setting the FMR41 bit to "0" (erase restart). 17.4.2 EW1 Mode EW1 mode is selected by setting FMR11 bit to "1" (EW1 mode) after setting the FMR01 bit to "1" (CPU rewrite mode enabled). Read the FMR0 register to check the status of program or erase operation at completion. Avoid executing software commands of Read Status register in EW1 mode. To enable the erase-suspend function, the Block Erase command should be executed after setting the FMR40 bit to "1" (erase-suspend enabled). An interrupt to request an erase-suspend must be in enabled state. Once being placed in an erase-suspend upon td(SR-ES) from the interrupt request,the interrupt request is generated. When an interrupt request is generated, FMR41 bit is automatically set to "1" (suspend requested) and the auto-erase operation is halted. If the auto-erase operation is not completed (FMR00 bit is "0") when the interrupt routine is ended, the Block Erase command should be executed again by setting the FMR41 bit to "0" (erase restart).
Rev.0.91
2003 Sep 08
page 152 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.4 CPU Rewrite Mode
Figure 17.3 shows the FMR0 and FMR1 registers. Figure 17.4 shows the FMR4 register. * FMR00 Bit This bit indicates the operating status of the flash memory. The bit is "0" during programming, erasing, or erase-suspend mode; otherwise, the bit is "1". * FMR01 Bit The microcomputer is made ready to accept commands by setting the FMR01 bit to "1" (CPU rewrite mode). * FMR02 Bit The Block1 and Block0 do not accept the Program and Block Erase commands if the FMR02 bit is set to "0" (rewrite disabled). * FMSTP Bit This bit is provided for initializing the flash memory control circuits, as well as for reducing the amount of current consumed in the flash memory. The flash memory is disabled against access by setting the FMSTP bit to "1". Therefore, the FMSTP bit must be written to by a program in other than the flash memory. In the following cases, set the FMSTP bit to "1": * When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit not reset to "1" (ready)) * When entering ring oscillator mode (main clock stop) Figure 17.6 shows a flow chart to be followed before and after entering ring oscillator mode (main clock stop). Note that when going to stop or wait mode while the CPU rewrite mode is disabled, the FMR0 register does not need to be set because the power for the flash memory is automatically turned off and is turned back on again after returning from stop or wait mode. * FMR06 Bit This is a read-only bit indicating the status of auto program operation. The bit is set to "1" when a program error occurs; otherwise, it is cleared to "0". For details, refer to the description of the full status check. * FMR07 Bit This is a read-only bit indicating the status of auto erase operation. The bit is set to "1" when an erase error occurs; otherwise, it is set to "0". For details, refer to the description of the full status check. * FMR11 Bit Setting this bit to "1" (EW1 mode) places the microcomputer in EW1 mode. * FMR40 bit The erase-suspend function is enabled by setting the FMR40 bit to "1" (valid). * FMR41 bit In EW0 mode, the flash module goes to erase-suspend mode when the FMR41 bit is set to "1". In EW1 mode, the FMR41 bit is automatically set to "1" (suspend requested) when an enabled interrupt occurred, and then the flash module goes to erase-suspend mode. The auto-erase operation restarts when the FMR41 bit is set to "0" (erase restart). * FMR46 bit The FMR46 bit is set to "0" during auto-erase execution and set to "1" during erase-suspend mode. Avoid accessing to the flash memory when this bit is set to "0".
Rev.0.91
2003 Sep 08
page 153 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.4 CPU Rewrite Mode
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR0 Bit symbol FMR00 FMR01
Address
01B716
After reset
XX0000012
00
Bit name
RY/BY status flag CPU rewrite mode select bit1
Function
0: Busy (being written or erased) 1: Ready 0: Disables CPU rewrite mode 1: Enables CPU rewrite mode 0: Enables lock bit 1: Disables lock bit 0: Enables flash memory operation 1: Stops flash memory operation (placed in low power mode, flash memory initialized) Must set to "0" 0: Terminated normally 1: Terminated in error 0: Terminated normally 1: Terminated in error
RW RO
RW
FMR02
Block1, 0 rewrite enable bit2
RW
FMSTP
Flash memory stop bit3, 5
RW
(b5-b4) FMR06 FMR07
Reserved bit Program status flag4 Erase status flag4
RW RO
RO Notes: 1. To set this bit to "1", write "0" and then "1" in succession. Make sure no interrupts will occur before writing "1" after writing "0". Set the microcomputer in read array mode before writing to this bit. 2. To set this bit to "1", write "0" and then "1" in succession when the FMR01 bit = 1. Make sure no interrupts will occur before writing "1" after writing "0". 3. Write to this bit from a program in other than the flash memory. 4. This flag is set to "0" by executing the Clear Status command. 5. Effective when the FMR01 bit = 1 (CPU rewrite mode). If the FMR01 bit = 0, although the FMSTP bit can be set to "1" by writing "1", the flash memory is neither placed in low power mode nor initialized.
Figure 17.3 FMR0 Register
Rev.0.91
2003 Sep 08
page 154 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.4 CPU Rewrite Mode
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR1 Bit symbol (b0) FMR11
Address
01B516
After reset
0100XX0X2
0
0
0
Bit name
Reserved bit EW1 mode select bit1 Reserved bit Reserved bit
Function
When read, its content is indeterminate. 0: EW0 mode 1: EW1 mode When read, its content is indeterminate. Must always be set to "0"
RW RO RW RO RW RO RW
(b3-b2) (b5-b4) (b6) (b7)
Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Reserved bit Must set to "0"
Notes: 1. To set this bit to "1", write "0" and then "1" in succession when the FMR01 bit = 1. Make sure no interrupts will occur before writing "1" after writing "0". The FMR01 and FMR11 bits both are set to "0" by setting the FMR01 bit to "0".
Flash memory control register 4
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR4 Bit symbol FMR40 FMR41 (b5-b2) FMR46
Address
01B316
After reset
0100000X2
0
0
00
0
Bit name
Erase-suspend function enable bit1 Erase-suspend request bit2 Reserved bit Erase status 0: Invalid 1: Valid
Function
RW RW RW RO RO
0: Erase restart 1: Suspend request Should set to "0" 0: Auto-erase active 1: Auto-erase inactive (erase-suspend mode)
Should set to "0" Reserved bit (b7) RW Notes: 1. To set this bit to "1", write "0" and then "1" in succession. Make sure no interrupts will occur before writing "1" after writing "0". 2. This bit is valid only when the FMR40 bit is set to "1" (valid) and can only be written before ending an erase after issuing an erase command. Other than this period, this bit is set to "1". In EW0 mode, this bit can be set to "0" and "1" by program. In EW1 mode, this bit is automatically set to "1" if a maskable interrupt occurs during an erase operation while the FMR40 bit is set to "1". This bit can not be set to "1" by program. (Can be set to "0".)
Figure 17.3-2 FMR1 Register and FMR4 Register
Rev.0.91
2003 Sep 08
page 155 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.4 CPU Rewrite Mode
Figures 17.5 and 17.6 show the setting and resetting of EW0 mode and EW1 mode, respectively.
EW0 mode operation procedure
Rewrite control program Set the FMR01 bit by writing "0" and then "1" (CPU rewrite mode enabled)2
Set CM0 and CM1 registers1
Execute software commands
Transfer a CPU rewrite mode based rewrite control program to any area other than the flash memory
Execute the Read Array command3
Jump to the rewrite control program which has been transferred to any area other than the flash memory (The subsequent processing is executed by the rewrite control program in any area other than the flash memory)
Write "0" to the FMR01 bit (CPU rewrite mode disabled)
Jump to a specified address in the flash memory
Notes: 1. Select 5 MHz or less for CPU clock using the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register. 2. To set the FMR01 bit to "1", write "0" and then "1" in succession. Make sure no interrupts will occur before writing " 1" after writing "0". Write to the FMR01 bit from a program in other than the flash memory. 3. Disables the CPU rewrite mode after executing the Read Array command.
Figure 17.4 Setting and Resetting of EW0 Mode
EW1 mode operation procedure Program in ROM
Set CM0 and CM1 registers1
Set the FMR01 bit by writing "0" and then "1" (CPU rewrite mode enabled) Set the FMR11 bit by writing "0" and then "1" (EW1 mode)2
Execute software commands
Write "0" to the FMR01 bit (CPU rewrite mode disabled) Notes: 1. Select 5 MHz or less for CPU clock using the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register. 2. To set the FMR01 bit to "1", write "0" and then "1" in succession. Make sure no interrupts will occur before writing " 1" after writing "0".
Figure 17.5 Setting and Resetting of EW1 Mode
Rev.0.91 2003 Sep 08 page 156 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.4 CPU Rewrite Mode
Ring oscillator mode ( main clock stop) program Transfer a ring oscillator mode (main clock stop) program to any area other the flash memory Set the FMR01 bit by writing "0" and then "1" (CPU rewrite mode enabled)
Jump to the ring oscillator mode (main clock stop) program which has been transferred to any area other the flash memory. (The subsequent processing is executed by a program in any area other than the flash memory.)
Set FMSTP bit to "1" (flash memory stopped. Low power state)1
Switch the clock source for CPU clock. Turn XIN off
Process of ring oscillator mode (main clock stop)
Turn main clock on wait until oscillation stabilizes switch the clock source for CPU clock2
Set the FMSTP bit to "0" (flash memory operation)
Write "0" to the FMR01 bit (CPU rewrite mode disabled)
Wait until the flash memory circuit stabilizes (10 s)3
Jump to a specified address in the flash memory
Notes: 1. Set the FMR01 bit to "1" (CPU rewrite mode) before setting the FMSTP bit to "1" . 2. Before the clock source for CPU clock can be changed, the clock to which to be changed must be stable. 3. Insert a 10 s wait time in a program. Avoid accessing to the flash memory during this wait time.
Figure 17.6 Processing Before and After Ring Oscillator Mode (Main Clock Stop)
Rev.0.91
2003 Sep 08
page 157 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.4 CPU Rewrite Mode
17.4.3 Software Commands Software commands are described below. The command code and data must be read and written in 8-bit units. Table 17.4 Software Commands
First bus cycle Command Read array Read status register Clear status register Program Block erase Mode Write Write Write Write Write Address X X X WA X Data (D7 to D0) FF16 7016 5016 4016 2016 Write Write WA BA WD D016 Read X SRD Mode Second bus cycle Address Data (D7 to D0)
SRD: Status register data (D7 to D0) WA: Write address (Make sure the address value specified in the the first bus cycle is the same address as the write address specified in the second bus cycle.) WD: Write data (8 bits) BA: Uppermost block address X: Any address in the user ROM area
* Read Array Command This command reads the flash memory. Writing `FF16' in the first bus cycle places the microcomputer in read array mode. Enter the read address in the next or subsequent bus cycles, and the content of the specified address can be read in 8-bit units. Because the microcomputer remains in read array mode until another command is written, the contents of multiple addresses can be read in succession. * Read Status Register Command This command reads the status register. Write `7016' in the first bus cycle, and the status register can be read in the second bus cycle. (Refer to Section 17.4.5, "Status Register.") When reading the status register too, specify an address in the user ROM area. Avoid executing this command in EW1 mode. * Clear Status Register Command This command sets the status register to "0". Write `5016' in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to SR5 in the status register will be set to "0".
Rev.0.91
2003 Sep 08
page 158 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.4 CPU Rewrite Mode
* Program Command This command writes data to the flash memory in one byte units. Write `4016' in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the same address as the write address specified in the second bus cycle. Check the FMR00 bit in the FMR0 register to see if auto programming has finished. The FMR00 bit is "0" during auto programming and set to "1" when auto programming is completed. Check the FMR06 bit in the FMR0 register after auto programming has finished, and the result of auto programming can be known. (Refer to Section 17.4.6, "Full Status Check.") Writing over already programmed addresses is inhibited. When the FMR02 bit in the FMR0 register is set to "0" (rewrite disabled), the Program command on the Block0 and Block1 is not accepted. In EW1 mode, do not execute this command on any address at which the rewrite control program is located. In EW0 mode, the microcomputer goes to read status register mode at the same time auto programming starts, making it possible to read the status register. The status register bit 7 (SR7) is set to "0" at the same time auto programming starts, and set back to "1" when auto programming finishes. In this case, the microcomputer remains in read status register mode until a read command is written next. The result of auto programming can be known by reading the status register after auto programming has finished.
Start Write the command code `4016' to the write address Write data to the write address
FMR00=1? YES Full status check
NO
Program completed
Figure 17.7 Program Command
Rev.0.91
2003 Sep 08
page 159 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.4 CPU Rewrite Mode
* Block Erase Write `2016' in the first bus cycle and write `D016' to the uppermost address of a block in the second bus cycle, and an auto erase operation (erase and verify) will start. Check the FMR00 bit in the FMR0 register to see if auto erasing has finished. The FMR00 bit is "0" during auto erasing and set to "1" when auto erasing is completed. When using the erase-suspend function in EW0 mode, the FMR46 bit in the FMR4 register should be checked to see if the flash memory is placed in a erase-suspend. The FMR46 bit is set to "0" when auto-erase operation is active and set to "0" auto-erase operation is inactive. Check the FMR07 bit in the FMR0 register after auto erasing has finished, and the result of auto erasing can be known. (Refer to Section 17.4.6, "Full Status Check.") When the FMR02 bit in the FMR0 register is set to "0" (rewrite disabled), the Block Erase command on the Block0 and Block1 is not accepted. Figure 17.9 shows an example of a block erase flowchart when the erase-suspend function is not used. Figure 17.10 shows an example of a block erase flowchart when the erase-suspend function is used. In EW1 mode, do not execute this command on any address at which the rewrite control program is located. In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to "0" at the same time auto erasing starts, and set back to "1" when auto erasing finishes. In this case, the microcomputer remains in read status register mode until the Read Array command is written next.
Start
Write the command code `2016' Write `D016' to the uppermost block address
FMR00=1? YES Full status check
NO
Block erase completed
Figure 17.8 Block Erase Command (When Not Using Erase-suspend Function)
Rev.0.91
2003 Sep 08
page 160 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.4 CPU Rewrite Mode
Start Interrupt
FMR40=1
FMR40=1
Write the command code `2016' Write `D016' to the uppermost block address FMR46=1? YES Access to flash memory FMR00=1? YES Full status check REIT NO FMR41=0 NO
Block erase completed
Start Interrupt
FMR40=1
Access to flash memory
Write the command code `2016' Write `D016' to the uppermost block address
REIT
FMR41=0
FMR00=1? YES Full status check
NO
Block erase completed
Notes: 1. In EW0 mode, interrupt vector table and interrupt routine for an interrupt used should be located in the RAM space.
Figure 17.9 Block Erase Flow Chart (When Using Erase-suspend Function)
Rev.0.91 2003 Sep 08 page 161 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.4 CPU Rewrite Mode
17.4.4 Status Register The status register indicates the operating status of the flash memory and whether an erase or programming operation terminated normally or in error. The status of the status register can be known by reading the FMR00, FMR06, and FMR07 bits in the FMR0 register. Table 17.5 lists the status register. In EW0 mode, the status register can be read in the following cases: (1) When a given address in the user ROM area is read after writing the Read Status Register command (2) When a given address in the user ROM area is read after executing the Program or Block Erase command but before executing the Read Array command. * Sequencer Status (SR7 and FMR00 Bits ) The sequence status indicates the operating status of the flash memory. SR7 = 0 (busy) during auto programming and auto erase, and is set to "1" (ready) at the same time the operation finishes. SR7 = 0 (busy) during erase suspend mode. * Erase Status (SR5 and FMR07 Bits) Refer to Section 17.4.6, "Full Status Check." * Program Status (SR4 and FMR06 Bits) Refer to Section 17.4.6, "Full Status Check." Table 17.5 Status Register FMR0 Status Status name register register bit bit SR7 (D7) Sequencer status FMR00
Contents "0" Busy Terminated normally Terminated normally "1" Ready Terminated in error Terminated in error -
Value after reset 1
SR6 (D6) SR5 (D5) SR4 (D4) SR3 (D3) SR2 (D2) SR1 (D1) FMR07 FMR06
Reserved Erase status Program status Reserved Reserved Reserved
0 0
Reserved SR0 (D0) * D7 to D0: Indicates the data bus which is read out when the Read Status Register command is executed. * The FMR07 bit (SR5) and FMR06 bit (SR4) are set to "0" by executing the Clear Status Register command. * When the FMR07 bit (SR5) or FMR06 bit (SR4) = 1, the Program and Block Erase commands are not accepted.
Rev.0.91
2003 Sep 08
page 162 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.4 CPU Rewrite Mode
17.4.5 Full Status Check When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to "1", indicating occurrence of each specific error. Therefore, execution results can be verified by checking these status bits (full status check). Table 17.6 lists errors and FMR0 register status. Figure 17.11 shows a full status check flowchart and the action to be taken when each error occurs. Table 17.6 Errors and FMR0 Register Status FRM00 register (status register) status FMR07 FMR06 (SR5) (SR4) 1 1
Error
Error occurrence condition
1 0
0 1
Command * When any command is not written correctly sequence error * When invalid data was written other than those that can be written in the second bus cycle of the Block Erase command (i.e., other than `D016' or `FF16')1 Erase error * When the Block Erase command was executed but not automatically erased correctly Program error * When the Program command was executed but not automatically programmed correctly.
Notes: 1. Writing `FF16' in the second bus cycle of these commands places the microcomputer in read array mode, and the command code written in the first bus cycle is nullified.
Rev.0.91
2003 Sep 08
page 163 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.4 CPU Rewrite Mode
Full status check
FMR06 =1 and FMR07=1?
YES
Command sequence error
(1) Execute the Clear Status Register command to set these status flags to "0". (2) Re-execute the command after checking that it is entered correctly.
NO NO (1) Execute the Clear Status Register command to set the erase status flag to "0". (2) Re-execute the Block Erase command. Note 1: If the error still occurs, the block in error cannot be used.
FMR07= 0? YES
Erase error
FMR06= 0? YES
NO
Program error
[During programming] (1) Execute the Clear Status Register command to set the program status flag to "0". (2) Re-execute the Program command. Note 2: If the error still occurs, the block in error cannot be used.
Full status check completed
Note 3: If FMR06 or FMR07 = 1, neither the Program nor Block Erase command is accepted. Execute the Clear Status Register command before executing those commands.
Figure 17.10 Full Status Check and Handling Procedure for Each Error
Rev.0.91
2003 Sep 08
page 164 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.5 Standard Serial I/O Mode
17.5 Standard Serial I/O Mode
In standard serial input/output mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a serial programmer suitable for this microcomputer. For more information about serial programmers, contact the manufacturer of your serial programmer. For details on how to use, refer to the user's manual included with your serial programmer. Table 17.7 lists pin functions (flash memory standard serial input/output mode). Figures 17.12 to 17.14 show pin connections for standard serial input/output mode. 17.5.1 ID Code Check Function This function determines whether the ID codes sent from the serial programmer and those written in the flash memory match (refer to Section 17.3, "Functions to Prevent Flash Memory from Rewriting").
Rev.0.91
2003 Sep 08
page 165 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.5 Standard Serial I/O Mode
Table 17.7 Pin Functions (Flash Memory Standard Serial I/O Mode)
Pin VCC,VSS IVCC RESET Name Power input IVCC Reset input I I/O Description Apply the voltage guaranteed for Program and Erase to Vcc pin and 0V to Vss pin. Connect capacitor (0.1 F) to Vss. Reset input pin. While RESET pin is "L" level, input a 20 cycle or longer clock to X IN pin. Connect a ceramic resonator or crystal oscillator between X IN and XOUT pins in standard serial I/O mode 2. In standard serial I/O mode 1, connect a ceramic resonator or crystal oscillator between X IN and XOUT pins, or input "H" or "L" level signal, or open. Connect AVss to Vss and AVcc to Vcc, respectively. Enter the reference voltage for AD from this pin. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Serial data output pin Standard serial I/O mode 1: connect to flash programmer Standard serial I/O mode 2: Input "L". Standard serial I/O mode 1: connect to flash programmer Standard serial I/O mode 2: Input "L". Serial data input pin
P46/XIN P47/XOUT AVCC, AVSS VREF P00 to P06 P10 to P17 P30 to P33 P45 P07 MODE CNVSS P37
P46 input/Clock input P47 input/Clock output Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P3 Input port P4 TxD output MODE CNVSS RxD input
I I/O I I I I I I O I/O I/O O
Rev.0.91
2003 Sep 08
page 166 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.5 Standard Serial I/O Mode
24 23 22 21 20 19 18 17 25 26 27 28 29 30 31 32 1 2345678 16 15 14 13 12 11 10 9
MODE
R8C/11
Vss
TxD
Vcc
RxD
Signal
Value Voltage from programmer Voltage from programmer Voltage from programmer
RESET
Mode Setting
Connect oscillator circuit1 Notes: 1: No need to connect an oscillation circuit when operating with ring oscillator clock.
CNVss MODE RxD RESET
Vss -->Vcc
CNVss
Package: 32P6U-A
Figure 17.11 Pin Connections for Standard Serial I/O Mode
Rev.0.91
2003 Sep 08
page 167 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
17.5 Standard Serial I/O Mode
* Example of Circuit Application in the Standard Serial I/O Mode Figures 17.13 and 17.14 show examples of circuit application in standard serial I/O mode 1 and mode 2, respectively. Refer to the serial programmer manual of your programmer to handle pins controlled by the programmer.
Microcomputer MODE input/output CNVss input Data output Data input MODE CNVss TxD RxD
Reset input User reset signal
RESET
(1) Control pins and external circuitry will vary according to programmer. For more information, see the programmer manual. (2) In this example, modes are switched between single-chip mode and standard serial input/output mode by connecting a programmer.
Figure 17.12 Circuit Application in Standard Serial I/O Mode 1
Microcomputer CNVss Data output TxD
Data input
RxD MODE
(1) In this example, modes are switched between single-chip mode and standard serial input/output mode by controlling the MODE input with a switch.
Figure 17.13 Circuit Application in Standard Serial I/O Mode 2
Rev.0.91
2003 Sep 08
page 168 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
18. On-chip Debugger
18. On-chip debugger
The microcomputer has functions to execute the on-chip debugger. Refer to "Appendix 2 Connecting examples for serial writer and on-chip debugging emulator". Refer to the respective on-chip debugger manual for the details of the on-chip debugger. Next, here are some explanations for the respective functions. Debugging the user system which uses these functions is not available. When using the onchip debugger, design the system without using these functions in advance. Additionally, the on-chip debugger uses the address "0C00016 to 0C7FF16 of the flash memory, thus avoid using for the user system.
18.1 Address match interrupt
The interrupt request is generated right before the arbitrary address instruction is executed. The debugger break function uses the address match interrupt. Refer to "10.4 Address match interrupt" for the details of the address match interrupt. Also, avoid using the address match interrupt with using the user system when using the on-chip debugger.
18.2 Single step interrupt
The interrupt request is generated every time one instruction is executed. The debugger single step function uses the single step interrupt. The other interrupt is not generated when using the single step interrupt. The single step interrupt is only for the developed support tool.
18.3 UART1
The UART1 is used for the communication with the debugger (or the personal computer). Refer to "13. Serial I/O" for the details of UART1. Also, avoid using the UART1 and the functions (P00/AN7 and P37) which share the UART1 pins.
18.4 BRK instruction
The BRK interrupt request is generated. Refer to "10.1 Interrupt overview" and "R8C/Tiny series software manual". Also, avoid using the BRK instruction with using the user system when using the on-chip debugger.
Rev.0.91
2003 Sep 08
page 169 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
19. Usage Notes
19. Usage Notes
19.1 Stop Mode and Wait Mode
When entering stop mode or wait mode, an instruction queue pre-reads 4 bytes from the WAIT instruction or an instruction that sets the CM10 bit in the CM1 register to "1" (all clocks stopped) before the program stops. Therefore, insert at least four NOPs after the WAIT instruction or an instruction that sets the CM10 bit to "1".
19.2 Interrupts
19.2.1 Reading Address 0000016 Avoid reading the address 0000016 in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is set to "0". If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to "0". This may cause a problem that the interrupt is canceled, or an unexpected interrupt is generated. 19.2.2 SP Setting Set any value in the SP before accepting an interrupt. The SP is set to `000016' after reset. Therefore, if an interrupt is accepted before setting any value in the SP, the program may go out of control. 19.2.3 External Interrupt and Key Input Interrupt _____ Either an "L" level or an "H" level of at least 250 ns width is necessary for the signal input to the INT0 _____ to INT3 pins and KI0 to KI3 pins regardless of the CPU clock. 19.2.4 Watchdog Timer Interrupt Initialize the watchdog timer after a watchdog timer interrupt occurs. 19.2.5 Changing Inerrupt Source The IR bit in the corresponding interrupt control register may be set to "1" (interrupt requested) when the interrupt source changes. When using an interrupt, the corresponding IR bit should be set to "0" (no interrupt requested) after changing the interrupt source. In addition, the changes of interrupt sources said here include all factors that change the interrupt sources assigned to individual software interrupt numbers, polarities, and timing. Therefore, when a mode change in the peripheral functions etc. involves interrupt sources, edge polarities, and timing, the corresponding IR bit should be set to "0" (no interrupt requested) after the change. Refer to the description of each peripheral function for the interrupts caused by the peripheral functions. Figure 1.1 shows an example of the procedure for changing interrupt sources.
Rev.0.91
2003 Sep 08
page 170 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
19. Usage Notes
Interrupt factor change
Interrupt disabled1, 2
Change interrupt source (including mode change of peripheral functions) Set IR bit to "0" (interrupt not requested) using MOV instruction2 Enable interrupt1, 2
Change completed * IR bit: The corresponding interrupt control register bit of an interrupt by which an interrupt source is changed. * The setting above should be performed individually. Avoid executing two or more settings at once (by one instruction). Notes: 1. The I flag should be used for the INTi (i=0 to 3) interrupt. To prevent interrupt requests from being generated when using a peripheral function interrupt other than the INTi interrupt, the corresponding peripheral function should be disabled before changing the interrupt factor. In this case, the I flag should be used when all maskable interrupts can be disabled. When not all maskable interrupts can be disabled, the ILVL2 to ILVL0 bits of the corresponding interrupt should be used. 2. Refer the paragraph 1.2.6 "Changing Interrupt Control Register" for the instructions to be used and their usage notes.
Figure 19.1 Example of Procedure for Changing Interrupt Source
Rev.0.91
2003 Sep 08
page 171 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
19. Usage Notes
19.2.6 Changing Interrupt Control Register (1) Each interrupt control register can only be modified while no interrupt requests corresponding to that register are generated. If interrupt requests managed by any interrupt control register are likely to occur, disable the interrupts before changing the interrupt control register. (2) To modify any interrupt control register after disabling interrupts, be careful with the instructions used. When Changing Other Than IR Bit If an interrupt request corresponding to that register is generated while executing the instruction, the IR bit may not be set to "1" (interrupt requested), with the result that the interrupt request is ignored. If this presents a problem, use the following instructions to modify the register. Instructions to use: AND, OR, BCLR, BSET When Changing IR Bit Even when the IR bit is cleared to "0" (interrupt not requested), it may not actually be cleared to "0" depending on the instruction used. Therefore, use the MOV instruction to set the IR bit to "0". (3) When disabling interrupts using the I flag, set the I flag according to the following sample programs. Refer to #2 for the change of interrupt control registers in the sample programs. Sample programs 1 to 3 are to prevent the I flag from being set to "1" (interrupt enabled) before writing to the interrupt control registers for reasons of the internal bus or the instruction queue buffer.
Example 1: Use NOP instructions to prevent I flag being set to "1" before interrupt control register is changed
INT_SWITCH1: FCLR I ; Disable interrupts AND.B #00H, 0056H ; Set TXIC register to "0016" NOP NOP FSET I ; Enable interrupts
Example 2: Use dummy read to have FSET instruction wait
INT_SWITCH2: FCLR I AND.B #00H, 0056H MOV.W MEM, R0 FSET I ; Disable interrupts ; Set TXIC register to "0016" ; Dummy read ; Enable interrupts
Example 3: Use POPC instruction to change I flag
INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts AND.B #00H, 0056H ; Set TXIC register to "0016" POPC FLG ; Enable interrupts
Rev.0.91
2003 Sep 08
page 172 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
19. Usage Notes
19.3 Timers
19.3.1 Timers X, Y and Z (1) Timers X, Y and Z stop counting after reset. Therefore, a value must be set to these timers and prescalers before starting counting. (2) Even if the prescalers and timers are read out simultaneously in 16-bit units, these registers are read byte-by-byte in the microcomputer. Consequently, the timer value may be updated during the period these two registers are being read. 19.3.2 Timer X (1) In pulse period measurement mode, the TXEDG bit and TXUND bit in the TXMR register can be set to "0" by writing "0" to these bits in a program. However, these bits remain unchanged when "1" is written. To set one flag to "0" in a program, write "1" to the other flag by using the MOV instruction. (This prevents any unintended changes of flag.) Example (when setting TXEDG bit to "0"): MOV.B #10XXXXXXB,008BH (2) When changing to pulse period measurement mode from other mode, the contents of the TXEDG bit and TXUND bit are indeterminate. Write "0" to the TXEDG bit and TXUND bit before starting counting. 19.3.3 Timer Z In programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the TZS bit in the TC register to "0" and the timer reloads the value of reload register and stops. Therefore, the timer count value should be read out in programmable one-shot generation mode and programmable wait one-shot generation mode before the timer stops. 19.3.4 Timer C (1) The TC register and TM0 register must be read in 16-bit units. This prevents the timer value from being updated during the period the high-byte and low-byte are being read. Example (when Timer C is read): MOV.W 0090H,R0 ; Read out timer C
Rev.0.91
2003 Sep 08
page 173 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
19. Usage Notes
19.4 Serial I/O
(1) When reading data from the UiRB (i=0,1) register even in the clock asynchronous serial I/O mode or in the clock synchronous serial I/O mode. Be sure to read data in 16-bit unit. When the high-byte of the UiRB register is read, the PER and FER bits of the UiRB register and the RI bit of the UiC1 register are set to "0". Example (when reading receive buffer register): MOV.W 00A6H, R0 ; Read the U0RB register (2) When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data length, data should be written high-byte first then low-byte in 8-bit unit. Example (when reading transmit buffer register): MOV.B #XXH, 00A3H ; Write the high-byte of U0TB register MOV.B #XXH, 00A2H ; Write the low-byte of U0TB register
Rev.0.91
2003 Sep 08
page 174 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
19. Usage Notes
19.5 A-D Converter
(1) When writing to each bit but except bit 6 in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit in the ADCON2 register, A/D conversion must be stopped (before a trigger occurs). When the VCUT bit in the ADCON1 register is changed from "0" (VREF not connected) to "1" (VREF connected), wait at least 1 s before starting A/D conversion. (2) When changing AD operation mode, select an analog input pin again. (3) In one-shot mode, A/D conversion must be completed before reading the AD register. The IR bit in the ADIC register can indicates whether the A/D conversion is completed or not. (4) In repeat mode, the undivided main clock must be used for the CPU clock. (5) If A/D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0 register to "0" (A/D conversion halted), the conversion result of the A/D converter is indeterminate. If the ADST bit is set to "0" in a program, ignore the value of AD register. (6) A 0.1 F capacitor should be connected between the AVcc/VREF pin and AVss pin.
Rev.0.91
2003 Sep 08
page 175 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
19. Usage Notes
19.6 Flash Memory Version
19.6.1 CPU Rewrite Mode (1) Operation Speed Before entering CPU rewrite mode (EW0 or EW1 mode), select 5 MHz or less for CPU clock using the CM06 bit in the CM0 register and the CM16 to CM17 bits in the CM1 register. (2) Instructions Inhibited Against Use The following instructions cannot be used in EW0 mode because the flash memory's internal data is referenced: UND instruction, INTO instruction, and BRK instruction (3) Interrupts EW0 Mode * Any interrupt which has a vector in the relocatable vector table can be used providing that its vector is transferred into the RAM space. * The watchdog timer and oscillation stop detection interrupts can be used because the FMR0 register and FMR1 register are initialized when one of those interrupts occurs. The jump addresses for those interrupt service routines should be set in the fixed vector table. Because the rewrite operation is halted when a watchdog timer, oscillation stop detection or voltage detection interrupt occur, the rewrite program should be executed again after exiting the interrupt service routine. * The address match interrupt cannot be used because the flash memory's internal data is referenced. EW1 Mode * Make sure that any interrupt which has a vector in the variable vector table or address match interrupt will not be accepted during the auto program period or the auto erase period with erasesuspend function disabled. * Avoid using watchdog timer interrupts. (4) How to Access To set the FMR01, FMR02, or FMR11 bit to "1", write "0" and then "1" in succession. This is necessary to ensure that no interrupts will occur before writing "1" after writing "0". (5) Writing in User ROM Space In EW0 Mode, if the power supply voltage drops while rewriting any block in which the rewrite control program is stored, a problem may occur that the rewrite control program is not correctly rewritten and, consequently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial I/O or parallel I/O mode should be used. (6) Wait Mode When shifting to wait mode, set the FMR01 bit to "0" (CPU rewrite mode disabled) before executing the WAIT instruction.
Rev.0.91
2003 Sep 08
page 176 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
19. Usage Notes
(7) Stop Mode When shifting to stop mode, the following settings are required: * Set the FMR01 bit to "0" (CPU rewrite mode disabled) and disable DMA transfers before setting the CM10 bit to "1" (stop mode). * Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to "1" (stop mode) Example program BSET JMP.B L1: Program after returning from stop mode (8) Ring Oscillator Low Power Dissipation Mode If the CM05 bit is set to "1" , the following commands must not be executed. * Program * Block erase 0, CM1 L1 ; Stop mode
Rev.0.91
2003 Sep 08
page 177 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
19. Usage Notes
19.7 Noise
(1) Bypass Capacitor between VCC and VSS Pins Insert a bypass capacitor (at least 0.1 F) between VCC and VSS pins as the countermeasures against noise and latch-up. The connecting wires must be the shortest and widest possible. (2) Port Control Registers Data Read Error During severe noise testing, mainly power supply system noise, and introduction of external noise, the data of port related registers may changed. As a firmware countermeasure, it is recommended to periodically reset the port registers, port direction registers and pullup control registers. However, you should fully examine before introducing the reset routine as conflicts may be created between this reset routine and interrupt routines (i. e. ports are switched during interrupts). (3) CNVss Pin Wiring In order to improve the pin tolerance to noise, insert a pull down resistance (about 5 k ) between CNVss and Vss, and placed as close as possible to the CNVss pin.
Rev.0.91
2003 Sep 08
page 178 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
20. Usage Notes for On-chip Debugger
20. Usage notes for on-chip debugger
When using the on-chip debugger to develop the R8C/11 group program and debug, pay the following attention. (1) Avoid using P00/AN7/TxD11 pin and P37/TxD10/RxD1 pin. (2) When write in the PD3 register (00E716 address), set bit 7 to "0". (3) Avoid accessing the related serial I/O1 register. (4) Avoid using from OC00016 address to OC7FF16 address because the on-chip debagger uses these addresses.
Rev.0.91
2003 Sep 08
page 179 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
32P6U-A
MMP
JEDEC Code - HD D
32 25
Plastic 32pin 77mm body LQFP
Weight(g) Lead Material Cu Alloy e MD
EIAJ Package Code LQFP32-P-0707-0.80
I2
1 24
Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp
A3
8
17
9
16
E HE
A
L1 A2
A3
e
F
A1
L
Lp
b
c
x y b2 I2 MD ME
x
M
y
Detail F
Rev.0.91
2003 Sep 08
page 180 of 184
b2
Dimension in Millimeters Min Nom Max - - 1.7 0.1 0.2 0 - - 1.4 0.32 0.37 0.45 0.105 0.125 0.175 6.9 7.0 7.1 6.9 7.0 7.1 0.8 - - 8.8 9.0 9.2 8.8 9.0 9.2 0.3 0.5 0.7 1.0 - - 0.6 0.75 0.45 - 0.25 - - - 0.2 0.1 - - 0 10 - 0.5 - - 1.0 - - 7.4 - - - - 7.4
ME
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
Appendix 2. Connecting Examples for Serial Writer and On-chip Debugging Emulator
Appendix 2. Connecting examples for serial writer and on-chip debugging emulator Appendix figure 2.1 shows connecting examples with USB Flash Writer and appendix figure 2.2 shows connecting examples with M16C Flash Starter.
24 23 22 21 20 19 18 17
33 k MODE
25 26 27 28 29 30
R8C/11
16 15 14 13 12 11 10 9
Vss
TxD
10 TxD
31 32 1 2345678
Vcc
8
RESET
7 Vss 3 CNVss 1 Vcc
4 RxD MODE 2
Connect oscillator circuit1
USB Flash Writer (M3A-0665)
RxD
User reset signal
CNVss
Notes: 1: No need to connect an oscillation circuit when operating with ring oscillator clock.
Appendix figure 2.1 Connecting examples with USB Flash Writer (M3A-0665)
24 23 22 21 20 19 18 17 25 26 27 16 15 14 R8C/11 13 12 11 10 9 1 2345678
MODE
28 29 30 31 32
Vss
TxD
Vcc
10 TxD 7 Vss 4 RxD 1 Vcc
Connet oscillator circuit1
M16C Flash Starter (M3A-0806)
CNVss
RESET
RxD
Note: 1: Need to connect the oscillator circuit
Appendix figure 2.2 Connecting examples with M16C Flash Starter (M3A-0806)
Rev.0.91 2003 Sep 08 page 181 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
Appendix 2. Connecting Examples for Serial Writer and On-chip Debugging Emulator
Appendix figure 2.3 shows connecting examples with emulator E7.
24 23 22 21 20 19 18 17 25 26 27 28 29 30 16 15 14 13 12 11 10 9 1 2345678
MODE
R8C/11
Vss
TxD
31 32
Vcc
14 12 10 8 Vcc 6 4 2 Vss
13
RESET
11 RxD 7 MODE 5 TxD 1 CNVss
Connect oscillator circuit1
Emulator E7 (HS0007TCU01H)
RxD
User reset signal
Note: 1: No need to connect an oscillation circuit when operating with ring oscillator clock.
Appendix figure 2.3 Connecting examples with emulator E7 (HS0007TCU01H )
Rev.0.91
2003 Sep 08
page 182 of 184
CNVss
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
Register Index
Register Index
A
AD 122 ADCON0 121, 124, 126 ADCON1 121, 124, 126 ADCON2 122 ADIC 49 AIER 63
P
P0 133 P1 133 P3 133 P4 133 PD0 133 PD1 133 PD3 133 PD4 133 PM0 41 PM1 41 PRCR 40 PREX 68 PREY 77 PREZ 85 PUM 78, 80, 82, 86, 88, 90, 92, 95 PUR0 134 PUR1 134
C
CM0 27 CM1 27 CMP1IC 49 CMP2IC 49
D
D4INT 20 DRR 134
F
FMR0 142 FMR1 142 FMR4 143
R
RMAD0 to RMAD1 63
H
HR0 HR1 29 29
S
S0RIC S0TIC S1RIC S1TIC 49 49 49 49
I
INT0F INT0IC INT1IC INT2IC INT3IC INTEN 56 49 49 49 49 56
T
TC 99 TCC0 60, 99 TCC1 60, 100 TCIC 49 TCOUT 100 TCSS 68, 78, 86 TM0 99 TM1 99 TX 68 TXIC 49 TXMR 58, 67, 69, 70, 71, 72, 74
K
KIEN 61 KUPIC 49
O
OCD 28
Rev.0.91
2003 Sep 08
page 183 of 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
Register Index
TYIC 49 TYPR 77 TYSC 77 TYZMR 58, 76, 80, 82, 84, 88, 90, 92, 95 TYZOC 77, 85 TZIC 49 TZPR 85 TZSC 85
U
U0BRG 107 U0C0 108 U0C1 109 U0MR 108 U0RB 107 U0TB 107 U1BRG 107 U1C0 108 U1C1 109 U1MR 108 U1RB 107 U1TB 107 UCON 109
V
VCR1 20 VCR2 20
W
WDC 65 WDTR 65 WDTS 65
Rev.0.91
2003 Sep 08
page 184 of 184
REVISION HISTORY
Rev. Date Page 0.91 Sep 08, 2003 - First edition issued
R8C/11 Group Hardware Manual
Description Summary
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER HARDWARE MANUAL R8C/11 Group Publication Data : Rev.0.91 Sep 08, 2003 Published by : Sales Strategic Planning Div. Renesas Technology Corp.
(c) 2003. Renesas Technology Corp., All rights reserved. Printed in Japan.
R8C/11 Group Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan

▲Up To Search▲

Price & Availability of R8C11

	To Download R8C11 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .