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Final Electrical Specifications
LT5512 DC-3GHz High Signal Level Down-Converting Mixer
July 2002
FEATURES
s s
DESCRIPTIO
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Broadband RF, LO and IF Operation High Input IP3: +20dBm at 950MHz +17dBm at 1900MHz Typical Conversion Gain: 1dB at 1900MHz SSB Noise Figure: 14dB at 1900MHz Integrated LO Buffer: Insensitive to LO Drive Level Single-Ended or Differential LO Signal High LO-RF Isolation Enable Function 4.5V to 5.25V Supply Voltage Range 4mm x 4mm QFN Package
The LT(R)5512 is a broadband mixer IC optimized for high linearity downconverter applications including cable and wireless infrastructure. The IC includes a differential LO buffer amplifier driving a double-balanced mixer. An integrated RF buffer amplifier improves LO-RF isolation and eliminates the need for precision external bias resistors. The LT5512 is a high-linearity alternative to passive diode mixers. Unlike passive mixers, which have conversion loss and require high LO drive levels, the LT5512 delivers conversion gain and requires significantly lower LO drive levels.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s s s
Cellular/PCS/UMTS Infrastructure CATV Downlink Infrastructure High Linearity Mixer Applications
TYPICAL APPLICATIO
5V 1850MHz TO 1910MHz LNA 1850MHz TO 1910MHz
EN 1:2 RF
+
VCC1
VCC2
+
170MHz (TYP)
IF VGA A/D
IF
RF -
POUT, IM3 (dBm/TONE)
IF -
LO
+
LO-
LO INPUT -10dBm
5512 F01a
Figure 1. High Signal-Level Downmixer for Wireless Infastructure
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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Output IF Power and Output IM3 vs RF Input Power (Two Input Tones)
10 0 -10 -20 -30 -40 -50 -60 -70 TA = 25C PLO = -10dBm fLO = 1730MHz fRF1 = 1899.9MHz fRF2 = 1900.1MHz 6 IM3 IFOUT -80 3 -21 -18 -15 -12 -9 -6 -3 0 RF INPUT POWER (dBm/TONE)
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LT5512
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
Supply Voltage ....................................................... 5.5V Enable Voltage ............................... -0.3V to VCC + 0.3V LO + to LO - Differential Voltage ............................ 1.5V ................................................... (+6dBm equivalent) + to RF - Differential Voltage ............................. 0.7V RF .................................................. (+10dBm equivalent) Operating Temperature Range .................-40C to 85C Storage Temperature Range ..................-65C to 125C Lead Temperature (Soldering, 10 sec).................. 300C
LO -
LO+
NC
16 15 14 13 NC 1 RF + 2 RF - 3 NC 4 5 6 7 8 12 GND 11 IF+ 10 IF - 9 GND
NC
ORDER PART NUMBER LT5512EUF
VCC1
VCC2
UF PACKAGE 16-LEAD (4mm x 4mm) PLASTIC QFN TJMAX = 125C, JA = 37C/W EXPOSED PAD IS GROUND (MUST BE SOLDERED TO PRINTED CIRCUIT BOARD)
NC
EN
PART MARKING 5512
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
PARAMETER RF Input Frequency Range2 LO Input Frequency Range2 IF Output Frequency Range2 CONDITIONS Requires Appropriate Matching Requires Appropriate Matching Requires Appropriate Matching MIN TYP DC to 3000 DC to 3000 DC to 2000 MAX UNITS MHz MHz MHz
1900MHz Downmixer Application: (Test Circuit Shown in Figure 2) VCC = 5VDC, EN = High, TA = 25C, RF input = 1900MHz at -10dBm, LO input = 1730MHz at -10dBm, IF output measured at 170MHz, unless otherwise noted. (Notes 2, 3)
LO Input Power Conversion Gain Input 3rd Order Intercept LO to RF Leakage LO to IF Leakage RF to LO Isolation Output 1dB Compression LO Input Common Mode Voltage Single-Sideband Noise Figure Internally Biased 2-Tone, -10dBm/Tone, f = 200kHz -1 -15 to -5 1 17 -53 -46 50 6.2 2 14 dBm dB dBm dBm dBm dB dBm VDC dB
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LT5512
1230MHz Cable Infrastructure Downmixer Application: (Test Circuit Shown in Figure 3) VCC = 5VDC, EN = High, TA = 25C, RF input = 1230MHz at -10dBm, LO input swept from 1500MHz to 2100MHz, PLO = -10dBm, IF output measured from 270MHz to 870MHz, unless otherwise noted.
PARAMETER Conversion Gain Input 3rd Order Intercept LO to RF Leakage LO to IF Leakage RF to LO Isolation 2 * RF - LO Output Spur Single-Sideband Noise Figure fIF = 570MHz, PRF = -18dBm, fLO = 1800MHz fLO = 1800MHz, fIF = 570MHz CONDITIONS fLO = 1800MHz, fIF = 570MHz 2-Tone RF Input, -10dBm/Tone, f = 1MHz, fLO = 1800MHz, fIF = 570MHz MIN TYP 2.8 17.9 -56 - 40 51 - 60 13.3 MAX UNITS dB dBm dBm dBm dB dBc dB
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
(Note 3), unless otherwise noted.
PARAMETER Enable (EN) Low = Off, High = On Turn On Time Turn Off Time Input Current Enable = High (On) Enable = Low (Off) Power Supply Requirements (VCC) Supply Voltage Supply Current Shutdown Current EN = Low
(Test Circuit Shown in Figure 2) VCC = 5VDC, EN = High, TA = 25C
MIN TYP 3 13 MAX UNITS s s A VDC 0.3 4.50 57 5.25 74 100 VDC VDC mA A
CONDITIONS
VENABLE = 5VDC 3
50
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: External components on the final test circuit are optimized for operation at fRF = 1900MHz, fLO = 1730MHz and fIF = 170MHz (Figure 2).
Note 3: Specifications over the -40C to 85C temperature range are assured by design, characterization and correlation with statistical process controls.
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
59 58
56 55 54 53 52 51 50 49 4.5 4.75 5.25 5.0 SUPPLY VOLTAGE (V) 5.5
5512 G01
SHUTDOWN CURRENT (A)
57
SUPPLY CURRENT (mA)
UW
(Test Circuit Shown in Figure 2) Shutdown Current vs Supply Voltage
100
TA = 85C TA = 25C
10
TA = 85C
TA = -40C
TA = 25C 1 TA = -40C
0.1 4.5
5.0 5.25 4.75 SUPPLY VOLTAGE (V)
5.5
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LT5512 TYPICAL PERFOR A CE CHARACTERISTICS
Conv Gain, IIP3 and SSB NF vs RF Frequency (Low-Side LO)
18 18
CONV GAIN (dB), NF (dB), IIP3 (dBm)
(1900MHz Downmixer Application) VCC = 5VDC, EN = High, TA = 25C, 1900MHz RF input matching, RF input = 1900MHz at -10dBm, LO input = 1730MHz at -10dBm, IF output measured at 170MHz, unless otherwise noted. (Test circuit shown in Figure 2). Conv Gain, IIP3 and SSB NF vs RF Frequency (High-Side LO)
20 IIP3 SSB NF fIF = 170MHz TA = 25C
CONV GAIN (dB), IIP3 (dBm)
CONV GAIN (dB), NF (dB), IIP3 (dBm)
16 14 12 10 8 6 4 2 0 1700
IIP3
SSB NF
fIF = 170MHz TA = 25C
CONV GAIN 1900 2000 1800 RF FREQUENCY (MHz) 2100
5512 * G03
Conv Gain and IIP3 vs LO Input Power
20 18 TA = 25C TA = -40C IIP3 TA = 85C
SSB NF (dB)
CONV GAIN (dB), IIP3 (dBm)
16 14 12 10 8 6 4 2 CONV GAIN TA = -40C
LO LEAKAGE (dBm)
TA = 25C TA = 85C
0 -18 -16 -14 -12 -10 -8 -6 LO INPUT POWER (dBm)
Conv Gain and IIP3 vs Supply Voltage
18 16 TA = 25C TA = -40C TA = 85C IIP3
POUT, IM3 (dBm/TONE)
CONV GAIN (dB), IIP3 (dBm)
14 12 10 8 6 4 2 0 4.5 CONV GAIN TA = -40C
RETURN LOSS (dB)
TA = 25C
4.75 5.25 5.0 SUPPLY VOLTAGE (V)
4
UW
-4
5512 * G06
Conv Gain and IIP3 vs Temperature RF = 1900MHz, IF = 170MHz
18 16 14 12 10 8 6 4 2 0 2100 -50 -25 CONV GAIN HIGH-SIDE LO LOW-SIDE LO 0 25 50 TEMPERATURE (C) 75 100 IIP3 LOW-SIDE LO HIGH-SIDE LO
16 14 12 10 8 6 4 2 0 1700
CONV GAIN
1800 2000 1900 RF FREQUENCY (MHz)
5512 * G04
5512 * G05
SSB Noise Figure vs LO Input Power
16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 -2 12.0 -18 -16 -14 -12 -10 -8 -6 LO INPUT POWER (dBm) -4 -2 LOW-SIDE LO HIGH-SIDE LO fRF = 1900MHz fIF = 170MHz TA = 25C -20 -25 -30 -35 -40 -45 -50
LO-IF and LO-RF Leakage vs LO Input Power
fLO = 1730MHz TA = 25C
LO-IF
LO-RF -55 -60 -18 -16 -14 -12 -10 -8 -6 LO INPUT POWER (dBm)
-4
-2
5512 * G07
5512 * G08
Output IF Power and Output IM3 vs RF Input Power (Two Input Tones)
10 0 -10 POUT -20 -30 -40 -50 -60 -70 -80
5.5
5512 * G09
RF, LO and IF Port Return Loss vs Frequency
0
TA = -40C
-5
TA = 85C TA = 25C TA = 85C
-10 -15 IF -20 RF -25 -30
LO
IM3
TA = -40C TA = 25C
TA = 85C
-90 0 -21 -18 -15 -12 -9 -6 -3 RF INPUT POWER (dBm/TONE)
TA = 25C 0 500 1000 1500 2000 FREQUENCY (MHz) 2500 3000
3
5512 G10
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LT5512 TYPICAL PERFOR A CE CHARACTERISTICS
Conv Gain, IIP3 and SSB NF vs IF Output Frequency
20 CONV GAIN (dB), NF (dB), IIP3 (dBm) 18 16 14 12 10 8 6 4 2 0 270 CONV GAIN TA = -40C TA = 85C 470 570 770 370 670 IF OUTPUT FREQUENCY (MHz) 870 -70 1500 1600 1700 1800 1900 2000 LO FREQUENCY (MHz) 2100 TA = 25C -50 LO-RF -60 dBm SSB NF TA = 25C IIP3 TA = 25C TA = -40C -30 LO-IF TA = 85C -10 -20
(1230MHz Cable Infrastructure Downmixer Application) VCC = 5VDC, EN = High, TA = 25C, RF input = 1230MHz at -10dBm, LO input swept from = 1500MHz to 2100MHz, PLO = -10dBm, IF output measured from 270MHz to 870MHz, unless otherwise noted. (Test circuit shown in Figure 3.) IF Output Power and 2RF-LO Spur vs RF Input Power
10 0 -10 -20 -30 TA = -40C POUT TA = 25C TA = -40C 2RF-LO TA = 85C TA = 85C
dBm
Conv Gain, IIP3 and SSB NF vs LO Input Power
20 TA = 85C IIP3 16 14 12 10 8 6 4 2 -20 -15 -5 -10 LO INPUT POWER (dBm) 0
5512 G15
CONV GAIN (dB), IIP3 (dBm), NF (dB)
TA = 25C TA = -40C
CONV GAIN (dB), IIP3 (dBm), NF (dB)
18
14 12 10 8 6 4 2 CONV GAIN
RETURN LOSS (dB)
SSB NF TA = 25C
fLO = 1800MHz fIF = 570MHz
CONV GAIN TA = 25C TA = -40C TA = 85C
UW
5512 G12
LO Leakage vs LO Frequency
-40
-40 -50 -60 -70 -80 -90 -21 -18
TA = 25C
fLO = 1800MHz fIF = 570MHz -3 0
-15 -12 -9 -6 RF INPUT POWER (dBm)
5512 G13
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Conv Gain and IIP3 vs Temperature
20 18 IIP3 16 5VDC fLO = 1800MHz fIF = 570MHz -10 -15 -20 -25 4.5, 5.0 AND 5.5VDC -50 -35 -20 -5 10 25 40 55 TEMPERATURE (C) 70 85 -30 5.5VDC 4.5VDC -5 0
RF, LO and IF Port Return Losses vs Frequency
IF
RF
LO
0
500
1000 1500 2000 FREQUENCY (MHz)
2500
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LT5512
PI FU CTIO S
NC (Pins 1, 4, 8, 13, 16): Not connected internally. These pins should be grounded on the circuit board for improved LO to RF and LO to IF isolation. RF +, RF - (Pins 2, 3): Differential Inputs for the RF Signal. These pins must be driven with a differential signal. Each pin must be connected to a DC ground capable of sinking 15mA (30mA total). This DC bias return can be accomplished through the center-tap of a balun, or with shunt inductors. An impedance transformation is required to match the RF input to 50 (or 75). EN (Pin 5): Enable Pin. When the input voltage is higher than 3V, the mixer circuits supplied through Pins 6, 7, 10, and 11 are enabled. When the input voltage is less than 0.3V, all circuits are disabled. Typical enable pin input current is 50A for EN = 5V and 0A when EN = 0V. VCC1 (Pin 6): Power Supply Pin for the LO Buffer Circuits. Typical current consumption is 22mA. This pin should be externally connected to the other VCC pins, and decoupled with 100pF and 0.01F capacitors. VCC2 (Pin 7): Power Supply Pin for the Bias Circuits. Typical current consumption is 4mA. This pin should be externally connected to the other VCC pins, and decoupled with 100pF and 0.01F capacitors. GND (Pins 9 and 12): Ground. These pins are internally connected to the backside ground for better isolation. They should be connected to RF ground on the circuit board, although they are not intended to replace the primary grounding through the backside contact of the package. IF -, IF + (Pins 10, 11): Differential Outputs for the IF Signal. An impedance transformation may be required to match the outputs. These pins must be connected to VCC through impedance matching inductors, RF chokes or a transformer center-tap. LO -, LO + (Pins 14, 15): Differential Inputs for the Local Oscillator Signal. They can also be driven single-ended by connecting one to an RF ground through a DC blocking capacitor. These pins are internally biased to 2V; thus, DC blocking capacitors are required. An impedance transformation is required to match the LO input to 50 (or 75). GROUND (Backside Contact): Circuit Ground Return for the Entire IC. This must be soldered to the printed circuit board ground plane.
BLOCK DIAGRA
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BACKSIDE GROUND 17 LINEAR AMPLIFIER DOUBLE-BALANCED MIXER 15mA 15mA
12 GND 11 IF
+
RF
+
2
RF - 3
+
10 IF - 9 GND
LO
15
HIGH-SPEED LO BUFFER
LO- 14
BIAS 5 EN 6 VCC1 7 VCC2
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LT5512
TEST CIRCUITS
LOIN 1500MHz TO 2300MHz C6 C7 0.018" L3 16 RFIN 1700MHz TO 2100MHz 1 4 TL1 2 C4 5 3 TL2 4 3 NC NC RF
+
ER = 4.4
RF GND DC
0.062" 14 LO- 13 NC GND IF 12 L1 C8 C5 9 L2 1 2 3 4 0.018" GND
15 LO
+
T1 1
T2 6
+ 11
IFOUT 170MHz
LT5512 RF - NC EN 5 6 7
IF - GND
10
VCC1 VCC2 NC 8 R1 VCC C1 C2 C3 GND
5512 F02
EN
REF DES C1, C5, C6, C7 C2 C3 C4 C8
VALUE 100pF 0.01F 1.0F 1.5pF 6.8pF
SIZE 0402 0402 0603 0402 0402
PART NUMBER Murata GRP1555C1H101J Murata GRP155R71C103K Taiyo Yuden LMK107F105ZA Murata GRP1555C1H1R5C Murata GRP1555C1H6R8D
REF DES L1, L2 L3 R1 T1 T2 TL1, TL2
VALUE 47nH 5.6nH 10 2:1 8:1 ZO = 72
SIZE 0402 0402 0402
PART NUMBER Coilcraft 0402CS-47NX Toko LL1005-FH5N6 Murata LDB211G9010C-001 Mini-Circuits TC8-1
= 8.1
(W = 0.4mm, L = 2mm)
Figure 2. Test Schematic for 1900MHz Downconverter (PCS/UMTS Applications)
LOIN 1500MHz TO 2100MHz
C6
C7
L3 16 1 6 3 1 5 N/C 4 TL2 4 TL1 2 C4 3 NC NC RF
+
15 LO
+
14 LO-
13 NC GND IF 12 L1 C5 T2 1 2 C10 3 L2 4 6 C9 IFOUT 270MHz TO 870MHz
RFIN 1230MHz
T1 2
+ 11
LT5512 RF - NC EN 5 6 7
10 IF - GND 9
VCC1 VCC2 NC 8 R1 VCC C1 C2 C3 GND
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EN
REF DES C1, C5, C6, C7, C9, C10 C2 C3 C4
VALUE 100pF 0.01F 1.0F 2.7pF
SIZE 0402 0402 0603 0402
PART NUMBER Murata GRP1555C1H101J Murata GRP155R71C103K Taiyo Yuden LMK107F105ZA Murata GRP1555C1H2R7C
REF DES L1, L2 L3 R1 T1 T2 TL1, TL2
VALUE 12nH 8.2nH 10 1:1 4:1 ZO = 72
SIZE 0402 0402 0402
PART NUMBER Toko LL1005-FH12N Toko LL1005-FH8N2 Murata LDB311G2705C-428 M/A-COM ETC1.6-4-2-3
= 5.4
(W = 0.4mm, L = 2.0mm)
Figure 3. Test Schematic for 1230MHz Downconverter (Cable Infrastructure Downlink Transmitter Applications)
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APPLICATIO S I FOR ATIO
The LT5512 consists of a double-balanced mixer, RF buffer amplifier, high-speed limiting LO buffer, and bias/ enable circuits. The RF, LO and IF ports are differential. All three ports can be matched from DC to 3GHz, although the IC has been optimized for downconverter applications where the RF and LO input signals are high frequency and the IF output frequency ranges from DC up to 2GHz. Low side or high side LO injection can be used. RF Input Port The RF input buffer has been designed to simplify impedance matching while improving LO-RF isolation and noise figure. A simplified schematic is shown in Figure 4 with the associated external impedance matching elements for a 1.9GHz application. Each RF input requires a low resistance DC return to ground capable of sinking 15mA. This can be accomplished with the center-tap of a balun as shown in Figure 4, or bias chokes connected from Pins 2 and 3 to ground.
VBIAS VCC 15mA 15mA
2 TL1 ZO = 72 = 8.1 AT 1.9GHz C4 1.5pF
3 TL2 ZO = 72 = 8.1 AT 1.9GHz
100 4 1 2 3 5
T1 1:2 RFIN LDB211G9010C-001 50
5512 F04
Figure 4. RF Input with External Matching for a 1.9GHz Application
Table 1 lists the differential input impedance and differential reflection coefficient between Pins 2 and 3 for several common RF frequencies. As shown in Figures 4 and 5, low-pass impedance matching is used to transform the
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differential input impedance up to the desired value for the balun input. The following example shows how to design the low-pass impedance transformation network for the RF input. From Table 1, the differential input impedance at 1900MHz is 20.6 + j22.8. As shown in Figure 5, the 22.8 reactance is split, with one half on each side of the 20.6 load resistor. The matching network will consist of additional inductance in series with the internal inductance and a capacitor in parallel with the desired 100 source impedance. The capacitance (C4) and inductance are calculated as follows. n = RS/RL = 100/20.6 = 4.85 Q = n - 1 = 1.963 XC = RS/Q = 100/1.963 = 50.9 C4 = 1/(Xc) = 1.6pF (use 1.5pF) XL = (RL * Q) = (20.6 * 1.963) = 40.4 XEXT = XL - XINT = 40.4 - 22.8 = 17.6 LEXT = (XEXT/) = 1.47nH The external inductance is split in half (0.74nH), with each half connected between the pin and the shunt capacitor, as shown in Figure 5. The inductance is implemented with short (2mm) high-impedance printed transmission lines, which yield a compact board layout. Finally, the 2:1balun transforms the 100 differential impedance down to a 50 single-ended input for the RF signal.
Table 1. RF Input Differential Impedance
Frequency (MHz) 10 44 240 450 950 1900 2150 2450 2700 Differential Input Impedance 18.2 + j0.14 18.0 + j0.26 18.1 + j2.8 18.1 + j5.2 18.7 + j11.3 20.6 + j22.8 21.4 + j26.5 22.5 + j30.5 24.1 + j34.7 Differential S11 Mag 0.467 0.470 0.471 0.473 0.479 0.503 0.512 0.522 0.530 Angle 179.6 178.6 172.6 166.3 150.8 124.3 116.9 109.2 101.7
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LT5512
APPLICATIO S I FOR ATIO
1/2 XEXT 2 RS 100 C4 1/2 XEXT 3 1/2 XINT j11.4 1/2 XINT j11.4
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RL 20.6
Figure 5. 1.9GHz RF Input Matching
It is also possible to eliminate the RF balun and drive the RF inputs differentially. In this case, inductors from Pins 2 and 3 to ground would be required to bias the input stage. The value of the inductors should be high enough to avoid reducing the input impedance at the frequency of interest. LO Input Port The LO buffer amplifier consists of high-speed limiting differential amplifiers, designed to drive the mixer quad for high linearity. The LO+ and LO- pins are designed for differential or single-ended drive. An external balun is optional. Both LO pins are internally biased to 2VDC. The LO input has been designed for simple impedance matching for frequencies up to 3GHz. A simplified schematic is shown in Figure 6 with the associated external impedance matching. The matching technique is similar to that described earlier for the RF port, except the match is not nearly as critical. Table 2 lists the differential input impedance and differential reflection coefficient between the LO+ and LO- pins (Pin 15 to Pin 14). As shown, the real part of the series impedance is close to 100. Series inductors (L3, L4) are used to tune out the capacitive portion of the differential impedance.
T3 1:2 LDB211G9010C-001 LOIN 50 1 4 L3 C11 2 VCC
LO + 15
2V
5
3
L4
14 LO -
5512 F06
Figure 6. LO Input with External Matching Elements
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Table 2. LO Input Differential Impedance
Frequency (MHz) 750 1000 1250 1500 1750 2000 2250 2500 2750 Differential Input Impedance 263 - j172 213 - j178 175 - j173 146 - j164 125 - j153 108 - j142 95 - j131 86 - j122 78 - j113 Differential S11 Mag 0.766 0.760 0.752 0.743 0.733 0.722 0.709 0.695 0.68 Angle -10.2 -13.4 -16.6 -19.8 -22.8 -25.8 -28.9 -31.8 -34.6
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Single-ended LO drive can be used if a differential LO source is not available, or the added expense of a LO balun is undesirable. In this case, one LO input is AC-coupled to ground through a 100pf DC blocking capacitor as shown in Figure 7. The other input is matched to 50 using a series inductor and a second DC blocking capacitor. The LT5512 is characterized and production tested with singleended LO drive.
L3 C6 100pF C7 100pF 14 LO -
5512 F07
LOIN 50
LO + 15
2V
VCC
Figure 7. Single-Ended LO Input Matching
The differential port impedance listed in Table 2 can be used to compute the value of the series matching inductor, L3. Alternatively, Figure 8 shows measured LO input return loss for various values of L3.
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LT5512
APPLICATIO S I FOR ATIO
0 -5 RETURN LOSS (dB) -10 -15 -20 -25 -30 8.2nH 10nH 0 4.7nH 5.6nH 6.8nH
500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (MHz)
1573 F08
Figure 8. Single-Ended LO Port Return Loss vs Frequency for Various Values of L3
IF Output Port The IF outputs, IF + and IF -, are internally connected to the collectors of the mixer switching transistors as shown in Figure 9. These differential outputs should be combined externally through an RF balun or 180 hybrid to achieve optimum performance. Both pins must be biased at the supply voltage, which can be applied through matching inductors (see Figure 2), or through the center-tap of an output transformer (see Figure 3). These pins are protected with ESD diodes; the diodes allow peak AC signal swing up to 1.3V above VCC. As shown in Table 3, the IF output differential impedance is approximately 390 in parallel with 0.44pF. A simple band-pass IF matching network suitable for wireless applications is shown in Figure 9. Here, L1, L2 and C8 set the desired IF output frequency. The 390 differential output can then be applied directly to a differential filter, or an 8:1 balun for impedance transformation down to 50. To achieve maximum linearity, C8 should be located as close as possible to the IF+/IF- pins. Even small amounts of inductance in series with C8 (such as through a via) can significantly degrade IIP3. For high IF frequencies, the value of C8 should be reduced by the value of internal capacitance (see Table 3).This matching network is simple and offers good selectivity for narrow band IF applications.
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An alternative matching network for a broadband CATV IF (270MHz to 870MHz) is shown in Figure 3. Here, a lowpass impedance transformer consisting of the internal capacitance, with L1 and L2, transforms the 371 output resistance at 870MHz to 200. A 4:1 balun then completes the match down to 50. Supply voltage is applied through the center-tap of the transformer.
Table 3. IF Output Differential Impedance (Parallel Equivalent)
Frequency (MHz) 10 70 170 240 450 750 860 1000 1250 1500 1900 Differential Output Impedance 396 || - j10k 394 || - j5445 393 || - j2112 392 || - j1507 387 || - j798 377 || - j478 371 || - j416 363 || - j359 363 || - j295 346 || - j244 317 || - j192 Differential S11 Mag 0.766 0.775 0.774 0.773 0.772 0.768 0.766 0.762 0.764 0.756 0.743 Angle 0 -1.1 -2.8 -3.9 -7.3 -12.2 -14.0 -16.2 -19.6 -23.6 -29.9
11 IF+ L1 400 C8 L2 10 IF- TO VCC DIFFERENTIAL FILTER OR BALUN
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Figure 9. IF Output Equivalent Circuit with Band-Pass Matching Elements
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LT5512
PACKAGE DESCRIPTIO
4.35 0.05 2.15 0.05 2.90 0.05 (4 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW--EXPOSED PAD 4.00 0.10 (4 SIDES) 0.75 0.05 R = 0.115 TYP 0.55 0.20 15 16
PIN 1 1 2.15 0.10 (4-SIDES) 2
NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC) 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 4. EXPOSED PAD SHALL BE SOLDER PLATED
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UF16 Package 16-Lead Plastic QFN (4mm x 4mm)
(Reference LTC DWG # 05-08-1692)
0.72 0.05 PACKAGE OUTLINE 0.30 0.05 0.65 BCS
(UF) QFN 0102
0.200 REF 0.00 - 0.05
0.30 0.05 0.65 BSC
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LT5512
APPLICATIO S I FOR ATIO
5512 F10a
Figure 10. 1900MHz Evaluation Board Layout
5512 F11
Figure 11. 1230MHz Cable Infrastructure Evaluation Board Layout (Wide Output Range Down-Converting Mixer for Downlink Transmitter)
RELATED PARTS
PART NUMBER LT5500 LT5502 LT5503 LT5504 LTC5505 LTC5507 LT5511 DESCRIPTION 1.8GHz to 2.7GHz Receiver-Front End 400MHz Quadrature IF Demodulator with RSSI 1.2GHz to 2.7GHz Direct IQ Modulator and Upconverting Mixer 800MHz to 2.7GHz RF Measuring Receiver RF Power Detectors with >40dB Dynamic Range 100kHz to 1000MHz RF Power Detector High Signal Level Upconverting Mixer COMMENTS 1.8V to 5.25V Supply, Dual-Gain LNA, Mixer, LO Buffer 1.8V to 5.25V Supply, 70MHz to 400MHz IF, 84dB Limiting Gain, 90db RSSI Range 1.8V to 5.25V Supply, Four-Step RF Power Control, 120MHz Modulation Bandwidth 80dB Dynamic Range, Temperature Compensated, 2.7V to 5.5V Supply 300MHz to 3GHz, Temperature Compensated, 2.7V to 6V Supply Temperature Compensated, 2.7V to 6V Supply RF Output to 3GHz, 17dBm IIP3, Integrated LO Buffer
5512i
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
www.linear.com
U
5512 F10b
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UU
LT/TP 0702 1.5K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2002

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