: Data byte write to or read from the register index. In read operation, the host must release the SDA line (high) before the first clock pulse is transmitted to the AL100/110/128. : Stop signal SCL SDA High Low High High The Stop signal is LOW to HIGH transition on the SDA line when SCL is HIGH.
Suppose data F0h is to be written to register 0Fh using write slave address 88h, the timing is as follows (same as the Philips standard):
Start Slave addr = 88h Ack Index = 0Fh Ack Data = F0h Ack Stop
SDA SCL
AL128-24 I2C Write timing
Suppose data is to be read from register 55h using read slave address 89h, the timing is as follows:
NAck Data read cycle Stop
Slave addr = 89h Ack
SDA SCL
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AL128
In comparison, reading data from register 55h using slave address 59h with Philips standard would be as follows:
Start
Ack
Index = 55h
Ack
Stop Read slave addr = 59h
NAck Data read cycle
SDA SCL
AL250-25 I2C Read timing
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AL128
7.0 Electrical Characteristics
Parameter VDD TAMB Ambient Operating Temperature
Min +3.8 +5.5 +70
Unit
Parameter IDD P VIH VIL VOH VOL ILI Ci tSU tHD CL tOH tPD tr tf Supply current Power consumption Hi-level input voltage Lo-level input voltage Hi-level output voltage Lo-level output voltage Input leakage current Input pin capacitance Input data set-up time Input data hold time Digital output load cap. Output hold time Propagation delay Output rise time Output fall time
Test Conditions 230 875 0.7VDD -0.5 2.4 10 3 15 CL = 15pF CL = 40pF Vi = 0.6 to 2.6V Vi = 2.6 to 0.6V 5 3 3
Max 350 1925 VDD+0.5 +0.8 VDD 0.5 1 8 50 15 7 7
Unit mA mW V V V V A PF ns ns PF ns ns ns ns
26
AL128
8.0 AL128 Register Definition
8.1 Index of the Control Registers
Register Configuration COMPANYID REVISION BOARDCONFIG GENERAL VERSION Push Button Interface SOFTBUTTON BUTTONSTATUS Graphic Input GRAPHCTRL GINHSTARTDLT GINVSTARTDLT GINCAPHSIZE GINYSIZE CAPVSIZE CAPVRATIO DSPHRATIO PLLDIVIDER GINHSTZOOMDLT GINVSTZOOMDLT GRAPHDP 20h 21h 22h 23h 24h 25h 26h 27h 28h 2Bh 2Ch 33h 40h Read Only Status Registers HWCONFIG GINHTOTAL 41h 42h Hardware configuration status Detected horizontal total Graphic control Delta of horizontal start Delta of vertical start Horizontal capture size Source picture vertical size Destination picture vertical size Vertical scale ratio Horizontal scale ratio PLL clock divider Delta of horizontal start in zoom mode Delta of vertical start in zoom mode Graphic data processing control Reserved (for assisting memory control) 18h 19h Software button I Software button II 00h 01h 02h 03h 04h Company ID number Revision number Board configuration General control Chip family number Index Function
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AL128
GINVTOTAL SCANRATE TVSTATUS Encoder ENCODERCTRL TVVSTARTDLT TVHSTARTDLT CAPINV Miscellaneous MCAPVRATIO NCAPVRATIO CHROMABYPASS
43h 44h 45h
Detected vertical total Detected scan rate Vertical position status
50h 51h 52h 53h
Encoder control Delta of vertical display start Delta of horizontal display start Capture control
71h 72h 73h
M of vertical capture ratio value: N/M N of vertical capture ratio value: N/M Chroma filter bypass control
8.2 Control Register Description
00h: Company ID (R) [COMPANYID] CompanyId <7:0> Company ID (0x46) Revision (R) [REVISION] Revision <7:0> 00000001, Revision ID numbers Board Configuration (R/W) [BOARDCONFIG] InType <1:0> Graphic input data format 00 Digital RGB 888 01 Reserved 10 Feature connector 11 VAFC MemConf <3:2> External memory configuration 00 No external memory used 01 One-field memory capture Only one field of video data is stored in the field memory. This proprietary design increases the resolution with limited 512kB memory (thus bringing better output quality), but does not work when the input refresh rate is
01h:
02h:
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AL128
less than 66Hz for NTSC or 55Hz for PAL, or when freeze control is used. 10 Two-field memory capture Both odd and even fields of video data are stored in the field memory. When the AL422 is used as the field memory, there is enough capacity at all times so this mode is suggested for programming simplicity. 11 Reserved MemType <4> Memory Type 0 Oki field memory 1 NEC field memory Pal <5> PAL/NTSC select 0 NTSC 1 PAL F4sc <6> 0 Use 8 times SC sampling clock as TV clock 1 Use 4 times SC sampling clock as TV clock RgbOut <7> 0 Composite and S-video output 1 RGB output Settings of this register are enabled only when software programming is turned on by writing 18h to Reg.#03h. 03h: General (R/W) [GENERAL] PwrDown <0> Power down the chip if set to 1. <2:1> Reserved DisButton <3> Disable touch button function; use I2C/Vsync interface to program the chip. This bit has to be turned on to enable all the functions marked as ** xxx **. SoftConfig <4> Enable configuration defined by software configuration registers 0x02. Reserved <7:5> To use software programming properly, read the value of Reg.#41h (hardware configuration) and write it to Reg.#02h. Then write value 18h to Reg.#03h. Chip Family (R) [VERSION] Family <7:0> 00000000, AL100 series
04h:
Push-Button Interface 18h: Push Button Value (R/W): [SOFTBUTTON]
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ValuePtr
<0> <1> <3:2> <7:4>
Reserved Reserved Reserved Number of on-screen-display white rectangle bar, to indicate the level of strength. Works only when Reg.#19h <1> is turned on.
19h:
Push Button Status (R/W): [BUTTONSTATUS] DspMenu <0> Enable display of on-screen-display menu icons DspValue <1> Enable display of on-screen-display function icons DspLeftR <2> Enable display of on-screen-display left-right icon DspUpDn <3> Enable display of on-screen-display up-down icon FuncPtr <6:4> Current function icon selected and highlighted. 000: sharpness function icon 001: zoom function icon 010: pan function icon 011: underscan/overscan function icon 100: position function icon 101: brightness function icon 110: color bar function icon 111: home function icon <7> Reserved
Graphic Input Block 20h: Graphics Control Register (R/W) [GRAPHCTRL] Zoom <1:0> zoomed quadrant ** zoom ** 00 Zoom quadrant 0 01 Zoom quadrant 1 10 Zoom quadrant 2 11 Zoom quadrant 3 Meaningful only when ZoomEn = 1. It is recommended not to set these bits when S/W mode is enabled. Instead, use reg#2Bh and reg#2Ch to control the zoomed video visible area. VGA VAFC/feature connector 555/565 format select 0: 565 format 1: 555 format
Vga555
<2>
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AL128
ZoomEn
<3> <4> <5> <6> <7>
Reserved Reserved Reserved Reserved Zoom enable ** zoom ** Set to 0 when in basic mode.
21h:
Delta of Horizontal Start (R/W) [GINHSTARTDLT] GinHStartDlt <7:0> Delta of default horizontal capture start position. (unit: 8 pixels) ** X Pan ** This register does not apply to zoom mode. The actual horizontal capture start position is defined as: (default horizontal capture start position) + (GinHStartDlt * 8). The value of GinHStartDlt is signed, and its value is between -128 and 127. Please refer to Section 8.3, AL128 Plug & Play Hardware Table for the default horizontal capture start positions. Delta of Vertical Start (R/W) [GINVSTARTDLT] GinVStartDlt <7:0> Bit-9 to bit-2 of GinVStartDlt; bit 1,0 are defined in Register 0x26. (Unit: one line) ** Y Pan ** This register does not apply to zoom mode. The actual vertical capture start position is defined as: (default vertical capture start position) + (GinVStartDlt * 4). The value of GinVStartDlt is signed, and its value is between -128 and 127. Please refer Section 8.3, AL128 Plug & Play Hardware Table for the default vertical capture start positions. Horizontal Capture Size (R/W) [GINCAPHSIZE] GinCapHSize <6:0> Horizontal capture size (Unit: 16 pixels) SoftCapHSize <7> Override default H capture size value and use GinCapHSize if set to 1. This register defines the number of pixels of each valid horizontal line, which length is defined by reg#22h (zoom off) or reg#2Ch (zoom on). Only the active horizontal lines are captured, and the range is defined by reg#24h and reg#25h. The actual horizontal capture size is defined as: GinCapHSize * 16. The starting capture position is defined by reg#21h (zoom off) or reg#2Bh (zoom on). The destination total displayed active pixels is defined as: GinCapHSize * 16 * (scale-up ratio defined in reg#27h) Please also refer to Section 6.3 Video Timing for better understanding.
22h:
23h:
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AL128
Make sure that: (GinCapHSize * 16) <= 800(AL100/128 built-in line buffer size) (GinCapHSize * 16) <= (reg#28h<6:0> * 16) For one-field memory configuration, the value of (GinCapHSize * 16) * (reg#25h<6:0> * 8) * 2 must be less or equal to the total field memory size on board. For two-field memory configuration, the value of (GinCapHSize * 16) * (reg#25h<6:0> * 8) * 2 * 2 must be less or equal to the total field memory size on board. 24h: Source Vertical Size (R/W) [GINVSIZE] GinVSize <6:0> Vertical size of graphic input (unit: 8 lines) SoftVSize <7> Override hardware detected V size value and use GinVSize if set to 1. This register defines the total number of input lines scanned, which starting position is defined by reg#22h (zoom off) or reg#2Bh (zoom on). The scanned input lines are scaled (down-sampled), filtered and captured into field memory. The destination down-sampled size is defined in reg#25h. The actual vertical source size is defined as: GinVSize * 8. The starting position to scan input lines is defined by reg#22h (zoom off) or reg#2Bh (zoom on). See reg#26h for more description. Please also refer to Section 6.3 Video Timing for better understanding Down-sampled Vertical Size (destination) [CAPVSIZE] (R/W) CapVSize <6:0> (unit: 8 lines) CapVSizeEn <7> enable software vertical size This register defines the total number of scaled (down-sampled) and filtered video lines captured into the field memory. The actual number is defined as: CapVSize * 8. For one-field memory configuration, the value of (reg#23h<6:0> * 16) * (CapVSize * 8) * 2 must be less or equal to the total field memory size on board. For two-field memory configuration, the value of (reg#23h<6:0> * 16) * (CapVSize * 8) * 2 * 2 must be less or equal to the total field memory size on board. See reg. #26h for more description Please also refer to Section 6.3 Video Timing for better understanding Y Downscale Ratio [CAPVRATIO] (R/W) CapVRatio <3:0> 0000 No line drop 0001 Drop 3 lines out of 10 lines xxxx (from 0010 to 1110): drop one line for every xxxx+1 lines 1111 vertical scale ratio defined as N/M
25h:
26h:
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AL128
CapVRatioEn
<4>
GinVStartDlt
<5> <7:6>
N is defined at reg.#72h<5:0> M is defined at reg.#71h<5:0> 0: Hardware default vertical scale ratio used for vertical scaling. 1: Software vertical down-scale ratio CapVRatio used. Reserved bit 1,0 of 10-bit GinVStartDlt. Used with Reg 0x22
The relationship between registers #24h, #25h and #26h is that Reg. #25h<6:0> approximately equals to Reg. #24h<6:0> * (Vertical scale ratio define in Reg. #26h) Please also refer to Section 6.3 Video Timing for better understanding 27h: Horizontal Scale Ratio [DSPHRATIO] (R/W) DspHRatio <5:0> Software horizontal scale ratio. The value is ((HSRC/HDST) x 256 - 128) / 2 HSRC is horizontal capture size defined in reg. #23h HDST is horizontal display active size. The default overscan HDST for NTSC is 752; PAL is 954 The default underscan HDST for NTSC is 656; PAL is 800 The pixel total for 910x525 for NTSC, 1126x615 for PAL The suggested HDST in zoom mode is 736~836 (NTSC) and 800~1203 (PAL). Please review the S.5.2 and S.5.3 sections of the AL128 Application Notes (and find the DspH value in different input modes) for details HscaleEn <6> 0: Use default hardware horizontal scale ratio. 1: Use DspHRatio and SoftNoScale to control horizontal scale ratio. SoftNoScale <7> turned on when horizontal scaling ratio is 1:1. Don't care if bit<6> = 0. The AL100 series perform horizontal up-scaling only. For down-scaling, reduce capture size instead by programming Reg.#28h. The destination total displayed active pixels is defined as: Reg#23h<6:0> * 16 * (HDST/HSRC) Please also refer to Section 6.3 Video Timing for better understanding. Graphic Clock PLL Divider (R/W) [PLLDIVIDER] PllDiv <6:0> PLL divider number (Unit: 16 pixels) PllDivEn <7> PLL divide number enable 0 Use default hardware divider value. 1 Use PllDiv registers for the PLL divider number.
28h:
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AL128
This register defines the horizontal total sampled pixels between 2 continuous input horizontal sync. The actual number is defined as: PllDiv * 16 Make sure that the value of (Graphic Clock PLL divider) * (Detected Vertical Total) * (Detected Scan Rate) does not exceed the maximum speed of the field memory used, e.g., PllDiv * 16 * GinVTotal * 4 * VGArr <= 56MHz for AL422 PllDiv, GinVTotal and VGArr are defined by registers 28h, 43h and 44h respectively. 2Bh: Delta of Horizontal Start in Zoom Mode (R/W) [GINHSTZOOMDLT] GinHStZoomDlt <6:0> (unit: 8 pixels) ** X Pan (in zoom mode) ** <7> Reserved This does not apply to non-zoom mode. The actual horizontal capture start position is defined as: (default horizontal capture start position) + (GinHStZoomDlt * 8). The value of GinHStZoomDlt is signed, and its range is between -64 and 63. Please refer to Section 8.3, AL128 Plug & Play Hardware Table for the default horizontal capture start positions. Delta of Vertical Start in Zoom Mode (R/W) [GINVSTZOOMDLT] GinVStZoomDlt <6:0> (unit: 4 lines) ** Y Pan (in zoom mode) ** <7> Reserved This does not apply to non-zoom mode. The actual vertical capture start position is defined as: (default vertical capture start position) + (GinVStZoomDlt * 4). The value of GinVStZoomDlt is signed, and its range is between -64 and 63. Please refer to Section 8.3, AL128 Plug & Play Hardware Table for the default vertical capture start positions. Graphic Data Processing (R/W) [GRAPHDP] VFltMode <2:0> Vertical Flicker filter mode select ** Filter modes ** UdScanX <3> H direction only underscan This only reply to H/W default mode. For S/W mode, please use reg#28h and reg#23h to control the horizontal sampling and set this bit to 0 <4> Reserved <5> Reserved SoftUdScan <6> 1: Underscan; 0: Overscan. To disable the hardware default settings of the underscan mode, program this bit as 0. For S/W control, use reg#28h and reg#23h to control the horizontal sampling and set this bit to 0 <7> Reserved
2Ch:
33h:
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AL128
40h:
Reserved (R/W) Reserved for assisting memory control, works only when MemConf is set as two-field memory capture. To be turned on only when there is memory I/O timing conflict. Suggested value is 81h for 1024x768 input / overcan PAL output, and 00h for other modes.
Status Read Only Registers 41h: Hardware Configuration (R only) [HWCONFIG] InType <1:0> Graphic input data format 00 Digital RGB 888 01 Reserved 10 Feature connector 11 VAFC MemConf <3:2> External memory configuration 00 No external memory used 01 One-field memory capture See reg#02h for more information 10 Two-field memory capture See reg#02h for more information 11 Reserved MemType <4> Memory Type 0 Oki field memory 1 AverLogic AL422, NEC or Panasonic field memory Pal <5> PAL/NTSC select 0 NTSC 1 PAL F4sc <6> 0 Use 8 times SC sampling clock as TV clock 1 Use 4 times SC sampling clock as TV clock RgbOut <7> 0 Composite and S-video output 1 RGB output Detected Horizontal Total (R only) [GINHTOTAL] GinHTotal <7:0> Detected horizontal total (Unit: 8 pixels) For input resolution of 640x480 or 800x600, the value of (GinHTotal * 8) equals to (reg#28h<6:0> * 16). For higher input resolution, PllDiv needs to be lower than the Detected Horizontal Total so as not to exceed the speed limit of the field memory.
42h:
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AL128
43h:
Detected Vertical Total (R only) [GINVTOTAL] GinVTotal <7:0> Detected vertical total (Unit: 4 lines) This value can also be used to determine the input resolution:
Detected vertical total <480 481~600 601~768 >769 Estimated Input Resolution 720 x 400 (DOS mode) 640 x 480 (VGA) 800 x 600 (SVGA) 1024 x 768 (XGA)
44h:
Detected Scan Rate (R only) [SCANRATE] ScanPeriod <6:0> Total number of TV lines counted during an input VGA frame period, in unit of 4 lines. GinVsync <7> 1 if graphic vsync is active To determine the VGA refresh rate (VGArr): For NTSC: VGArr = (525 / (Reg.#44h<6:0>)) * 59.94 / 8 For PAL: VGArr = (625 / (Reg.#44h<6:0>)) * 50 / 8
45h:
Vertical Postion Status (R only) [TVSTATUS] GinData <2:0> Green0, blue1, blue0 pins, reserved as input ports when these hardware pins are not used for digital input. I2cP <3> I2C pin I2cP <4> I2C address select pin TvBlank <5> TV blanking signal TvField <6> Odd/even field 0 Even field 1 Odd field TvVsync <7> 1 if TV Vsync is active
Encoder Output Block 50h: Encoder Control: (R/W) [ENCODERCTRL] Reserved <0> ColorBar <1> Color bar enable ** Color bar ** BW <2> Make TV output Black and white TvBright <4:3> TV brightness control ** Brightness ** Filter2 <5> Turned on only for TV without comb filter
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AL128
<7:6> 51h:
Reserved
Delta of Vertical Display Start Line (R/W) [TVVSTARTDLT] TvVStartDlt <7:0> Delta of vertical start line No. (unit: 4 lines) ** Y position ** The actual vertical display start position is defined as: (default vertical display start position) + (TvVStartDlt * 4). The value of TvVStartDlt is signed, and its range is between -128 and 127. Please refer to Section 8.3, AL128 Plug & Play Hardware Table for the default vertical display start positions. Delta of Horizontal Display Start Position (R/W) [TVHSTARTDLT] TvHStartDlt <7:0> Delta of horizontal display start pixel No. (unit: 8 pixels) ** X position ** The actual horizontal display start position is defined as: (default horizontal displaye start position) + (TvHStartDlt * 8). The value of TvHStartDlt is signed, and its value is between -128 and 127. Please refer to Section 8.3, AL128 Plug & Play Hardware Table for the default horizontal display start positions. Overrun Test Register (R/W) [CAPINV] Freeze <0> Freeze the picture, use only two-field memory configuration mode. <7:1> Reserved
52h:
53h:
Miscellaneous Control Block 70h: Reserved (R/W) When <7:5> = 101, pin TEST6 (the internal LUMA<3>) works as hde signal (horizontal data enable input), pin TEST7 (the internal LUMA<2>) works as vde signal (vertical data enable output). 71h: Vertical Capture Ratio M Control: (R/W) [MCAPVRATIO] M <5:0> Vertical Capture Ratio M Control: (R/W) [MCAPVRATIO] N <5:0>
72h:
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AL128
73h:
Chroma Filter Bypass Control: (R/W) [CHROMABYPASS] NoCFilt <3> Chroma filter bypass control; enhance S-video color resolution only when composite output is not used. 0 disabled 1 enabled UvFlip <2> Flip UV
8.3 AL128 Plug & Play Hardware Table
NTSC 640x400 (DOS) Underscan CapH: 648 CapV: 404->404 CapHST: 136 CapVST: 28 DspH: 648->648 DspV: 404 DspHST: 176 DspVST: 74 Hpll: 800 CapH: 656 CapV: 480->420 CapHST: 160 CapVST: 20 DspH: 656->656 DspV: 420 DspHST: 152 DspVST: 68 Hpll: 832 CapH: 512 CapV: 480->420 CapHST: 120 CapVST: 20 DspH: 512->656 DspV: 420 DspHST: 152 DspVST: 68 Hpll: 640 Overscan Same as NTSC underscan defined left PAL Underscan CapH: 648 CapV: 404->404 CapHST: 136 CapVST: 28 DspH: 648->648 DspV: 404 DspHST: 288 DspVST: 136 Hpll: 800 CapH: 656 CapV: 480->480 CapHST: 160 CapVST: 20 DspH: 656->656 DspV: 480 DspHST: 288 DspVST: 96 Hpll: 832 CapH: 512 CapV: 480->480 CapHST: 120 CapVST: 20 DspH: 512->656 DspV: 480 DspHST: 288 DspVST: 96 Hpll: 640 Overscan Same as PAL underscan defined left
640x480 reg.#02h<3> = 0 or VGA refresh rate: NTSC: >= 66 Hz PAL: >= 56 Hz
640x480 reg.#02h<3> = 1 or VGA refresh rate: NTSC: < 66 Hz PAL: < 56 Hz
CapH: 656 CapV: 480->480 CapHST: 160 CapVST: 20 DspH: 656->752 DspV: 480 DspHST: 136 DspVST: 32 Hpll: 832 CapH: 512 CapV: 480->480 CapHST: 120 CapVST: 20 DspH: 512->752 DspV: 480 DspHST: 136 DspVST: 32 Hpll: 640
Same as PAL underscan defined left
Same as PAL underscan defined left
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AL128
800x600 reg.#02h<3> = 0 or VGA refresh rate: NTSC: >= 66 Hz PAL: >= 56 Hz
800x600 reg.#02h<3> = 1 or VGA refresh rate: NTSC: < 66 Hz PAL: < 56 Hz
CapH: 656 CapV: 600->420 CapHST: 160 CapVST: 28 DspH: 656->656 DspV: 420 DspHST: 152 DspVST: 68 Hpll: 832 CapH: 512 CapV: 600->420 CapHST: 120 CapVST: 28 DspH: 512->656 DspV: 420 DspHST: 152 DspVST: 68 Hpll: 640
CapH: 656 CapV: 600->480 CapHST: 160 CapVST: 28 DspH: 656->752 DspV: 480 DspHST: 136 DspVST: 32 Hpll: 832 CapH: 512 CapV: 600->480 CapHST: 120 CapVST: 28 DspH: 512->752 DspV: 480 DspHST: 136 DspVST: 32 Hpll: 640
CapH: 800 CapV: 600->500 CapHST: 200 CapVST: 28 DspH: 800->800 DspV: 500 DspHST: 224 DspVST: 84 Hpll: 1024 CapH: 656 CapV: 600->500 CapHST: 160 CapVST: 28 DspH: 656->800 DspV: 500 DspHST: 224 DspVST: 84 Hpll: 832
CapH: 800 CapV: 576->576 CapHST: 200 CapVST: 28 DspH: 800->928 DspV: 576 DspHST: 152 DspVST: 24 Hpll: 1024 CapH: 656 CapV: 576->576 CapHST: 160 CapVST: 28 DspH: 656->928 DspV: 576 DspHST: 152 DspVST: 24 Hpll: 832
Remarks: CapH: Horizontal Capture Width CapHST: Horizontal Capture Start DspH: Horizontal Display Width DspHST: Horizontal Display Start Hpll: Horizontal Total ->: scaled to
CapV: Vertical Capture Height CapVST: Vertical Capture Start DspV: Vertical Display Height DspVST: Vertical Display Start
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AL128
9.0 Board Design and Layout Considerations
The AL128 is a highly integrated mixed-signal IC. It contains both precision analog and high speed digital circuitry. Special care needs to be taken in order to maintain the best video quality. Noise coupling from digital circuits to analog circuits may result in poor video quality. Therefore, the layout should be optimized for lowest noise on the power and ground planes by shielding the digital circuitry and providing good decoupling. It is recommended to place the AL128 chip close to the graphic and video input/output connectors.
9.1 Grounding
Analog and digital circuits are separated within the AL128 chip. To minimize system noise and prevent digital system noise from entering the analog portion, a common ground plane for all devices, including the AL128, is recommended. All the connections to the ground plane should have very short lead. The ground plane should be solid, not cross-hatched.
9.2 Power Planes
The analog portion of the AL128 and any associated analog circuitry should have their own power plane, referred to as the analog power plane (AVDD). The analog power plane should be connected to the digital power plane (DVDD) at a single point through a low resistance ferrite bead. The D/A conversion circuitry within the AL128 uses the DVDD power. The digital power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all of the AL128 analog power pins and relevant analog circuitry. The digital power plane should not be placed under the AL128 chip, the voltage references or other analog circuitry. Capacitive coupling of digital power supply noise from this layer to the AL128 and its related analog circuitry can degrade video output quality.
9.3 Power Supply Decoupling
Power supply connection pins should be individually decoupled. For best results, use 0.1F ceramic chip capacitors. Lead lengths should be minimized. The power pins should be connected to the bypass capacitors before being connected to the power planes. 22F capacitors should also be used between the AL128 power planes and the ground planes to control low-frequency power ripple.
9.4 Digital Signal and Clock Interconnect
Digital signals to the AL128 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these signals should not overlap the analog power plane. If this is not possible, coupling can be minimized by routing the digital signal at a 90 degree angle across the analog signals.
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AL128
The high frequency clock reference or crystal should be handled carefully. Jitter and noise on the clock will degrade the video performance. Keep the clock paths to the AL128 as short as possible to reduce noise pickup. Locate phase locked loop components close to the relevant AL128 pins. Isolate these components from noise.
9.5 Analog Signal Interconnect
The AL128 should be located closely to the output connectors to minimize noise and reflections. Keep the critical analog traces as short and wide as possible. High frequency digital signals, especially pixel clocks and data signals should never overlap any of the analog signal circuitry and should be kept as far away as possible. The AL128 should have no inputs left floating. Each of the unused analog input pins should be connected to GND. All of the digital input pins are internally pulled down. The analog output traces should also not cross the AL128 and VDD power planes to maximize highfrequency power supply rejection.
9.6 Component Placement
The suggested component placement is as follows:
AL422 Analog Power AL128 AL422
RGB input
PLL XTAL TV output
(separated and shielded)
AL128-15
Layout considerations
Remarks: 1. PLL crystal/oscillator circuits should be placed at the lower left corner and close to AL128 to avoid noise interference.
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AL128
2. VGA input and TV output are both analog signals so should be away from high frequency digital signals as much as possible. Use thicker connection such as 20 or 30 mil wires. Output signals should not be too far away from the output connectors and should be shielded properly. Shielding in between the output signals is recommended as well. 3. Analog power should be arranged at the upper left corner of the AL128 only (the output circuits including DAC's share the same power plane with digital power plane so do not need to use analog power). Keep the analog power separated and clean to avoid noise interference.
10.0 Mechanical Drawing
The AL128 is fabricated using CMOS process and packaged in a low profile 24mm x 24mm 160-pin LQFP package. This package type is perfect for PCMCIA or laptop computer applications. Optional 28mm x 28mm PQFP package is also available upon request. The drawing is provided on the following page.
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AL128
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AL128
11.0 Power Consumption
The AL128 works at +5V or +3.3V, but the support of input resolution and refresh rate may be limited at the lower power. For full functionality of the AL128, the power needs to be more than +3.8V. At +3.3V, the AL128 can only support 640x480 resolution up to 85Hz and 800x600 resolution up to 60Hz. The following table shows the current consumption of the AL128 at different supply voltages. +5V Normal Power down 330mA 90mA +3.8V 230mA 35mA +3.3V (800x600 @60Hz) 130mA 10mA
Please be reminded that when lower power supply is used, the pull-down resistance to the RSET pin has to be adjusted to compensate (in both Y/C/Composite mode and RGB mode) accordingly. The lower the supply voltage is, the lower the pull-down resistance has to be. The ideal resistance values can be achieved by adjusting the Y/C/Composite output to be 1V peak-to-peak, or the RGB output to be 0.7V peak-to-peak.
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CONTACT INFORMATION
AverLogic Technologies, Inc. 6840 Via Del Oro Suite 160 San Jose, CA 95119 USA
Tel Fax E-mail URL
: 1 408 361-0400 : 1 408 361-0404 : sales@averlogic.com : http://www.averlogic.com