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Integrated Circuit Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
FEATURES
* 4 LVCMOS/LVTTL outputs, 7 typical output impedance * Selectable CLK0, nCLK0 or CLK1, nCLK1 clock inputs * CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CLK0 and CLK1 inputs * Output frequency range: 15.625MHz to 250MHz * Input frequency range: 15.625MHz to 250MHz * VCO range: 250MHz to 500MHz * External feedback for "zero delay" clock regeneration with configurable frequencies * Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 * Fully integrated PLL * Cycle-to-cycle jitter: 45ps (maximum) * Output skew: 45ps (maximum) * Static phase offset: 50 125ps (3.3V 5%) * Full 3.3V or 2.5V operating supply * 5V tolerant inputs * Lead-Free package available * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS87004 is a highly versatile 1:4 Differentialto-LVCMOS/LVTTL Clock Generator and a memHiPerClockSTM ber of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS87004 has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. Internal bias on the nCLK0 and nCLK1 inputs allows the CLK0 and CLK1 inputs to accept LVCMOS/LVTTL. The ICS87004 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625MHz to 250MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-toinput frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.
ICS
BLOCK DIAGRAM
PLL_SEL
/2, /4, /8, /16, /32, /64, /128
0
PIN ASSIGNMENT
Q0
GND Q0 VDDo SEL0 SEL1 SEL2 SEL3 CLK_SEL VDD CLK0 nCLK0 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q1 VDDO Q2 GND Q3 VDDO MR FB_IN PLL_SEL CLK1 nCLK1 VDDA
CLK0 nCLK0 CLK1 nCLK1 CLK_SEL FB_IN
0
Q1
1
1
PLL
Q2
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Q3
24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm G Package Top View
SEL0 SEL1 SEL2 SEL3 MR
87004AG
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1
REV. A JUNE 16, 2004
Integrated Circuit Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Type Power Output Power Input Input Power Input Description
TABLE 1. PIN DESCRIPTIONS
Number 1, 12, 21 2, 20, 22, 24 3, 19, 23 4, 5, 6, 7 8 9 10 Name GND Q0, Q3, Q2, Q1 VDDO SEL0, SEL1, SEL2, SEL3 CLK_SEL VDD CLK0 Power supply ground. Clock outputs. 7 typical output impedance. LVCMOS/LVTTL interface levels. Output supply pins. Determines output divider values in Table 3. Pulldown LVCMOS/LVTTL interface levels. Clock select input. When HIGH, selects differential CLK1, nCLK1. Pulldown When LOW, selects differential CLK0, nCLK0. LVCMOS/LVTTL interface levels. Core supply pin.
Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. 11 nCLK0 Input Pulldown 13 VDDA Power Analog supply pin. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. 14 nCLK1 Input Pulldown 15 CLK1 Input Pulldown Non-inver ting differential clock input. Selects between the PLL and reference clock as input to the dividers. 16 PLL_SEL Input Pullup When LOW, selects the reference clock (PLL Bypass). When HIGH, selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels. LVCMOS/LVTTL feedback input to phase detector for regenerating 17 FB_IN Input Pulldown clocks with "zero delay". Connect to one of the outputs. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are 18 MR Input Pulldown reset causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance VDD, VDDA, VDDO = 3.465V VDD, VDDA, VDDO = 2.625V 5 7 Test Conditions Minimum Typical 4 51 51 23 17 12 Maximum Units pF K K pF pF
87004AG
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REV. A JUNE 16, 2004
Integrated Circuit Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Outputs PLL_SEL = 1 PLL Enable Mode Q0:Q3 /1 /1 /1 /1 /2 /2 /2 /4 /4 /8 x2 x2 x2 x4 x4 x8
TABLE 3A. PLL ENABLE FUNCTION TABLE
Inputs SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference Frequency Range (MHz) 125 - 250 62.5 - 125 31.25 - 62.5 15.625 -31.25 125 - 250 62.5 - 125 31.25 - 62.5 125 - 250 62.5 - 125 125 - 250 62.5 - 125 31.25 - 62.5 15.625 - 31.25 31.25 - 62.5 15.625 - 31.25 15.625 - 31.25
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
87004AG
SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
S E L0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Outputs PLL_SEL = 0 PLL Bypass Mode Q0:Q3 /8 /8 /8 / 16 / 16 / 16 / 32 / 32 / 64 / 128 /4 /4 /8 /2 /4 /2
REV. A JUNE 16, 2004
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Integrated Circuit Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 70C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 100 16 6 Units V V V mA mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol VIH Parameter Input High Voltage Input Low Voltage PLL_SEL, CLK_SEL, SEL0, SEL1, SEL2, SEL3, FB_IN, MR PLL_SEL, CLK_SEL, SEL0, SEL1, SEL2, SEL3, FB_IN, MR CLK_SEL, MR, FB_IN, SEL0, SEL1, SEL2, SEL3 PLL_SEL CLK_SEL, MR, FB_IN, SEL0, SEL1, SEL2, SEL3 PLL_SEL VDD = VIN = 3.465V, VDD = VIN = 2.625V VDD = VIN = 3.465V, VDD = VIN = 2.625V VDD = 3.465V, VIN = 0V, VDD = 2.625V, VIN = 0V VDD = 3.465V, VIN = 0V, VDD = 2.625V, VIN = 0V VDDO = 3.465V VDDO = 2.625V -5 -150 2.6 1.8 0.5 Test Conditions Minimum Typical 2 Maximum VDD + 0.3 Units V
VIL
-0.3
0.8 150 5
V A A A A V V V
IIH
Input High Current
IIL
Input Low Current
VOH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1 VDDO = 3.465V or 2.625V VOL NOTE 1: Outputs terminated with 50 to VDDO/2. In the Parameter Measurement Information Section, see Output Load Test Circuit Diagrams.
87004AG
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4
REV. A JUNE 16, 2004
Integrated Circuit Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Test Conditions CLK0, CLK1 VDD = VIN = 3.465V, VDD = VIN = 2.625V VDD = VIN = 3.465V, VDD = VIN = 2.625V VDD = 3.465V, VIN = 0V, VDD = 2.625V, VIN = 0V VDD = 3.465V, VIN = 0V, VDD = 2.625V, VIN = 0V -5 -150 Minimum Typical Maximum 150 150 Units A A A A V V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol Parameter
IIH
Input High Current nCLK0, nCLK1 CLK0, CLK1
IIL
Input Low Current nCLK0, nCLK1
Peak-to-Peak Input Voltage 0.15 1.3 Common Mode Input Voltage; GND + 0.5 VDD - 0.85 VCMR NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V.
V PP
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 2.375 Typical 2.5 2.5 2.5 Maximum 2.625 2.625 2.625 96 15 6 Units V V V mA mA mA
87004AG
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REV. A JUNE 16, 2004
Integrated Circuit Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Test Conditions PLL_SEL = 0V f 250MHz, Qx / 2 PLL_SEL = 3.3V fREF 167MHz, Qx / 1 PLL_SEL = 0V fOUT > 40MHz 20% to 80% 400 Minimum 15.625 5 -75 50 40 30 Typical Maximum 250 6 175 50 45 1 800 Units MHz ns ps ps ps ms ps %
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol fMAX tPD t(O) Parameter Output Frequency Propagation Delay, CLK0, nCLK0 NOTE 1 CLK1, nCLK1 Static Phase Offset; CLK0, nCLK0 NOTE 2, 4 CLK1, nCLK1 Output Skew; CLK0, nCLK0 NOTE 3, 4 CLK1, nCLK1 Cycle-to-Cycle Jitter ; NOTE 4 PLL Lock Time Output Rise/Fall Time
tsk(o) tjit(cc)
tL tR / tF
odc Output Duty Cycle 40 50 60 NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol fMAX tPD t(O) Parameter Output Frequency Propagation Delay, CLK0, nCLK0 NOTE 1 CLK1, nCLK1 Static Phase Offset; CLK0, nCLK0 NOTE 2, 4 CLK1, nCLK1 Output Skew; CLK0, nCLK0 NOTE 3, 4 CLK1, nCLK1 Cycle-to-Cycle Jitter ; NOTE 4 PLL Lock Time Output Rise/Fall Time 20% to 80% 400 Test Conditions PLL_SEL = 0V f 250MHz, Qx / 2 PLL_SEL = 2.5V fREF 167MHz, Qx / 1 PLL_SEL = 0V fOUT > 40MHz Minimum 15.625 5.3 -175 -25 40 35 Typical Maximum 250 6.7 125 45 45 1 700 Units MHz ns ps ps ps ms ps %
tsk(o) tjit(cc)
tL tR / tF
odc Output Duty Cycle 44 50 56 NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
87004AG
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REV. A JUNE 16, 2004
Integrated Circuit Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V5% 1.25V5%
VDD, VDDA, VDDO
SCOPE
Qx
VDD, VDDA, VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
V DD
V
DDO
nCLK0, nCLK1
V
PP
Qx
Cross Points
2
V
CMR
CLK0, CLK1
Qy
V
DDO
2 tsk(o)
GND
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
V
DDO
V
DDO
V
DDO
80% 20% tR
80% 20% tF
Q0:Q3
87004AG
2
2
2
tcycle
n
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
tcycle n+1
Clock Outputs
OUTPUT RISE/FALL TIME
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REV. A JUNE 16, 2004
Integrated Circuit Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
nCLK0, nCLK1 CLK0, CLK1
VOH VOL VOH VDDO 2 VOL
nCLK0, nCLK1 CLK0, CLK1
VDDO 2 t
FB_IN
t(O)
VDDO 2 t PW t PERIOD
Q0:Q3
PD
t(O) mean = Static Phase Offset (where t(O) is any random sample, and t(O) mean is the average of the sampled cycles measured on controlled edges)
STATIC PHASE OFFSET
PROPAGATION DELAY
VDDO
VDDO 2
Q0:Q3
2
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
87004AG
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8
REV. A JUNE 16, 2004
Integrated Circuit Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87004 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA.
3.3V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
87004AG
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REV. A JUNE 16, 2004
Integrated Circuit Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
LVDS_Driv er
Zo = 50 Ohm
CLK
R1 100
nCLK
Receiv er
Zo = 50 Ohm
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
87004AG
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REV. A JUNE 16, 2004
Integrated Circuit Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 6.
JAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 200
63C/W
500
60C/W
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87004 is: 2578
87004AG
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11
REV. A JUNE 16, 2004
Integrated Circuit Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
24 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
87004AG
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REV. A JUNE 16, 2004
Integrated Circuit Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Package 24 Lead TSSOP 24 Lead TSSOP on Tape and Reel 24 Lead "Lead Free" TSSOP 24 Lead "Lead Free" TSSOP on Tape and Reel Count 60 per tube 2500 60 per tube 2500 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS87004AG ICS87004AGT ICS87004AG ICS87004AGT Marking ICS87004AG ICS87004AG ICS87004AG ICS87004AG
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87004AG
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REV. A JUNE 16, 2004
Integrated Circuit Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
REVISION HISTORY SHEET Description of Change Ordering Information table - added "Lead-Free" par t number. Date 6/16/04
Rev A
Table T8
Page 13
87004AG
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REV. A JUNE 16, 2004

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