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CS8553 TV Encoder
GENERAL DESCRIPTION The CS8553 provides full conversion from digital video format YCbCr into NTSC/PAL composite. It can be used in VCD, DVD, and digital VCR applications. Two times oversampling reduces the output filter requirements and guarantees no alias interference by internal UV filters and Y filter. A 9-bit DAC provides a composite video output with high quality image. 32-pin package and pin assignment make the CS8553 compatible with major vendors. FEATURES * Especially designed for VCD, Karaoke, digital VCR, DVD, DIGITAL set-top box. * Supports the following 4 modes: NTSC, PAL-M, PAL-BDGHI, PAL-Nc. * 8-bit 4:2:2 YCbCr inputs for glueless interface to MPEG decoders. * CVBS (composite YC) outputs. * Supports CCIR-601 format, non-square pixel * 2x oversampling simplifying external filtering. * 6MHz and 1.3MHz anti-alias filters for Y and U/V channels each. * 1 channel of 9-bit DAC. * Supports master and slave modes. * Supports interlace operation only. * Automatic mode detection/switching in slave mode. * 3.3V supply voltage; 5V tolerant for all digital I/O pins.
BLOCK DIAGRAM
H, V-SYNC
VIDEO-TIMING CONTROLLER
SUB-CARRIER GENERATION
SINE-TABLE
CLK_27 SLEEP u-FILTER SERIAL P[7:0] TO PARALLEL 4:2:2 to 4:4:4 INTERPOLATION y-FILTER v-FILTER COLOR-BURST & MODULATION & MIXER
CVBS/Y DAC
MODE[3:0] SVIDEO MASTER CBSWAP
DACMAPPING
VREF_O
FSADJUST
COMP
Myson Century, Inc. Taiwan: No. 2, Industry East Rd. III, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349
USA: 1485 Saratoga Ave. #200 San Jose, CA, 95129 Tel: 408-973-8388 Fax: 408-973-9388
Sales@myson.com.tw www.myson.com.tw Rev. 1.3 January 2003 page 1 of 21
CS8553
PIN CONNECTION DIAGRAM
CVBS/Y
32
31
30
29
28
27
26
FADJI COMPI VAA VREFO VREFI NC NC VSS
25
CLK_27
HSYNC
VSYNC
VDD
VSS
VSS
VSS
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 9
24 23 22 21 20 19 18 17
P7 P6 P5 P4 P3 P2 P1 P0
CS8553T
SVIDEOI
CBSWAPI
MASTERI
SLEEP
MD3
MD2
MD1
Figure-1 32-pin TQFP
MD0
page 2 of 21
CS8553
PIN DESCRIPTION
Name CLK_27 VSYNC HSYNC P[7:0] I/O I I/O I/O I TQFP Pin No. 25 28 29 24-17 Description Pixel clock, 27MHz, twice the Y sample rate Vertical sync, output in master mode or input in slave mode, is synchronized by CLK. Horizontal sync, output in master mode or input in slave mode, is synchronized by CLK too. YCbCr pixel inputs (TTL compatible). Also, synchronized by CLK with respect to the incoming HSYNC timing, the higher index corresponds to a greater significance. Configuration inputs in 0: slave mode, h and v sync are inputs. 1: master mode, h and v sync are outputs. 0: normal Cr, Cb sequence. 1: swaps Cr, Cb sequence Connected to VSS. 1: power down, reset 0: normal operation Full scale adjust control pin. A resistor RSET is connected to GND. Used to control the full-scale output current on analog outputs. Compensation pin. A 0.1F capacitor is used to bypass this pin to VCC. Voltage reference output, typically 1.2V, may be used to connect to VREFI input. Voltage reference input, typically 1.235V. A 0.11F capacitor must be used to decouple this input to GND. DAC current switch reference input, connect to VREFO output. No connection No connection Composite output or luminance (with blanking and sync) Analog power Digital power Digital ground Analog ground Analog ground
MD[3:0] MASTER CBSWAP SVIDEO SLEEP FSADJUST COMP VREFO VREFI/VRDAC
I I I I I I I I I
13-16 12 11 10 9 1 2 4 5
NC NC CVBS/Y VAA VDD GND AGND VSS
O O O
6 7 32 3 27 26 31,8 30
page 3 of 21
CS8553
FUNCTIONAL DESCRIPTION MODE configuration SeeTable 1 to Table 3 for details. master = 1: master mode Horizontal sync and vertical sync are generated from internal timing and are output at the rising edge of clk_27. md[3]: Defines EFIELD function 0: vsync is output pin 1: vsync is even/odd field indicator, vsync=0 even, vsync=1 odd. md[2]: Defines PAL625 function 0: 525-line operation is set. 1: 626-line operation is set. master = 0: slave mode Horizontal sync and vertical sync are inputs that are synchronized by clk_27. A falling edge of VSYNC* occurring within 1/4 of a scan line from the falling edge of HSYNC* cycle time indicates the beginning of Field-1. A falling edge of VSYNC* occurring within 1/4 of a scan line from the middle point of the line indicates the beginning of Field-2. See Figure 2. Field-1 Field-2
Figure-2 md[3]: Defines YCSWAP 0: normal operation. 1: Swap the luma and chroma samples. md[2]: Defines SETUP function 0: 7.5 IRE setup is enabled for NTSC and PAL-M, with scaling for 92.5% black-to-white range, other PALs with normal 100% black-to-white range. 1: 7.5 IRE setup is disabled for NTSC and PAL-M, with scaling for 100% black-to-white range. md[1]: Defines PALSA function, South America. 0: Normal operation. 1: PAL-M used for Brazil 525 lines operation. PAL-Nc used for Argentina 625 lines operation.
page 4 of 21
CS8553
Table-1 Mode Slave Master EFIELD PAL625 YCSWAP SETUP Mode[3] YCSWAP EFIELD Mode[2] SETUP PAL625 Mode[1] PALSA RESERVED Mode[0] RESERVED RESERVED
PALSA
EFIELD is used when configured as a master. When EFIELD is set low, the Normal vsync* signal is output on the VSYNC* pin. When EFIELD is set high, field ID information is output on the VSYNC* pin (VSYNC* low for Field-1 and high for Field-2) PAL625 is used when configured as a master. When PAL625 is set low, 525-line operation is selected. When PAL625 is set high, 625-line operation is selected. This mode is set by automatic detection when configured as a slave. YCSWAP should normally be set to zero. When configured as a slave, this bit can be set high to swap the luma and chroma samples, thus altering the pixel sequence with respect to the incoming HSYNC* timing reference. SETUP is normally low for the common video modes. The setup and scaling function is toggled when this bit is high. When SETUP is low, the 7.5IRE setup is enabled for NTSC and PAL-M with scaling amplified for a 92.5% black-to-white range. When SETUP is high, the 7.5 IRE setup is disabled for NTSC and PAL-M with 100% black-to-white range scaling. Other PAL formats have setup disabled with normal 100% scaling. PALSA is normally low for the common video modes. South American video Standards can be enabled by setting this bit high. For 525-line operation, the PALSA enables PAL-M for Brazil; in 625line operation, the PALSA enables PAL-Nc for Argentina. Master mode: Mode[3:0] X000 X010 X010 X010 X100 X010 X010 X110 System (Normal setup) NTSC PAL-M PAL-BDGHI PAL-Nc PAL-625 0 0 1 1 PALSA 0 1 0 1 Fv Hz 59.94 59.94 50.00 50.00 Fh Hz 15734.26 15734.26 15625 15625
Table-2 master 1 0 1 1 0 1
Table-3 Master 0 0 0 0
Slave mode: Mode[3:0] X000 X010 X000 X010 System NTSC PAL-M PAL-BDGHI PAL-Nc PAL-625 0 0 1 1 PALSA 0 1 0 1 Fv hz 59.94 59.94 50.00 50.00 Fh Hz 15734.26 15734.26 15625 15625
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CS8553
PIXEL INPUT/OUTPUT TIMING 1. Clk is 2x the luminance sampling rate (13.5 MHz) or 4x the chrominance sampling rate (6.75 MHz), all signals are reference to rising edge. 2. In accordance with CCIR656, the input pixel pattern begins during the first clk period after the falling edge of HSYNC (same for master mode and slave mode). The input pattern is Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3,...... The input pin CBSWAP and md[3] (YCSWAP) could be used to swap cb, cr sequence and also y and cb, cr sequence. See Figure 3 and Figure 4. 3. Pixel input range: See Table 4. Y: 16-235 for normal range; 0-15, 236-255 are invalid. When Y value is between 0-15, clamp to 16; when the Y value is between 236-255, Y is set to 235. CbCr: 16-240 for normal range with 128 mapped to 0; 0-15, 241-255 are invalid. When Cb/Cr is between 0-15, clamp to 16; when Cb/Cr is 241 to 255, Y is set to 240. Table-4
Y Cb Cr
75% amplitude, 100% saturated YCbCr color bars range
16-235 16-240 16-240
element
White
235 128 128
Yellow
162 44 142
Cyan
131 156 44
Green
112 72 58
Magenta
84 184 198
Red
65 100 212
Blue
35 212 114
black
16 128 128
CLK
HSYNC*
YCSWAP=0 P[7:0]/CBSWAP=0 P[7:0]/CBSWAP=1 YCSWAP=1 P[7:0]/CBSWAP=0 P[7:0]/CBSWAP=1 y0 y0 cb0 cr0 y1 y1 cr2 cb1 y2 y2 cb2 cr2 y3 y3 cr4 cb4 y4 y4 cb0 cr0 y0 y0 cr0 cb0 y1 y1 cb2 cr2 y2 y2 cr2 cb2 y3 y3 cb4 cr4
Figure-3 Master Mode
page 6 of 21
CS8553
CLK
HSYNC*
YCSWAP=0 P[7:0]/CBSWAP=0 P[7:0]/CBSWAP=1 YCSWAP=1 P[7:0]/CBSWAP=0 P[7:0]/CBSWAP=1 y0 y0 cb0 cr0 y1 y1 cr2 cb1 y2 y2 cb2 cr2 y3 y3 cr4 cb4 y4 y4 cb0 cr0 y0 y0 cr0 cb0 y1 y1 cb2 cr2 y2 y2 cr2 cb2 y3 y3 cb4 cr4
Figure-4 Slave Mode
page 7 of 21
CS8553
VIDEO TIMING See Table 5, Table 6 1. If master mode is selected, horizontal counter is incremented on rising edge of clk-27, and reset to 1 when htotal is hit. Vertical counter is incremented by every horizontal scan line and reset to 1 after v-total hit. The output vertical sync is 3 or 2.5 lines for 262/525 and 312/625 later. 2. If slave mode is selected, the horizontal counter is incremented on the rising of clk-27 and then reset to 1 after 2 clk cycles late of falling edge of hsync. The vertical counter is incremented on the falling edge of hsync and reset to 1 at falling edge of vertical sync ocurring within [-1/4, 1/4] of a scan line from the falling edge of hsync. 3. If the falling edge of vertical sync occurring within [-1/4,1/4] of a scan line from the falling edge of hsync indicates the even field, if within [-1/4,1/4] of middle point of scan line indicates odd field. 4. The width of horizontal sync and the start and end of color burst is automatically calculated and inserted for each mode. 5. Sync timing and burst envelopes are internally controlled. Color burst frequency is derived from the clock. Any jitter on clock may induce a color burst frequency error. 6. Timing tables: Table-5 System
NTSC PAL-BDGHI
Vertical timing table Odd-field Odd-field Active Non-active
Line 1-22 Line 1-22, 311, 312 Line 23-262 Line 23-310
Even-field Non-active
Line 263-284; 524 Line 311-335; 624, 625
Even-field Active
Line 285-525 Line 336-623
Total size
858*525 864*625
Active size
720*480 720*575
Table-6 System
Horizontal timing table: number of 13.5 MHz cycles Front-porch
20 20 20 20
Back-porch
127 127 142 142
Active
711 711 702 702
Burst-start
72 78 76 76
Burst-width
34 34 30 34
total
858 858 864 864
NTSC PAL-M PAL-BDGHI PAL-Nc
7. Color burst is disabled on appropriate scan lines. Serration and equalization pulses are generated on appropriate scan lines. For NTSC, color burst information is automatically disabled on scan line 1-9 and 264272. For PAL-M, color burst information is automatically disabled on scan line 1-11 and 264-273 for field 1, 2, 5, and 6. However, for field 3, 4, 7 and 8, burst is disabled at scan line 1-10, 264-272. For PAL-BDGHINc, color burst information is automatically disabled on scan line 1-6 and 310-318 and 623-625 for field 1,2,5,6. However, for field 3,4,7,8 burst is disabled at scan line 1-5,311-319,622-625. See the following Figure 5, Figure 6 and Figure 7.
page 8 of 21
CS8553
Start of VSYNC Analog Field 1
523
524
525
1
2
3
4
5
6
7
8
9
10
21
22
Burst Phase Analog Field 2
261
262
263
264
265
266
267
268
269
270
271
272
284
285
286
Analog Field 3
523
524
525
1
2
3
4
5
6
7
8
9
10
21
22
Burst Phase Analog Field 4
261
262
263
264
265
266
267
268
269
270
271
272
284
285
286
burst begins with positive half-cycle burst phase=reference phase=180 relative to B-Y
burst begins with negative half-cycle burstphase=reference phase=180 relative to B-Y
Figure-5 Interface 525-line (NTSC) video timing
page 9 of 21
CS8553
Start of VSYNC Analog Field 1, 5
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
-U Phase Field 1 -U Phase Field 5
Analog Field 2, 6
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog Field 3, 7
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
Analog Field 4, 8
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
burst phase = reference phase=135 relative to U PAL switch = 0, +V component
burst phase = reference phase = 225 relative to U PAL switch = 1, -V component
Figure-6 Interface 625-line (PAL-B,D,G,H,I,N,Nc) video timing
page 10 of 21
CS8553
Start of VSYNC
Analog Field 1
523
524
525
1
2
3
4
5
6
7
8
9
10
11
12
21
22
Burst Phase Analog Field 2
261
262
263
264
265
266
267
268
269
270
271
272
273
274
284
285
Analog Field 3
523
524
525
1
2
3
4
5
6
7
8
9
10
11
12
21
22
Burst Phase Analog Field 4
261
262
263
264
265
266
267
268
269
270
271
272
273
274
284
285
burst phase=feference phase=135relative to U PAL switch = 0, +V component
burst phase=reference phase=225 relative to U PAL switch = 0, -V component
Figure-7 Interlace 525-line (PALM) video timing
page 11 of 21
CS8553
ANTI-ALIAS FILTERS CHARACTERISTICS The Y and the U, V are up-samples to clk, 27MHz after 4:2:2 to 4:4:4 conversion. Y is filtered by a filter whose passband is 6MHz. And U, V are also filtered by passband = 1.3MHz filters. Please refer to Figure 8 to Figure 11
1 0.5 0 -0.5 dB -1
-1.5 -2 -2.5 -3 0 1 2 3 4 frequency (MHz) 5 6
Figure-8 2X Sample Y filter frequency response/passband
0 -10 -20 dB -40 -30 -50 -60
0
2
4
6 8 frequency (MHz)
10
12
14
Figure-9 2X Sample Y filter frequency response/stopband
page 12 of 21
CS8553
1 0.5 0 -0.5 dB -1
-1.5 -2 -2.5 -3 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
frequency (MHz)
Figure-10 2X U/V filter frequency response/passband
0 -10 -20 dB -40 -30 -50 -60
0
2
4
6 8 frequency (MHz)
10
12
14
Figure-11 2X U/V filter frequency response/stopband
page 13 of 21
CS8553
DAC MAPPING Depends on the video output mode, the color bars mapping to DAC are specified in Table 7, Table 8 and Figure 12, Figure 13. Where white is 400. For PAL-BDGHINc blank = 120. For NTSC/PAL-M blank = 114 (setup = 0), 1 IRE = 2.857; if setup = 1, blank = 112, 1 IRE = 2.8. Table-7 composite NTSC/PAL 525
Typical with 37.5 load, vref_o = vref_i, SETUP = 0 100% saturation color bars.
Description
Peak C (high) White Burst (high) Black Blank Burst (low) Peak C (low) Sync
DAC data
488 400 171 136 114 57 48 0
Sync interval
0 0 0 0 0 0 0 1
mA V 32.55 1.221 26.68 1.000 100 IRE 400 370 321 291 245 215 11.41 0.423 9.07 0.34 7.6 0.285 3.8 0.00 0.143 0.00 166 20 IRE 20 IRE 40 IRE sync level 7.5 IRE 136 114 blank level
Figure-12 colors, composite NTSC/PAL 525 video output waveform
page 14 of 21
CS8553
Table-8 composite PAL-BDGHINc 625 Typical with 37.5 load, vref_o = vref_i, SETUP = 0 100% saturation (100/0/100/0) color bars. Description
Peak C (high) White Burst (high) Black Blank Burst (low) Peak C (low) Sync
DAC data
493 400 180 120 120 60 27 0
Sync interval
0 0 0 0 0 0 0 1
mA V 32.88 1.233 26.68 1.000 400 368 319 284 236 12.01 0.45 8.0 4.0 1.8 0.00 0.30 0.15 0.068 0.00 sync level 204 152 120 black/blank level
Figure-13 Colors, composite PAL-BDGHINc 625 video output waveform
page 15 of 21
CS8553
RECOMMENDED OPERATING CONDITIONS Symbol VAA TA RL VREF_IN Power Supply Ambient Operating Temperature DAC Output Load External Voltage Reference Nominal RSET 1.11 Parameter Min 3.0 0 Typ 3.3 37.5 1.23 850 Max 3.6 70 -1.35 Unit V C V
ABSOLUTE MAXIMUM RATINGS Symbol VAA TA TS TJ Parameter Power Supply (Measured to ground) Ambient Operating Temperature Voltage on Any Signal Pin Storage Temperature Junction Temperature Min --55 GND-0.3 -65 Typ --Max 5 125 VAA+0.3 +150 +150 Unit V C V C C
page 16 of 21
CS8553
DC CHARACTERISTICS (Recommended operating conditions using external voltage reference with RSET = 850, VREFIN = 1.23V, NTSC CCIR601 operation and clock frequency = 27MHz at 25C, +3.3V) Symbol IAA INL DNL VOC Parameter VAA Supply Current Video D/A Resolution Integral Nonlinearity Differential Nonlinearity Maximum Output Current Output Compliance Video level Error Full-Scale DAC Output Digital Inputs VIH VIL IIH IIL VOH VOL IOZ VREF_IN Input High Voltage Input Low Voltage Input High current (Vin=2.4V) Input Low current (Vin=0.4V) Digital Outputs Output High Voltage (IOH=-400A) Output Low Voltage (IOL=3.2mA) Three-State Current VREF_IN Input Current 1.11 10 1.23 10 1.35 2.4 0.4 50 V V A A V A 2.0 GND-0.3 VAA+0.3 0.8 1 -1 V V A A 182.5 0 9 9 Min Typ Max 105 9 1 1 35 1.5 5 Unit mA Bits LSB LSB mA V % IRE
VREF_OUT VREF_OUT Output Voltage IREF_OUT VREF_OUT current
page 17 of 21
CS8553
AC CHARACTERISTICS (Recommended operating conditions using external voltage reference with RSET = 850, VREFIN = 1.23V, NTSC CCIR601 operation and clock frequency = 27MHz at 25C, +3.3V) Symbol Parameter Luminance Bandwidth Chrominance Bandwidth Differential Gain Differential Phase SNR Hue Accuracy Color Saturation Accuracy 4 Analog Output Delay Analog Output Rise Time Analog Output Setting Time 1 2 3 Fck Pixel/Control Setup Time Pixel/Control Hold Time Control Output Delay Time CLOCK Frequency CLOCK Pulse Width Low Time CLOCK Pulse Width High Time 10 10 1 3 15 27 Min Typ Fck/4 1.3 1 1 60 1.5 1.5 30 3 30 3 3 Max Unit MHz MHz % dB % ns ns ns ns ns ns MHz ns ns
page 18 of 21
CS8553
Video Input and Output Timing
CLOCK P[7:0] HSYNCN, VSYNCN (slave mode) HSYNCN, VSYNCN (master mode)
3 4 pixel 1 pixel 0 1 2 pixel 0 pixel 1
Analog output
Figure-14 Video Input and Output Timing
page 19 of 21
CS8553
PACKAGE OUTLINE 32-pin TQFP
PIN 1 INDENT
E1
E
D1 D
A2
A
A1
y L L1
e C
b
DETAIL A
0.25 GAGE PLANE
Symbol A A1 A2 b C E E1 D D1 e L L1 y
Dimensions in Millimeters MIN 0.05 0.95 0.30 0.09 0.45 0 0.0 NOM 1.00 0.37 9.00 7.00 9.00 7.00 0.80 0.60 1.00 3.5 MAX 1.20 0.15 1.05 0.45 0.20 0.75 7 0.10
Dimensions in Inches MIN 0.002 0.037 0.012 0.003 0.018 0 0.000 NOM 0.039 0.014 0.354 0.276 0.354 0.276 0.031 0.024 0.039 3.5 MAX 0.047 0.006 0.041 0.017 0.008 0.030 7 0.004
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CS8553
APPLICATION SCHEMATICS
DVDD AVDD
AVDD
U2 HSYNC VSYNC CLK27M P0 P1 P2 P3 P4 P5 P6 P7 29 28 25 17 18 19 20 21 22 23 24 6 7 1 RSET 2KR-VAR HSYNC VSYNC CLK_27 P0 P1 P2 P3 P4 P5 P6 P7 NC NC FADJI
27
3
VDD
VAA
COMPI CVBS/Y SLEEP SVIDEO CBSWAP MASTER MD3 MD2 MD1 MD0
2 32 9 10 11 12 13 14 15 16 4 5
C1 DVDD 0.1uF CVBS/Y C2 0.1uF SLEEP CBSWAP MASTER MD3 MD2 MD1 MD0
RCA_JACK CVBS/Y 4 2
J1 3
VDSS
VASS VASS VASS
VREFO VREFI
R1 75 C3 0.1uF
26
8 30 31
CS8553(TQFP32)
ORDERING INFORMATION
Standard Configuration Prefix
CS
Part Type
8553
Package Type
T: TQFP
page 21 of 21
1

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