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DATA SHEET
PD753104, 753106, 753108
4-BIT SINGLE-CHIP MICROCONTROLLER
MOS INTEGRATED CIRCUIT
The PD753108 is one of the 75XL Series 4-bit single-chip microcontroller chips and has a data processing capability comparable to that of an 8-bit microcontroller. The existing 75X Series containing an LCD controller/driver supplies an 80-pin package. The PD753108 supplies a 64-pin package (12 x 12 mm), which is suitable for small-scale systems. It features expanded CPU functions and can provide high-speed operation at a low supply voltage of 1.8 V compared with the existing PD75308B. For detailed function descriptions, refer to the following user's manual. Be sure to read the document before designing.
PD753108 User's Manual: U10890E
Features
Low voltage operation: VDD = 1.8 to 5.5 V * Can be driven by two 1.5-V batteries On-chip memory * Program memory (ROM): 4096 x 8 bits (PD753104) 6144 x 8 bits (PD753106) 8192 x 8 bits (PD753108) * Data memory (RAM): 512 x 4 bits Capable of high-speed operation and variable instruction execution time for power saving * 0.95, 1.91, 3.81, 15.3 s (@ 4.19 MHz with main system clock) * 0.67, 1.33, 2.67, 10.7 s (@ 6.0 MHz with main system clock) * 122 s (@ 32.768 kHz with subsystem clock) Internal programmable LCD controller/driver Small package: 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch) One-time PROM version: PD75P3116
Application
Remote controllers, cameras, hemadynamometers, electronic scale, gas meters, etc.
Unless otherwise indicated, references in this data sheet to the PD753108 mean the
PD753104 and PD753106.
The information in this document is subject to change without notice. The mark Document No. U10086EJ3V0DS00 (3rd edition) Date Published April 1997 N Printed in Japan shows major revised points.
(c)
1995
PD753104, 753106, 753108
Ordering Information
Part number Package 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch) 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch) 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch) 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch) 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch) 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch) ROM (x 8 bits) 4096 4096 6144 6144 8192 8192
PD753104GC-xxx-AB8 PD753104GK-xxx-8A8 PD753106GC-xxx-AB8 PD753106GK-xxx-8A8 PD753108GC-xxx-AB8 PD753108GK-xxx-8A8
Remark
xxx indicates the ROM code suffix.
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PD753104, 753106, 753108
Functional Outline
Parameter Instruction execution time Function * 0.95, 1.91, 3.81, 15.3 s (@ 4.19 MHz with main system clock) * 0.67, 1.33, 2.67, 10.7 s (@ 6.0 MHz with main system clock) * 122 s (@ 32.768 kHz with subsystem clock) ROM 4096 x 8 bits (PD753104) 6144 x 8 bits (PD753106) 8192 x 8 bits (PD753108) RAM General-purpose register 512 x 4 bits * 4-bit operation: 8 x 4 banks * 8-bit operation: 4 x 4 banks 8 20 On-chip pull-up resistors which can be specified by software: 7 On-chip pull-up resistors which can be specified by software: 12 Also used for segment pins: 8 N-ch open-drain input/output pins Total LCD controller/driver 4 On-chip pull-up resistors which can be specified by mask option, 13-V withstand voltage
On-chip memory
Input/ output port
CMOS input CMOS input/output
32 16/20/24 segments (can be changed to CMOS input/ output port in 4 time-unit; max. 8) * Display mode selection: Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) * On-chip split resistor for LCD drive can be specified by mask option * Segment selection:
Timer
5 channels * 8-bit timer/event counter: 3 channels (16-bit timer/event counter, carrier generator, timer with gate) * Basic interval timer/watchdog timer: 1 channel * Watch timer: 1 channel * 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit * 2-wire serial I/O mode * SBI mode 16 bits * , 524, 262, 65.5 kHz (@ 4.19 MHz with main system clock) * , 750, 375, 93.8 kHz (@ 6.0 MHz with main system clock) (@ 4.19 MHz with main system clock or @ 32.768 kHz with subsystem clock) * 2.93, 5.86, 46.9 kHz (@ 6.0 MHz with main system clock) External: 3, Internal: 5 External: 1, Internal: 1 * Ceramic or crystal oscillator for main system clock oscillation * Crystal oscillator for subsystem clock oscillation STOP/HALT mode VDD = 1.8 to 5.5 V * 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch) * 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch) * 2, 4, 32 kHz
Serial interface
Bit sequential buffer (BSB) Clock output (PCL)
Buzzer output (BUZ)
Vectored interrupt Test input System clock oscillator
Standby function Supply voltage Package
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PD753104, 753106, 753108
CONTENTS
1. PIN CONFIGURATION (Top View) ......................................................................................................6 2. BLOCK DIAGRAM ................................................................................................................................ 8 3. PIN FUNCTIONS ...................................................................................................................................9 3.1 Port Pins ......................................................................................................................................9 3.2 Non-port Pins ............................................................................................................................ 11 3.3 Pin Input/Output Circuits ......................................................................................................... 13 3.4 Recommended Connections for Unused Pins ....................................................................... 15 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ................................................ 16 4.1 Difference between Mk I Mode and Mk II Mode ......................................................................16 4.2 Setting Method of Stack Bank Select Register (SBS) ...........................................................17 5. MEMORY CONFIGURATION .............................................................................................................18 6. PERIPHERAL HARDWARE FUNCTION ........................................................................................... 23 6.1 Digital I/O Port ........................................................................................................................... 23 6.2 Clock Generator ........................................................................................................................23 6.3 Subsystem Clock Oscillator Control Functions ....................................................................25 6.4 Clock Output Circuit .................................................................................................................26 6.5 Basic Interval Timer/Watchdog Timer ..................................................................................... 27 6.6 Watch Timer .............................................................................................................................. 28 6.7 Timer/Event Counter .................................................................................................................29 6.8 Serial Interface ..........................................................................................................................33 6.9 LCD Controller/Driver ...............................................................................................................35 6.10 Bit Sequential Buffer ................................................................................................................ 37 7. INTERRUPT FUNCTION AND TEST FUNCTION .............................................................................. 38 8. STANDBY FUNCTION ........................................................................................................................40 9. RESET FUNCTION .............................................................................................................................41 10. MASK OPTION ...................................................................................................................................44 11. INSTRUCTION SET ............................................................................................................................ 45 12. ELECTRICAL SPECIFICATIONS ....................................................................................................... 59 13. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ............................................................... 75 14. PACKAGE DRAWINGS ..................................................................................................................... 78 15. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 80
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PD753104, 753106, 753108
APPENDIX A. PD75308B, 753108 AND 75P3116 FUNCTIONAL LIST .............................................. 81 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................. 83 APPENDIX C. RELATED DOCUMENTS ................................................................................................ 87
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PD753104, 753106, 753108
1. PIN CONFIGURATION (Top View)
* 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
PD753104GC-xxx-AB8, PD753106GC-xxx-AB8, PD753108GC-xxx-AB8
* 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
PD753104GK-xxx-8A8, PD753106GK-xxx-8A8, PD753108GK-xxx-8A8
COM3 COM2 COM1 COM0
S10 50
64
63
62
61
60
59
58
57
56
55
54
53
52
51
49
S11
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
BIAS VLC0 VLC1 VLC2 P30/LCDCL P31/SYNC P32 P33 VSS P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
S12 S13 S14 S15 S16/P93 S17/P92 S18/P91 S19/P90 S20/P83 S21/P82 S22/P81 S23/P80 P23/BUZ P22/PCL/PTO2 P21/PTO1 P20/PTO0
P63/KR3
RESET
XT1
XT2
P12/INT2/TI1/TI2
P00/INT4
P01/SCK
P02/SO/SB0
P03/SI/SB1
P10/INT0
P11/INT1
Note
Connect the IC (Internally Connected) pin directly to VDD.
6
P13/TI0
Note
IC
VDD
X1
X2
PD753104, 753106, 753108
Pin Identification P00 to P03 P10 to P13 P20 to P23 P30 to P33 P50 to P53 P60 to P63 P80 to P83 P90 to P93 KR0 to KR3 SCK SI SO SB0, SB1 RESET S0 to S23 COM0 to COM3 : : : : : : : : : : : : : : : : Port 0 Port 1 Port 2 Port 3 Port 5 Port 6 Port 8 Port 9 Key Return 0 to 3 Serial Clock Serial Input Serial Output Serial Data Bus 0, 1 Reset Segment Output 0 to 23 Common Output 0 to 3 VLC0 to VLC2 BIAS LCDCL SYNC TI0 to TI2 PTO0 to PTO2 BUZ PCL INT0, INT1, INT4 INT2 X1, X2 XT1, XT2 VDD VSS IC : : : : : : : : : : : : : : : LCD Power Supply 0 to 2 LCD Power Supply Bias Control LCD Clock LCD Synchronization Timer Input 0 to 2 Programmable Timer Output 0 to 2 Buzzer Clock Programmable Clock External Vectored Interrupt 0, 1, 4 External Test Input 2 Main System Clock Oscillation 1, 2 Subsystem Clock Oscillation 1, 2 Positive Power Supply Ground Internally Connected
7
8
PORT0 PORT1 PORT2 PORT3 PORT5 GENERAL REG. PORT6 PROGRAM MEMORY Note (ROM) DECODE AND CONTROL DATA MEMORY (RAM) 512 x 4 BITS PORT8 PORT9 4 4 4 P60 to P63 P80 to P83 P90 to P93 4 4 4 P20 to P23 P30 to P33 P50 to P53 4 P10 to P13 4 P00 to P03 INTW ALU SBS BANK fLCD
BUZ/P23 PROGRAM COUNTER CY SP(8)
WATCH TIMER
2. BLOCK DIAGRAM
BASIC INTERVAL TIMER/ WATCHDOG TIMER INTBT
TI0/P13
PTO0/P20 TOUT0
8-BIT TIMER/EVENT COUNTER #0
INTT0 INTT1
TI1/TI2/P12/INT2
PTO1/P21
PTO2/PCL/P22 TOUT0
8-BIT TIMER/EVENT CASCADED COUNTER #1 16-BIT TIMER/ 8-BIT EVENT TIMER/EVENT COUNTER COUNTER #2
LCD CONTROLLER/ 16 DRIVER 4 4 fx/2
N
S0 to S15 S16/P93 to S19/P90 S20/P83 to S23/P80 4 COM0 to COM3
INTT2 CPU CLOCK
SI/SB1/P03 SO/SB0/P02 SCK/P01 INTCSI TOUT0 INT1
CLOCKED SERIAL INTERFACE
CLOCK CLOCK SYSTEM CLOCK STAND BY OUTPUT DIVIDER GENERATOR CONTROL CONTROL MAIN SUB
fLCD
INT0/P10 INT1/P11 INT4/P00 INT2/P12/TI1/TI2 KR0/P60 to KR3/P63 PCL/PTO2/P22 X1 X2 XT1XT2
4
INTERRUPT CONTROL
BIAS VLC0 VLC1 VLC2 SYNC/P31 LCDCL/P30 IC VDD VSS RESET
BIT SEQ. BUFFER (16)
PD753104, 753106, 753108
Note
The ROM capacity depends on the product.
PD753104, 753106, 753108
3. PIN FUNCTIONS 3.1 Port Pins (1/2)
Alternate Function INT4 SCK SO/SB0 SI/SB1 INT0 INT1 TI1/TI2/INT2 TI0 Input/Output PTO0 PTO1 PCL/PTO2 BUZ Input/Output LCDCL SYNC - - Input/Output - Programmable 4-bit input/output port (PORT3). This port can be specified for input/output bit-wise. Connection of on-chip pull-up resistors can be specified by software in 4-bit units. N-ch open-drain 4-bit input/output port (PORT5). A pull-up resistor can be contained bit-wise (mask option). Withstand voltage is 13 V in open-drain mode. No Input E-B 4-bit input port (PORT1). Connection of on-chip pull-up resistors can be specified by software in 4-bit units. P10/INT0 can select noise elimination circuit. 4-bit input/output port (PORT2). Connection of on-chip pull-up resistors can be specified by software in 4-bit units. No Input 8-bit I/O No I/O Circuit TYPE Note 1 (B) (F)-A (F)-B (M)-C (B)-C
Pin Name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 P50-P53 Note 2
Input/Output Input Input/Output Input/Output Input/Output Input
Function 4-bit input port (PORT0). For P01 to P03, connection of on-chip pullup resistors can be specified by software in 3-bit units.
After Reset Input
No
Input
E-B
No
High level (when pullup resistors are provided) or highimpedance
M-D
Notes 1. 2.
Characters in parentheses indicate the Schmitt trigger input. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port), low-level input leakage current increases when input or bit manipulation instruction is executed.
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PD753104, 753106, 753108
3.1 Port Pins (2/2)
Alternate Function KR0 KR1 KR2 KR3 Input/Output S23 S22 S21 S20 Input/Output S19 S18 S17 S16 4-bit input/output port (PORT9). Connection of on-chip pull-up resistors can be specified by software in 4-bit units Note 2 . Input H 8-bit I/O No I/O Circuit TYPE Note 1 (F)-A
Pin Name P60 P61 P62 P63 P80 P81 P82 P83 P90 P91 P92 P93
Input/Output Input/Output
Function Programmable 4-bit input/output port (PORT6). This port can be specified for input/output bit-wise. Connection of on-chip pull-up resistors can be specified by software in 4-bit units. 4-bit input/output port (PORT8). Connection of on-chip pull-up resistors can be specified by software in 4-bit units Note 2 .
After Reset Input
Yes
Input
H
Notes 1. 2.
Characters in parentheses indicate the Schmitt trigger input. When these pins are used as segment signal output pins, do not connect the on-chip pull-up resistor by software.
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PD753104, 753106, 753108
3.2 Non-port Pins (1/2)
Alternate Function P13 P12/INT2/TI2 P12/INT2/TI1 Output P20 P21 P22/PCL P22/PTO2 P23 Clock output Optional frequency output (for buzzer output or system clock trimming) Serial clock input/output Serial data output Serial data bus input/output Serial data input Serial data bus input/output Edge detection vectored interrupt input (both rising edge and falling edge detection) Edge detection vectored interrupt input (detection edge can be selected). INT0/P10 can select noise elimination circuit. Rising edge detection testable input Noise elimination circuit/ asynchronous selection Asynchronous Input Input (F)-A (F)-B Timer/event counter output Input E-B I/O Circuit TYPE Note 1 (B)-C
Pin Name TI0 TI1 TI2 PTO0 PTO1 PTO2 PCL BUZ
Input/Output Input
Function Inputs external event pulses to the timer/event counter.
After Reset Input
SCK SO/SB0
Input/Output
P01 P02
SI/SB1
P03
(M)-C
INT4
Input
P00
(B)
INT0
Input
P10
Input
(B)-C
INT1
P11
INT2 KR0-KR3 S0-S15 S16-S19 S20-S23 COM0-COM3 VLC0-VLC2 Input Output Output Output Output -
P12/TI1/TI2 P60-P63 - P93-P90 P83-P80 - -
Asynchronous Input Note 2 Input Input Note 2 - (F)-A G-A H H G-B -
Falling edge detection testable input Segment signal output Segment signal output Segment signal output Common signal output LCD drive power On-chip split resistor is enabled (mask option). Output for external split resistor disconnect Clock output for externally expanded driver Clock output for externally expanded driver synchronization
BIAS LCDCL Note 4 SYNC Note 4
Output Output Output
- P30 P31
Note 3 Input Input
- E-B E-B
Notes 1. 2. 3. 4.
Characters in parentheses indicate the Schmitt trigger input. Each display output selects the following VLCX as input source. S0-S15: VLC1, COM0-COM2: VLC2, COM3: VLC0 When a split resistor is contained ........ Low level When no split resistor is contained ...... High-impedance These pins are provided for future system expansion. At present, these pins are used only as pins P30 and P31.
11
PD753104, 753106, 753108
3.2 Non-port Pins (2/2)
Alternate Function - I/O Circuit TYPE Note -
Pin Name X1 X2
Input/Output Input -
Function Crystal/ceramic connection pin for the main system clock oscillation. When the external clock is used, input the external clock to pin X1, and the inverted phase of the external clock to pin X2. Crystal connection pin for the subsystem clock oscillation. When the external clock is used, input the external clock to pin XT1, and the inverted phase of the external clock to pin XT2. Pin XT1 can be used as a 1-bit input (test) pin. System reset input (low-level active) Internally connected. Connect directly to VDD. Positive power supply Ground potential
After Reset -
XT1 XT2
Input -
-
-
-
RESET IC VDD VSS
Input - - -
- - - -
- - - -
(B) - - -
Note
Characters in parentheses indicate the Schmitt trigger input.
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PD753104, 753106, 753108
3.3 Pin Input/Output Circuits
The PD753108 pin input/output circuits are shown schematically. (1/2)
TYPE A TYPE D VDD VDD data P-ch IN N-ch output disable N-ch P-ch OUT
CMOS standard input buffer TYPE B
Push-pull output that can be placed in output high-impedance (both P-ch and N-ch off). TYPE E-B VDD P.U.R. P.U.R. enable P-ch
IN data Type D output disable IN/OUT
Type A Schmitt trigger input with hysteresis characteristics
P.U.R. : Pull-Up Resistor
TYPE B-C
TYPE F-A VDD VDD P.U.R. P.U.R. enable P.U.R. enable data output disable IN Type B Type D P.U.R. P-ch
P-ch
IN/OUT
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
13
PD753104, 753106, 753108
(2/2)
TYPE F-B VDD P.U.R. P.U.R enable output disable (P) data output disable output disable (N) N-ch data output disable TYPE E-B VDD P-ch IN/OUT P-ch SEG data IN/OUT TYPE G-A TYPE H
P.U.R. : Pull-Up Resistor TYPE G-A VLC0 P-ch N-ch P-ch N-ch P-ch N-ch P.U.R. enable TYPE M-C VDD P.U.R. P-ch IN/OUT data output disable N-ch VLC2 P-ch N-ch N-ch P.U.R. : Pull-Up Resistor TYPE G-B TYPE M-D
VLC1
OUT SEG data
N-ch
VDD P.U.R. (Mask Option) IN/OUT
VLC0 VLC1 P-ch N-ch
P-ch N-ch data P-ch N-ch output disable input instruction N-ch (+13 V withstand voltage)
VDD P-ch P.U.R.
OUT COM data N-ch VLC2 N-ch P-ch N-ch P-ch
Note
Voltage limitation circuit (+13 V withstand voltage) Note The pull-up resistor operates only when an input instruction is executed (current flows from VDD to the pin when the pin is low).
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PD753104, 753106, 753108
3.4 Recommended Connections for Unused Pins
Table 3-1. List of Recommended Connections for Unused Pins
Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0, P11/INT1 P12/TI1/TI2/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PCL/PTO2 P23/BUZ P30/LCDCL P31/SYNC P32 P33 P50-P53 Input state: Connect to VSS Input state: Connect to VSS or VDD via a resistor individually Output state: Leave open Connect to VSS Connect to VSS or VDD Recommended Connection Connect to VSS or VDD Connect to VSS or VDD via a resistor individually
Output state: Connect to VSS (do not connect a pull-up resistor of mask option) P60/KR0-P63/KR3 Input state: Connect to VSS or VDD via a resistor individually Output state: Leave open S0-S15 COM0-COM3 S16/P93-S19/P90 Input state: Connect to VSS or VDD via a resistor individually S20/P83-S23/P80 VLC0-VLC2 BIAS Output state: Leave open Connect to VSS Only if all of VLC0 to VLC2 are unused, connect to VSS. In other cases, leave open. Connect to VSS or VDD Leave open Connect directly to VDD Leave open
XT1 Note XT2 Note IC
Note
When the subsystem clock is not used, specify SOS.0 = 1 (so as not to use the on-chip feedback resistor).
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PD753104, 753106, 753108
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Difference between Mk I Mode and Mk II Mode
The CPU of the PD753108 has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by bit 3 of the stack bank select register (SBS). * Mk I mode: Upward compatible with the PD75308B. Can be used in the 75XL CPU with a ROM capacity of up to 16 Kbytes. * Mk II mode: Incompatible with the PD75308B. Can be used in all the 75XL CPU's including those products whose ROM capacity is more than 16 Kbytes. Table 4-1. Differences between Mk I Mode and Mk II Mode
Mk I mode Number of stack bytes for subroutine instructions BRA !addr1 instruction CALLA !addr1 instruction CALL !addr instruction CALLF !faddr instruction 2 bytes 3 bytes Mk II mode
Not available
Available
3 machine cycles 2 machine cycles
4 machine cycles 3 machine cycles
Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series. Therefore, this mode is effective for enhancing software compatibility with products exceeding 16 Kbytes. When the Mk II mode is selected, the number of stack bytes used during execution of subroutine call instructions increases by one byte per stack compared to the Mk I mode. When the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes longer by one machine cycle. Therefore, use the Mk I mode if the RAM efficiency and processing performance are more important than software compatibility.
16
PD753104, 753106, 753108
4.2 Setting Method of Stack Bank Select Register (SBS)
Switching between the Mk I mode and Mk II mode can be done by the stack bank select register (SBS). Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 100xB Note at the beginning of a program. When using the Mk II mode, it must be initialized to 000xB Note. Note Set the desired value in the x position. Figure 4-1. Stack Bank Select Register Format
Address F84H 3 SBS3 2 1 0 SBS0 Symbol SBS
SBS2 SBS1
Stack area specification 0 0 0 1 Memory bank 0 Memory bank 1
Other than above setting prohibited
0
0 must be set in the bit 2 position.
Mode switching specification 0 1 Mk II mode Mk I mode
Caution Since SBS. 3 is set to "1" after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to "0" to select the Mk II mode.
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PD753104, 753106, 753108
5. MEMORY CONFIGURATION
Program Memory (ROM) .... 4096 x 8 bits (PD753104) .... 6144 x 8 bits (PD753106) .... 8192 x 8 bits (PD753108) * Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset start is possible from any address. * Addresses 0002H to 000DH Vector table wherein the program start address and the values set for the RBE and MBE by each vectored interrupt are written. Interrupt processing can start from any address. * Addresses 0020H to 007FH Table area referenced by the GETI instruction Note. Note The GETI instruction realizes a 1-byte instruction on behalf of any 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the number of program steps. Data Memory (RAM) * Data area ... 512 words x 4 bits (000H to 1FFH) * Peripheral hardware area ... 128 words x 4 bits (F80H to FFFH)
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PD753104, 753106, 753108
Figure 5-1. Program Memory Map (1/3) (a) PD753104
Address 7 6 5 0 4 0 Internal reset start address Internal reset start address 0 0 2 H MBE RBE 0 0 INTBT/INT4 INTBT/INT4 0 0 4 H MBE RBE 0 0 INT0 INT0 0 0 6 H MBE RBE 0 0 INT1 INT1 0 0 8 H MBE RBE 0 0 INTCSI INTCSI 0 0 A H MBE RBE 0 0 INTT0 INTT0 0 0 C H MBE RBE 0 0 INTT1/INTT2 INTT1/INTT2 start address start address start address start address start address start address start address start address start address start address start address start address 0 (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) CALLF !faddr instruction entry address
0 0 0 H MBE RBE
Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1 Note or CALLA !addr1 Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address -15 to -1, +2 to +16
020H GETI instruction reference table 07FH 080H
BRCB !caddr instruction branch address
7FFH 800H
Branch destination address and subroutine entry address when GETI instruction is executed
FFFH
Note
Can be used in Mk II mode only.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction.
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PD753104, 753106, 753108
Figure 5-1. Program Memory Map (2/3) (b) PD753106
Address 7 6 5 0 Internal reset start address Internal reset start address 0 0 0 2 H MBE RBE 0 INTBT/INT4 INTBT/INT4 0 0 0 4 H MBE RBE 0 INT0 INT0 0 0 0 6 H MBE RBE 0 INT1 INT1 0 0 0 8 H MBE RBE 0 INTCSI INTCSI 0 0 0 A H MBE RBE 0 INTT0 INTT0 0 0 0 C H MBE RBE 0 INTT1/INTT2 INTT1/INTT2 start address start address start address start address start address start address start address start address start address start address start address start address 0 (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1 Note or CALLA !addr1 Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address -15 to -1, +2 to +16
0 0 0 0 H MBE RBE
0020H GETI instruction reference table 007FH 0080H
BRCB !caddr instruction branch address
Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 0800H
0FFFH 1000H BRCB !caddr instruction branch address 17FFH
Note
Can be used in Mk II mode only.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
20
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
PD753104, 753106, 753108
Figure 5-1. Program Memory Map (3/3) (c) PD753108
Address 7 6 5 0 Internal reset start address Internal reset start address 0 0 0 2 H MBE RBE 0 INTBT/INT4 INTBT/INT4 0 0 0 4 H MBE RBE 0 INT0 INT0 0 0 0 6 H MBE RBE 0 INT1 INT1 0 0 0 8 H MBE RBE 0 INTCSI INTCSI 0 0 0 A H MBE RBE 0 INTT0 INTT0 0 0 0 C H MBE RBE 0 INTT1/INTT2 INTT1/INTT2 start address start address start address start address start address start address start address start address start address start address start address start address 0 (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) BRCB !caddr instruction branch address CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1 Note or CALLA !addr1 Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address -15 to -1, +2 to +16
0 0 0 0 H MBE RBE
0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 0800H
0FFFH 1000H BRCB !caddr instruction branch address 1FFFH
Note
Can be used in Mk II mode only. eight bits of PC by executing the BR PCDE or BR PCXA instruction.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
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PD753104, 753106, 753108
Figure 5-2. Data Memory Map
Data memory 000H General-purpose register area 01FH 0 256 x 4 (224 x 4) Stack area Note Data area static RAM (512 x 4) 0FFH 100H 256 x 4 (224 x 4) 1 1DFH 1E0H (24 x 4) 1F7H 1F8H 1FFH (8 x 4) Memory bank
(32 x 4)
Display data memory
Not incorporated
F80H
Peripheral hardware area
128 x 4
15
FFFH
Note
Either memory bank 0 or 1 can be selected for the stack area.
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PD753104, 753106, 753108
6. PERIPHERAL HARDWARE FUNCTION 6.1 Digital I/O Port
There are three kinds of I/O port. * CMOS input ports (PORT 0, 1) :8
* CMOS input/output ports (PORT 2, 3, 6, 8, 9) : 20 * N-ch open-drain input/output ports (PORT 5) : 4 Total 32 Table 6-1. Types and Features of Digital Ports
Port name PORT0 Function 4-bit input Operation and features When the serial interface function is used, the dual function pins function as output ports depending on the operation mode. 4-bit input only port. 4-bit input/ output Can be set to input mode or output mode in 4-bit units. Can be set to input mode or output mode bit-wise. 4-bit input/ output (N-ch opendrain, 13 V withstand voltage) 4-bit input/ output Can be set to input mode or output mode in 4-bit units. On-chip pull-up resistor can be specified bit-wise by mask option. Remarks Also used for the INT4, SCK, SO/SB0, SI/SB1 pins. Also used for the INT0-INT2/ TI1/TI2, TI0 pins. Also used for the PTO0PTO2/PCL, BUZ pins. Also used for the LCDCL, SYNC pins. --
PORT1 PORT2 PORT3 PORT5
PORT6 PORT8 PORT9
Can be set to input mode or output mode bit-wise. Can be set to input mode or output mode in 4-bit units. Ports 8 and 9 are paired and data can be input/ output in 8-bit units.
Also used for the KR0-KR3 pins. Also used for the S20-S23 pins. Also used for the S16-S19 pins.
6.2 Clock Generator
The clock generator is a device that generates the clock which is supplied to peripheral hardware on the CPU and is configured as shown in Figure 6-1. The clock generator operates according to how the processor clock control register (PCC) and system clock control register (SCC) are set. There are two kinds of clocks, main system clock and subsystem clock. The instruction execution time can also be changed. * 0.95, 1.91, 3.81, 15.3 s (main system clock: in 4.19-MHz operation) * 0.67, 1.33, 2.67, 10.7 s (main system clock: in 6.0-MHz operation) * 122 s (subsystem clock: in 32.768-kHz operation)
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PD753104, 753106, 753108
Figure 6-1. Clock Generator Block Diagram
XT1 VDD XT2 X1 VDD X2 Main system clock oscillator fX 1/1 to 1/4096 Divider 1/2 1/4 1/16 Subsystem clock oscillator fXT LCD controller/driver Watch timer
* Basic interval timer (BT) * Timer/event counter * Serial interface * Watch timer * LCD controller/driver * INT0 noise elimination circuit * Clock output circuit
Selector WM.3 SCC SCC3
Internal bus
Oscillation stop Selector
Divider 1/4 * CPU * INT0 noise elimination circuit * Clock output circuit
SCC0 PCC PCC0 PCC1 4 PCC2 HALT Note PCC3 STOP Note R Q HALT F/F S
PCC2, PCC3 Clear
STOP F/F Q S
Wait release signal from BT RESET signal
R
Standby release signal from interrupt control circuit
Note Instruction execution Remarks 1. 2. 3. 4. 5. 6. fX = Main system clock frequency fXT = Subsystem clock frequency = CPU clock PCC: Processor Clock Control Register SCC: System Clock Control Register One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction.
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PD753104, 753106, 753108
6.3 Subsystem Clock Oscillator Control Functions
The PD753108 subsystem clock oscillator has the following two control functions. * Selects by software whether an on-chip feedback resistor is to be used or not Note. * Reduces current consumption by decreasing the drive current of the on-chip inverter when the supply voltage is high (VDD 2.7 V). Note When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the on-chip feedback resistor) by software, connect XT1 to VSS or VDD, and open XT2. consumption in the subsystem clock oscillator. The above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (SOS). (See Figure 6-2.) Figure 6-2. Subsystem Clock Oscillator This makes it possible to reduce the current
SOS.0
Feedback resistor Inverter SOS.1 XT1 XT2
VDD
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PD753104, 753106, 753108
6.4 Clock Output Circuit
The clock output circuit is provided to output the clock pulses from the P22/PTO2/PCL pin to the remote control wave outputs and peripheral LSI's. Clock output (PCL): , 524, 262, 65.5 kHz (main system clock: in 4.19-MHz operation) , 750, 375, 93.8 kHz (main system clock: in 6.0-MHz operation) Figure 6-3. Clock Output Circuit Block Diagram
From clock generator fX/23 Selector fX/24 fX/26
Selector
From timer/event counter (channel 2)
Output buffer PCL/PTO2/P22
PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 output latch
Bit 2 of PMGB Port 2 I/O mode specification bit
4 Internal bus
Remark Special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable.
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PD753104, 753106, 753108
6.5 Basic Interval Timer/Watchdog Timer
The basic interval timer/watchdog timer has the following functions. Interval timer operation to generate a reference time interrupt Watchdog timer operation to detect a runaway of program and reset the CPU Selects and counts the wait time when the standby mode is released Reads the contents of counting Figure 6-4. Basic Interval Timer/Watchdog Timer Block Diagram
From clock generator fX/25 fX/27 MPX fX/29 fX/212 3 BT Clear Clear
Basic interval timer (8-bit frequency divider)
Set
BT interrupt request flag Vectored interrupt IRQBT request signal
Wait release signal when standby is released.
Internal reset signal WDTM SET1 Note 1
BTM3 BTM2 BTM1 BTM0 BTM SET1 Note 4 8 Internal bus
Note Instruction execution
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PD753104, 753106, 753108
6.6 Watch Timer
The PD753108 has one watch timer channel which has the following functions. Sets the test flag (IRQW) at 0.5-second intervals. The standby mode can be released by the IRQW. 0.5-second interval can be created by both the main system clock (4.194304 MHz) and subsystem clock (32.768 kHz). Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the fast feed mode. Outputs the frequencies (2.048, 4.096, 32.768 kHz) to the P23/BUZ pin, usable for buzzer and trimming of system clock oscillation frequencies. Clears the frequency divider to make the watch start with zero seconds. Figure 6-5. Watch Timer Block Diagram
fW (512 Hz : 1.95 ms) 26 fW (256 Hz : 3.91 ms) 27 fX 128 From clock generator (32.768 kHz) fXT (32.768 kHz) Selector
fLCD
fW (32.768 kHz) 4 kHz 2 kHz fW fW 23 24
Divider
fW 214 2 Hz 0.5 sec
Selector
INTW IRQW set signal
Clear
Selector
Output buffer P23/BUZ
WM WM7 0 WM5 WM4 WM3 WM2 WM1 WM0
PORT2.3 P23 output latch
Bit 2 of PMGB Port 2 input/ output mode
8
Bit test instruction
Internal bus
Remark The values enclosed in parentheses are applied when fX = 4.194304 MHz and fXT = 32.768 kHz.
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PD753104, 753106, 753108
6.7 Timer/Event Counter
The PD753108 has three channels of timer/event counters. Its configuration is shown in Figures 6-6 to 6-8. The timer/event counter has the following functions. Programmable interval timer operation Square wave output of any frequency to the PTOn pin (n = 0 to 2) Event counter operation Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided frequency to the PTOn pin (frequency divider operation). Supplies the serial shift clock to the serial interface circuit. Reads the count value. The timer/event counter operates in the following four modes as set by the mode register. Table 6-2. Operation Modes of Timer/Event Counter
Channel Channel 0 Mode 8-bit timer/event counter mode Gate control function PWM pulse generator mode 16-bit timer/event counter mode Gate control function Carrier generator mode Yes No Note No No No Note No Yes No No Yes Yes Yes Yes Yes Yes Channel 1 Channel 2
Note Used for gate control signal generation
29
30
Figure 6-6. Timer/Event Counter (Channel 0) Block Diagram
Internal bus 8 TM0 0 - Modulo register (8) T0 enable flag TMOD0 TOE0 SET1 Note 8 8 P20 output latch PORT2.0 Bit 2 of PMGB Port 2 input/output mode To serial interface 8 TOUT0 Comparator (8) 8 Reset T0 MPX CP Clear Count register (8) Match TOUT F/F Output buffer PTO0/P20 INTT0 IRQT0 set signal Timer operation start RESET IRQT0 clear signal To timer/event counter (channel 2)
-
TM06 TM05 TM04 TM03 TM02
PORT1.3
Input buffer
TI0/P13
fX/24
From fX/2 clock fX/28 generator fX/210
6
Note Instruction execution
PD753104, 753106, 753108
Caution
When setting data to TM0, be sure to set bit 1 to 0.
Figure 6-7. Timer/Event Counter (Channel 1) Block Diagram
Internal bus 8 TM1 8 TMOD1 Decoder Modulo register (8) 8 Comparator (8) 8 T1 MPX CP Clear Count register (8) Match P21/PTO1 TOUT F/F Reset Output buffer T1 enable flag TOE1 SET1 Note PORT2.1 P21 output latch Bit 2 of PMGB
Port 2 input/output mode
-
TM16 TM15 TM14 TM13 TM12 TM11 TM10
PORT1.2
Input buffer
TI1/TI2/P12/INT2
Timer/event counter (channel 2) output
fX/2 fX/26 From clock 8 generator fX/2 10 fX/2 fX/212
5
RESET Timer operation start 16-bit timer/event counter mode Selector IRQT1 clear signal
Timer/event counter (channel 2) match signal (When 16-bit timer/event counter mode)
Timer/event counter (channel 2) reload signal Timer/event counter (channel 2) comparator (When 16-bit timer/event counter mode)
INTT1 IRQT1 set signal
Note Instruction execution
PD753104, 753106, 753108
31
Selector
Input buffer Reset
Comparator (8)
TOUT F/F Overflow Carrier generator mode
TI1/TI2/P12/INT2 MPX CP Clear 8 T2 Count register (8)
Selector
fX fX/2 From clock fX/24 fX/26 generator fX/28 fX/210
16-bit timer/event counter mode
Selector
32
Figure 6-8. Timer/Event Counter (Channel 2) Block Diagram
Internal bus 8 8 TMOD2H TM2
High-level period setting modulo register (8) TOE2 REMC NRZB NRZ
Reload
SET1 Note 8 8 TC2
TM26 TM25 TM24 TM23 TM22 TM21 TM20
TMOD2 Modulo register (8) TGCE
PORT1.2 Decoder MPX (8) 8
Match
8 8
PORT2.2 Bit 2 of PMGB P22 Port 2 output latch input/output
P22/PCL/PTO2
Output buffer
Timer/event counter (channel 1) clock input
INTT2 IRQT2 set signal IRQT2 clear signal
Timer operation start
RESET Timer event counter (channel 0) TOUT F/F
Timer/event counter (channel 1) clear signal (When 16-bit timer/event counter mode) Timer/event counter (channel 1) match signal (When 16-bit timer/event counter mode)
From clock output circuit
Timer/event counter (channel 1) match signal (When carrier generator mode)
PD753104, 753106, 753108
Note Instruction execution
PD753104, 753106, 753108
6.8 Serial Interface
The PD753108 incorporates a clock-synchronous 8-bit serial interface. The serial interface can be used in the following four modes. * Operation stop mode * 3-wire serial I/O mode * 2-wire serial I/O mode * SBI mode
33
ACKT
ACKE
P02/SO/SB0
Selector Bus release/ command/ acknowledge detection circuit RELD CMDD ACKD
Busy/ acknowledge output circuit
BSYE
34
Figure 6-9. Serial Interface Block Diagram
Internal bus 8/4 8 CSIM RELT Address comparator (8) SO latch SET CLR Selector Shift register (SIO) D (8) Q Match CMDT Slave address register (SVA) (8) SBIC 8 Bit test 8 Bit manipulation Bit test INTCSI Serial clock counter INTCSI control circuit IRQCSI set signal P01 output Iatch Serial clock control circuit Serial clock selector fX/23 fX/24 fX/26 TOUT0 (from timer/event counter (channel 0)) External SCK
P03/SI/SB1
PD753104, 753106, 753108
P01/SCK
PD753104, 753106, 753108
6.9 LCD Controller/Driver
The PD753108 incorporates a display controller which generates segment and common signals according to the display data memory contents and incorporates segment and common drivers which can drive the LCD panel directly. The PD753108 LCD controller/driver has the following functions: Display data memory is read automatically by DMA operation and segment and common signals are generated. Display mode can be selected from among the following five: <1> Static <2> 1/2 duty (time multiplexing by 2), 1/2 bias <3> 1/3 duty (time multiplexing by 3), 1/2 bias <4> 1/3 duty (time multiplexing by 3), 1/3 bias <5> 1/4 duty (time multiplexing by 4), 1/3 bias A frame frequency can be selected from among four in each display mode. A maximum of 24 segment signal output pins (S0 to S23) and four common signal output pins (COM0 to COM3). The segment signal output pins (S0 to S23) can be changed to the I/O ports (PORT8 and PORT9). Split resistor can be incorporated to supply LCD drive power (mask option). * Various bias methods and LCD drive voltages are applicable. * When display is off, current flowing through the split resistor is cut. Display data memory not used for display can be used for normal data memory. It can also operate by using the subsystem clock.
35
36
Figure 6-10. LCD Controller/Driver Block Diagram
Internal bus 8 Port mode
register group C 0 1
4 LCD/port selection register 1F7H 3210 Display mode register 1F0H 1EFH 3210 3210 1E0H 3210 Display control register
4
4
4
4
4
8
4
4
4 Port 3 Port mode output latch register group A
1 0 1 0
Port 8 output latch
Port 9 output latch
3210
3210
Decoder 3210 3210 3210 3210 Timing fLCD controller
Port 8 Input/output buffer Segment driver
Port 9 Input/output buffer
Segment driver
Common driver
0
1
2
3
0
1
2
3
LCD drive voltage control
LCD drive mode switching
PD753104, 753106, 753108
S23/P80
S16/P93
S15
S0
COM3 COM2 COM1 COM0 VLC2 VLC1 VLC0
P31/SYNC P30/LCDCL
PD753104, 753106, 753108
6.10 Bit Sequential Buffer ....... 16 Bits
The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing a long data bit-wise. Figure 6-11. Bit Sequential Buffer Format
Address Bit Symbol 3
FC3H 2 1 0 3
FC2H 2 1 0 3
FC1H 2 1 0 3
FC0H 2 1 0
BSB3
BSB2
BSB1
BSB0
L register
L = FH
L = CH L = BH
L = 8H L = 7H DECS L
L = 4H L = 3H
L = 0H
INCS L
Remarks 1. 2.
In the pmem.@L addressing, the specified bit moves corresponding to the L register. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MBS specification.
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PD753104, 753106, 753108
7. INTERRUPT FUNCTION AND TEST FUNCTION
The PD753108 has eight types of interrupt sources and two types of test sources. Of these test sources, INT2 has two types of edge detection testable inputs. The interrupt control circuit of the PD753108 has the following functions. (1) Interrupt function * Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (IExxx) and interrupt master enable flag (IME). * Can set any interrupt start address. * Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). * Test function of interrupt request flag (IRQxxx). An interrupt generation can be checked by software. * Release the standby mode. An interrupt to be released can be selected by the interrupt enable flag. (2) Test function * Test request flag (IRQxxx) generation can be checked by software. * Release the standby mode. The test source to be released can be selected by the test enable flag.
38
Figure 7-1. Interrupt Control Circuit Block Diagram
Internal bus 4 IME IPS IM0 Decoder INTBT
VRQn
2 IST1 IST0 Interrupt enable flag (IExxx)
1
IM2
IM1
IRQBT IRQ4 IRQ0 IRQ1
INT4/P00 Edge detector
Both edge detector
INT0/P10
Note
Selector
INT1/P11 INTCSI INTT0 INTT1 INTT2 INTW
Selector
Edge detector IRQCSI IRQT0 IRQT1 IRQT2 IRQW IRQ2
Priority control circuit
Vector table address generator
INT2/P12
Rising edge detector
Standby release signal
KR0/P60
KR3/P63
Falling edge detector
IM2
Note Noise elimination circuit (Standby release is disabled when noise elimination circuit is selected.)
PD753104, 753106, 753108
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PD753104, 753106, 753108
8. STANDBY FUNCTION
In order to reduce power dissipation while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the PD753108. Table 8-1. Operation Status in Standby Mode
Item Set instruction System clock when set Mode STOP mode STOP instruction Settable only when the main system clock is used. Main system clock stops oscillation. HALT mode HALT instruction Settable both by the main system clock and subsystem clock. Only the CPU clock halts (oscillation continues). Operable only when the main system clock is oscillated. BT mode : IRQBT is set in the reference time interval WT mode : Reset signal is generated by BT overflow Operable only when an external SCK input is selected as the serial clock or when the main system clock is oscillated. Operable only when a signal input to the TI0 to TI2 pins is specified as the count clock or when the main system clock is oscillated. Operable.
Operation status
Clock generator
Basic interval timer/ watchdog timer
Operation stops.
Serial interface
Operable only when an external SCK input is selected as the serial clock.
Timer/event counter
Operable only when a signal input to the TI0 to TI2 pins is specified as the count clock.
Watch timer
Operable when fXT is selected as the count clock.
LCD controller/driver
Operable only when fXT is selected as the Operable. LCDCL. The INT1, 2, and 4 are operable. Only the INT0 is not operated Note. The operation stops. Interrupt request signal sent from the operable hardware enabled by the interrupt enable flag or RESET signal input.
External interrupt
CPU Release signal
Note
Can operate only when the noise elimination circuit is not used (IM02 = 1) by bit 2 of the edge detection mode register (IM0).
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PD753104, 753106, 753108
9. RESET FUNCTION
There are two reset inputs: external reset signal (RESET) and reset signal sent from the basic interval timer/ watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 91 shows the configuration of the above two inputs. Figure 9-1. Configuration of Reset Function
RESET
Internal reset signal
Reset signal sent from the basic interval timer/watchdog timer WDTM
Internal bus
Generation of the RESET signal initializes each hardware as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation
Wait Note
RESET signal generated Operation mode or standby mode HALT mode Internal reset operation Operation mode
Note
The following two times can be selected by the mask option. 217/fX (21.8 ms: @ 6.00-MHz operation, 31.3 ms: @ 4.19-MHz operation) 215/fX (5.46 ms: @ 6.00-MHz operation, 7.81 ms: @ 4.19-MHz operation)
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PD753104, 753106, 753108
Table 9-1. Status of Each Hardware After Reset (1/2)
RESET signal generation in the standby mode RESET signal generation in operation Sets the low-order 4 bits of program memory's address 0000H to the PC11-PC8 and the contents of address 0001H to the PC7-PC0. Sets the low-order 5 bits of program memory's address 0000H to the PC12-PC8 and the contents of address 0001H to the PC7-PC0. Undefined 0 0 Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Undefined Undefined 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0 FFH FFH
Hardware Program counter (PC)
PD753104
Sets the low-order 4 bits of program memory's address 0000H to the PC11-PC8 and the contents of address 0001H to the PC7-PC0.
PD753106, Sets the low-order 5 bits of PD753108 program memory's address 0000H to the PC12-PC8 and the contents of address 0001H to the PC7-PC0.
PSW Carry flag (CY) Skip flag (SK0 to SK2) Interrupt status flag (IST0, IST1) Bank enable flag (MBE, RBE) Held 0 0 Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Held Held 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0 FFH FFH
Stack pointer (SP) Stack bank select register (SBS) Data memory (RAM) General-purpose register (X, A, H, L, D, E, B, C) Bank select register (MBS, RBS) Basic interval timer/watchdog timer Timer/event counter (T0) Counter (BT) Mode register (BTM) Watchdog timer enable flag (WDTM) Counter (T0) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT F/F Timer/event counter (T1) Counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Timer/event counter (T2) Counter (T2) Modulo register (TMOD2) High-level period setting modulo register (TMOD2H) Mode register (TM2) TOE2, TOUT F/F REMC, NRZ, NRZB TGCE Watch timer Mode register (WM)
0 0, 0 0, 0, 0 0 0
0 0, 0 0, 0, 0 0 0
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PD753104, 753106, 753108
Table 9-1. Status of Each Hardware After Reset (2/2)
RESET signal generation in the standby mode Held 0 0 Held 0 0 0 0 0 0 0 Reset (0) 0 0 0, 0, 0 Off Cleared (0) 0 0 Held RESET signal generation in operation Undefined 0 0 Undefined 0 0 0 0 0 0 0 Reset (0) 0 0 0, 0, 0 Off Cleared (0) 0 0 Undefined
Hardware Serial interface Shift register (SIO) Operation mode register (CSIM) SBI control register (SBIC) Slave address register (SVA) Clock generator, clock output circuit Processor clock control register (PCC) System clock control register (SCC) Clock output mode register (CLOM)
Sub-oscillator control register (SOS) LCD controller/ driver Display mode register (LCDM) Display control register (LCDC) LCD/port selection register (LPS) Interrupt function Interrupt request flag (IRQxxx) Interrupt enable flag (IExxx) Interrupt priority selection register (IPS) INT0, 1, 2 mode registers (IM0, IM1, IM2) Digital port Output buffer Output latch I/O mode registers (PMGA, B, C) Pull-up resistor setting register (POGA, B) Bit sequential buffer (BSB0 to BSB3)
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PD753104, 753106, 753108
10. MASK OPTION
The PD753108 has the following mask options. P50-P53 mask options Selects whether or not to internally connect a pull-up resistor. <1> Connect pull-up resistor internally bit-wise. <2> Do not connect pull-up resistor internally. VLC0-VLC2 pins, BIAS pin mask option Selects whether or not to internally connect LCD-driving split resistors. <1> Do not connect split resistor internally. <2> Connect four 10-k (typ.) split resistors simultaneously internally. <3> Connect four 100-k (typ.) split resistors simultaneously internally. Standby function mask option Selects the wait time with the RESET signal. <1> 217/fx (21.8 ms: When fx = 6.0 MHz, 31.3 ms: When fx = 4.19 MHz) <2> 215/fx (5.46 ms: When fx = 6.0 MHz, 7.81 ms: When fx = 4.19 MHz) Subsystem clock mask option Selects whether or not to use an internal feedback resistor. <1> Use internal feedback resistor. (Switch internal feedback resistor ON/OFF by software) <2> Do not use internal feedback resistor. (Disconnect internal feedback resistor by hardware)
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PD753104, 753106, 753108
11. INSTRUCTION SET
(1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to "RA75X ASSEMBLER PACKAGE USERS' MANUAL----LANGUAGE (EEU-1363)". If there are several elements, one of them is selected. Capital letters and the + and - symbols are key words and are described as they are. For immediate data, appropriate numbers and labels are described. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the register flags can be described. However, there are restrictions in the labels that can be described for fmem and pmem. For details, see User's Manual.
Expression format reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, BC, XA, BC, BC, DE, DE BC, DE, DE, HL HL DE, HL, XA', BC', DE', HL' HL, XA', BC', DE', HL'
Description method
HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label 2-bit immediate data or label
Note
FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 0000H-0FFFH immediate data 0000H-17FFH immediate data 0000H-1FFFH immediate data 0000H-0FFFH immediate data 0000H-17FFH immediate data 0000H-1FFFH immediate data 12-bit immediate data or label 11-bit immediate data or label or or or or or or label label label label label label (PD753104) (PD753106) (PD753108) (PD753104) (PD753106) (PD753108)
addr1 (Mk II mode only) caddr faddr taddr PORTn IExxx RBn MBn
20H-7FH immediate data (where bit0 = 0) or label PORT0-PORT3, PORT5, PORT6, PORT8, PORT9 IEBT, IET0-IET2, IE0-IE2, IE4, IECSI, IEW RB0-RB3 MB0, MB1, MB15
Note mem can be only used for even address in 8-bit data processing.
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PD753104, 753106, 753108
(2) Legend in explanation of operation A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE PORTn IME IPS IExxx RBS MBS PCC . (xx) xxH : A register, 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : XA register pair; 8-bit accumulator : BC register pair : DE register pair : HL register pair : XA' expanded register pair : BC' expanded register pair : DE' expanded register pair : HL' expanded register pair : Program counter : Stack pointer : Carry flag, bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Port n (n = 0 to 3, 5, 6, 8, 9) : Interrupt master enable flag : Interrupt priority selection register : Interrupt enable flag : Register bank selection register : Memory bank selection register : Processor clock control register : Separation between address and bit : The contents addressed by xx : Hexadecimal data
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PD753104, 753106, 753108
(3) Explanation of symbols under addressing area column
*1 MB = MBE*MBS (MBS = 0, 1, 15) MB = 0 MBE = 0 : MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH
*2 *3
Data memory addressing
*4 *5 *6
PD753104 PD753106 PD753108
addr = 000H to FFFH addr = 0000H to 17FFH addr = 0000H to 1FFFH
*7
addr
= (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16
addr1 = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 *8
PD753104 PD753106 PD753108
caddr = 000H to FFFH caddr = 0000H to 0FFFH (PC12 = 0) or 1000H to 17FFH (PC12 = 1) caddr = 0000H to 0FFFH (PC12 = 0) or 1000H to 1FFFH (PC12 = 1) Program memory addressing
*9 *10 *11
faddr = 0000H to 07FFH taddr = 0020H to 007FH
PD753104 PD753106 PD753108
addr1 = 000H to FFFH addr1 = 0000H to 17FFH addr1 = 0000H to 1FFFH
Remarks 1. 2. 3. 4.
MB indicates memory bank that can be accessed. In *2, MB = 0 independently of how MBE and MBS are set. In *4 and *5, MB = 15 independently of how MBE and MBS are set. *6 to *11 indicate the areas that can be addressed.
47
PD753104, 753106, 753108
(4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. * When no skip is made: S = 0 * When the skipped instruction is a 1- or 2-byte instruction: S = 1 * When the skipped instruction is a 3-byte instruction Note: S = 2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types by setting PCC.
48
PD753104, 753106, 753108
Number of machine cycles 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 A <- n4 reg1 <- n4 XA <- n8 HL <- n8 rp2 <- n8 A <- (HL) A <- (HL), then L <- L+1 A <- (HL), then L <- L-1 A <- (rpa1) XA <- (HL) (HL) <- A (HL) <- XA A <- (mem) XA <- (mem) (mem) <- A (mem) <- XA A <- reg XA <- rp' reg1 <- A rp'1 <- XA A <-> (HL) A <-> (HL), then L <- L+1 A <-> (HL), then L <- L-1 A <-> (rpa1) XA <-> (HL) A <-> (mem) XA <-> (mem) A <-> reg1 XA <-> rp' *1 *1 *1 *2 *1 *3 *3 L=0 L = FH *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH String effect A String effect B
Instruction group Transfer
Mnemonic
Operand
Number of bytes 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2
Operation
Addressing area
Skip condition
MOV
A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA
String effect A
XCH
A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp'
49
PD753104, 753106, 753108
Number of machine cycles 3
Instruction group Table reference
Mnemonic
Operand
Number of bytes 1
Operation
Addressing area
Skip condition
MOVT
XA, @PCDE
PD753104 XA <- (PC11-8+DE)ROM PD753106, 753108 XA <- (PC12-8+DE)ROM
XA, @PCXA
1
3
PD753104 XA <- (PC11-8+XA)ROM PD753106, 753108 XA <- (PC12-8+XA)ROM
XA, @BCDE XA, @BCXA Bit transfer MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY Operation ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' rp'1, XA SUBC A, @HL XA, rp' rp'1, XA
1 1 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2
3 3 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2
XA <- (BCDE)ROM XA <- (BCXA)ROM CY <- (fmem.bit)
Note
*6 *6 *4 *5 *1 *4 *5 *1 carry carry *1 carry carry carry *1
Note
CY <- (pmem7-2+L3-2.bit(L1-0)) CY <- (H+mem3-0.bit) (fmem.bit) <- CY (pmem7-2+L3-2.bit(L1-0)) <- CY (H+mem3-0.bit) <- CY A <- A+n4 XA <- XA+n8 A <- A+(HL) XA <- XA+rp' rp'1 <- rp'1+XA A, CY <- A+(HL)+CY XA, CY <- XA+rp'+CY rp'1, CY <- rp'1+XA+CY A <- A-(HL) XA <- XA-rp' rp'1 <- rp'1-XA A, CY <- A-(HL)-CY XA, CY <- XA-rp'-CY rp'1, CY <- rp'1-XA-CY
*1
borrow borrow borrow
*1
Note
Set "0" in B register if the PD753104 is used. Only low-order one bit of B register will be valid if the
PD753106 or 753108 is used.
50
PD753104, 753106, 753108
Number of machine cycles 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 A <- A n4 A <- A (HL) XA <- XA rp' rp'1 <- rp'1 XA A <- A n4 A <- A (HL) XA <- XA rp' rp'1 <- rp'1 XA A <- A v n4 A <- A v (HL) XA <- XA v rp' rp'1 <- rp'1 v XA CY <- A0, A3 <- CY, An-1 <- An A <- A reg <- reg+1 rp1 <- rp1+1 (HL) <- (HL)+1 (mem) <- (mem)+1 reg <- reg-1 rp' <- rp'-1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY <- 1 CY <- 0 Skip if CY = 1 CY <- CY CY = 1 *1 *1 *1 *1 *3 reg = 0 rp1 = 00H (HL) = 0 (mem) = 0 reg = FH rp' = FFH reg = n4 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp' *1 *1 *1
Instruction group Operation
Mnemonic
Operand
Number of bytes 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1
Operation
Addressing area
Skip condition
AND
A, #n4 A, @HL XA, rp' rp'1, XA
OR
A, #n4 A, @HL XA, rp' rp'1, XA
XOR
A, #n4 A, @HL XA, rp' rp'1, XA
Accumulator manipulation
RORC NOT
A A reg rp1 @HL mem
Increment and decrement
INCS
DECS
reg rp'
Comparison
SKE
reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp'
Carry flag manipulation
SET1 CLR1 SKT NOT1
CY CY CY CY
51
PD753104, 753106, 753108
Number of machine cycles 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 (mem.bit) <- 1 (fmem.bit) <- 1 (pmem7-2+L3-2.bit(L1-0)) <- 1 (H+mem3-0.bit) <- 1 (mem.bit) <- 0 (fmem.bit) <- 0 (pmem7-2+L3-2.bit(L1-0)) <- 0 (H+mem3-0.bit) <- 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7-2+L3-2.bit(L1-0)) = 1 Skip if (H+mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2+L3-2.bit(L1-0)) = 0 Skip if (H+mem3-0.bit) = 0 Skip if (fmem.bit) = 1 and clear Skip if (pmem7-2+L3-2.bit(L1-0)) = 1 and clear Skip if (H+mem3-0.bit) = 1 and clear CY <- CY (fmem.bit) CY <- CY (pmem7-2+L3-2.bit(L1-0)) CY <- CY (H+mem3-0.bit) CY <- CY (fmem.bit) CY <- CY (pmem7-2+L3-2.bit(L1-0)) CY <- CY (H+mem3-0.bit) CY <- CY v (fmem.bit) CY <- CY v (pmem7-2+L3-2.bit(L1-0)) CY <- CY v (H+mem3-0.bit)
Instruction group Memory bit manipulation
Mnemonic
Operand
Number of bytes 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Operation
Addressing area *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1
Skip condition
SET1
mem.bit fmem.bit pmem.@L @H+mem.bit
CLR1
mem.bit fmem.bit pmem.@L @H+mem.bit
SKT
mem.bit fmem.bit pmem.@L @H+mem.bit
(mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H+mem.bit) = 0 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1
SKF
mem.bit fmem.bit pmem.@L @H+mem.bit
SKTCLR
fmem.bit pmem.@L @H+mem.bit
AND1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
OR1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
XOR1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
52
PD753104, 753106, 753108
Number of machine cycles -
Instruction group Branch
Mnemonic
Operand
Number of bytes -
Operation
Addressing area *6
Skip condition
BR Note
addr
PD753104 PC11-0 <- addr Select appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used. PD753106, 753108 PC12-0 <- addr Select appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used.
addr1
-
-
PD753104 PC11-0 <- addr1 Select appropriate instruction from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. PD753106, 753108 PC12-0 <- addr1 Select appropriate instruction from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used.
*11
!addr
3
3
PD753104 PC11-0 <- addr PD753106, 753108 PC12-0 <- addr
*6
$addr
1
2
PD753104 PC11-0 <- addr PD753106, 753108 PC12-0 <- addr
*7
$addr1
1
2
PD753104 PC11-0 <- addr1 PD753106, 753108 PC12-0 <- addr1
Note
The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode.
53
PD753104, 753106, 753108
Number of machine cycles 3
Instruction group Branch
Mnemonic
Operand
Number of bytes 2
Operation
Addressing area
Skip condition
BR
PCDE
PD753104 PC11-0 <- PC11-8+DE PD753106, 753108 PC12-0 <- PC12-8+DE
PCXA
2
3
PD753104 PC11-0 <- PC11-8+XA PD753106, 753108 PC12-0 <- PC12-8+XA
BCDE
2
3
PD753104 PC11-0 <- BCDE Note 1 PD753106, 753108 PC12-0 <- BCDE Note 2
*6
BCXA
2
3
PD753104 PC11-0 <- BCXA Note 1 PD753106, 753108 PC12-0 <- BCXA Note 2
*6
BRA
Note 3
!addr1
3
3
PD753104 PC11-0 <- addr1 PD753106, 753108 PC12-0 <- addr1
*11
BRCB
!caddr
2
2
PD753104 PC11-0 <- caddr11-0 PD753106, 753108 PC12-0 <- PC12+caddr11-0
*8
Subroutine stack control
CALLA
Note 3
!addr1
3
3
PD753104 (SP-2) <- x, x, MBE, RBE (SP-6) (SP-3) (SP-4) <- PC11-0 (SP-5) <- 0, 0, 0, 0 PC11-0 <- addr1, SP <- SP-6 PD753106, 753108 (SP-2) <- x, x, MBE, RBE (SP-6) (SP-3) (SP-4) <- PC11-0 (SP-5) <- 0, 0, 0, PC12 PC12-0 <- addr1, SP <- SP-6
*11
Notes 1. 2. 3.
"0" must be set to B register. Only low-order one bit is valid in B register. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode.
54
PD753104, 753106, 753108
Number of machine cycles 3
Instruction group Subroutine stack control
Mnemonic
Operand
Number of bytes 3
Operation
Addressing area *6
Skip condition
CALL Note
!addr
PD753104 (SP-3) <- MBE, RBE, 0, 0 (SP-4) (SP-1) (SP-2) <- PC11-0 PC11-0 <- addr, SP <- SP-4 PD753106, 753108 (SP-3) <- MBE, RBE, 0, PC12 (SP-4) (SP-1) (SP-2) <- PC11-0 PC12-0 <- addr, SP <- SP-4
4
PD753104 (SP-2) <- x, x, MBE, RBE (SP-6) (SP-3) (SP-4) <- PC11-0 (SP-5) <- 0, 0, 0, 0 PC11-0 <- addr, SP <- SP-6 PD753106, 753108 (SP-2) <- x, x, MBE, RBE (SP-6) (SP-3) (SP-4) <- PC11-0 (SP-5) <- 0, 0, 0, PC12 PC12-0 <- addr, SP <- SP-6
CALLF Note
!faddr
2
2
PD753104 (SP-3) <- MBE, RBE, 0, 0 (SP-4) (SP-1) (SP-2) <- PC11-0 PC11-0 <- 0+faddr, SP <- SP-4 PD753106, 753108 (SP-3) <- MBE, RBE, 0, PC12 (SP-4) (SP-1) (SP-2) <- PC11-0 PC12-0 <- 00+faddr, SP <- SP-4
*9
3
PD753104 (SP-2) <- x, x, MBE, RBE (SP-6) (SP-3) (SP-4) <- PC11-0 (SP-5) <- 0, 0, 0, 0 PC11-0 <- 0+faddr, SP <- SP-6 PD753106, 753108 (SP-2) <- x, x, MBE, RBE (SP-6) (SP-3) (SP-4) <- PC11-0 (SP-5) <- 0, 0, 0, PC12 PC12-0 <- 00+faddr, SP <- SP-6
Note
The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode.
55
PD753104, 753106, 753108
Number of machine cycles 3
Instruction group Subroutine stack control
Mnemonic
Operand
Number of bytes 1
Operation
Addressing area
Skip condition
RET Note
PD753104 PC11-0 <- (SP) (SP+3) (SP+2) MBE, RBE, 0, 0 <- (SP+1), SP <- SP+4 PD753106, 753108 PC11-0 <- (SP) (SP+3) (SP+2) MBE, RBE, 0, PC12 <- (SP+1), SP <- SP+4 PD753104 x, x, MBE, RBE <- (SP+4) 0, 0, 0, 0, <- (SP+1) PC11-0 <- (SP) (SP+3) (SP+2), SP <- SP+6 PD753106, 753108 x, x, MBE, RBE <- (SP+4) MBE, 0, 0, PC12 <- (SP+1) PC11-0 <- (SP) (SP+3) (SP+2), SP <- SP+6
RETS Note
1
3+S
PD753104 MBE, RBE, 0, 0 <- (SP+1) PC11-0 <- (SP) (SP+3) (SP+2) SP <- SP+4 then skip unconditionally PD753106, 753108 MBE, RBE, 0, PC12 <- (SP+1) PC11-0 <- (SP) (SP+3) (SP+2) SP <- SP+4 then skip unconditionally PD753104 0, 0, 0, 0 <- (SP+1) PC11-0 <- (SP) (SP+3) (SP+2) x, x, MBE, RBE <- (SP+4) SP <- SP+6 then skip unconditionally PD753106, 753108 0, 0, 0, PC12 <- (SP+1) PC11-0 <- (SP) (SP+3) (SP+2) x, x, MBE, RBE <- (SP+4) SP <- SP+4 then skip unconditionally
Unconditional
Note
The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode.
56
PD753104, 753106, 753108
Number of machine cycles 3
Instruction group Subroutine stack control
Mnemonic
Operand
Number of bytes 1
Operation
Addressing area
Skip condition
RETI Note 1
PD753104 MBE, RBE, 0, 0 <- (SP+1) PC11-0 <- (SP) (SP+3) (SP+2) PSW <- (SP+4) (SP+5), SP <- SP+6 PD753106, 753108 MBE, RBE, 0, PC12 <- (SP+1) PC11-0 <- (SP) (SP+3) (SP+2) PSW <- (SP+4) (SP+5), SP <- SP+6 PD753104 0, 0, 0, 0 <- (SP+1) PC11-0 <- (SP) (SP+3) (SP+2) PSW <- (SP+4) (SP+5), SP <- SP+6 PD753106, 753108 0, 0, 0, PC12 <- (SP+1) PC11-0 <- (SP) (SP+3) (SP+2) PSW <- (SP+4) (SP+5), SP <- SP+6
PUSH
rp BS
1 2 1 2 2
1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2
(SP-1) (SP-2) <- rp, SP <- SP-2 (SP-1) <- MBS, (SP-2) <- RBS, SP <- SP-2 rp <- (SP+1) (SP), SP <- SP+2 MBS <- (SP+1), RBS <- (SP), SP <- SP+2 IME (IPS.3) <- 1 IExxx <- 1 IME (IPS.3) <- 0 IExxx <- 0 A <- PORTn XA <- PORTn+1, PORTn PORTn <- A PORTn+1, PORTn <- XA Set HALT Mode (PCC.2 <- 1) Set STOP Mode (PCC.3 <- 1) No Operation RBS <- n MBS <- n (n = 0-3) (n = 0, 1, 15) (n = 0-3, 5, 6, 8, 9) (n = 8) (n = 3, 5, 6, 8, 9) (n = 8)
POP
rp BS
Interrupt control
EI IExxx DI IExxx
2 2 2 2 2 2 2 2 2 1
Input/output
IN Note 2
A, PORTn XA, PORTn
OUT Note 2
PORTn, A PORTn, XA
CPU control
HALT STOP NOP
Special
SEL
RBn MBn
2 2
Notes 1. 2.
The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1, and MBS must be set to 15.
57
PD753104, 753106, 753108
Instruction group Special Number of bytes 1 Number of machine cycles 3 Addressing area *10
Mnemonic
Operand
Operation
Skip condition
GETI Note 1, 2
taddr
PD753104 * When TBR instruction PC11-0 <- (taddr) 3-0 + (taddr+1)
----------------------------------
-------------
* When TCALL instruction (SP-4) (SP-1) (SP-2) <- PC11-0 (SP-3) <- MBE, RBE, 0, 0 PC11-0 <- (taddr) 3-0 + (taddr+1) SP <- SP-4
---------------------------------- -------------
* When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed.
Depending on the reference instruction
PD753106, 753108 * When TBR instruction PC12-0 <- (taddr) 4-0 + (taddr+1)
---------------------------------- -------------
* When TCALL instruction (SP-4) (SP-1) (SP-2) <- PC11-0 (SP-3) <- MBE, RBE, 0, PC12 PC12-0 <- (taddr) 4-0 + (taddr+1) SP <- SP-4
---------------------------------- -------------
* When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. 3
Depending on the reference instruction *10
PD753104 * When TBR instruction PC11-0 <- (taddr) 3-0 + (taddr+1)
* When TCALL instruction (SP-6) (SP-3) (SP-4) <- PC11-0 (SP-5) <- 0, 0, 0, 0 (SP-2) <- x, x, MBE, RBE PC11-0 <- (taddr) 3-0 + (taddr+1) SP <- SP-6
------------------------------------- ----
-------------
4
------------------------------------- ----
-------------
3
* When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed.
Depending on the reference instruction
3
PD753106, 753108 * When TBR instruction PC12-0 <- (taddr) 4-0 + (taddr+1)
-------------
------------------------------------- ----
4
* When TCALL instruction (SP-6) (SP-3) (SP-4) <- PC11-0 (SP-5) <- 0, 0, 0, PC12 (SP-2) <- x, x, MBE, RBE PC12-0 <- (taddr) 4-0 + (taddr+1) SP <- SP-6
-------------
------------------------------------- ----
3
* When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed.
Depending on the reference instruction
Notes 1. 2.
The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode.
58
PD753104, 753106, 753108
12. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 C)
Parameter Supply voltage Input voltage Symbol VDD VI1 VI2 Except port 5 Port 5 On-chip pull-up resistor When N-ch open-drain Output voltage Output current high VO IOH Per pin Total of all pins Output current low IOL Per pin Total of all pins Operating ambient temperature Storage temperature TA Test Conditions Rating -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +14 -0.3 to VDD + 0.3 -10 -30 30 220 -40 to +85
Note
Unit V V V V V mA mA mA mA C
Tstg
-65 to +150
C
Note
When LCD is driven in normal mode: TA = -10 to +85 C
Caution Exposure to Absolute Maximum Ratings even for instant may affect device reliability; exceeding the ratings could cause parmanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC Characteristics. CAPACITANCE (TA = 25 C, VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Test Conditions f = 1 MHz Unmeasured pins returned to 0 V. MIN. TYP. MAX. 15 15 15 Unit pF pF pF
59
PD753104, 753106, 753108
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Resonator Ceramic resonator
C1 VDD C2
Recommended constant
X1 X2
Parameter Oscillation frequency (fx) Oscillation stabilization time Note 3
Note 1
Test conditions
MIN. 1.0
TYP.
MAX. 6.0
Note 2
Unit MHz
After VDD reaches oscillation voltage range MIN. 1.0
Note 1
4
ms
Crystal resonator
C1
X1
X2
Oscillation frequency (fx)
C2
6.0
Note 2
MHz
Oscillation stabilization time Note 3 X1 input
VDD = 4.5 to 5.5 V
10 30 1.0 6.0
Note 2
ms
VDD
External clock X1 X2
MHz
frequency (fx)
Note 1
X1 input high/low-level width (tXH, tXL)
83.3
500
ns
Notes 1. 2.
The oscillation frequency and X1 input frequency indicate characteristics of the oscillator only. For the instruction execution time, refer to the AC characteristics. When the oscillation frequency is 4.19 MHz < fx 6.0 MHz at 1.8 V VDD < 2.7 V, setting the processor clock control register (PCC) to 0011 results in 1 machine cycle time being less than the required 0.95
s. Therefore, set PCC to a value other than 0011.
3. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing the STOP mode. Caution When using the main system clock oscillator, wiring in the area enclosed with the dotted line in the above figure should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VDD. * Do not ground to the ground pattern in which a high current flows. * Do not fetch a signal from the oscillator.
60
PD753104, 753106, 753108
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Resonator Crystal resonator
C3 VDD
Recommended constant
XT1 XT2 R C4
Parameter Oscillation frequency (fXT) Oscillation stabilization time Note 2 XT1 input frequency
Note 1
Test conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
VDD = 4.5 to 5.5 V
1.0
2 10
s
External XT1 clock XT2
32
100
kHz
(fXT)
Note 1
X1 input high/low-level width (tXTH, tXTL)
5
15
s
Notes 1. 2. Caution
Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD. When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line in the above figure should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VDD. * Do not ground to the ground pattern in which a high current flows. * Do not fetch a signal from the oscillator. The subsystem clock oscillator is designed as a low amplification circuit to provide low consumption current, causing misoperation by noise more frequently than the main system clock oscillator. Special care should therefore be taken for wiring method when the subsystem clock is used.
61
PD753104, 753106, 753108
RECOMMENDED OSCILLATOR CONSTANT Ceramic Resonator (TA = -20 to +85 C)
Manufacturer Product name Frequency Oscillator constant (pF) C1 100 82 33 -- C2 100 82 33 -- Oscillation voltage range (VDD) MIN. 1.8 2.2 1.8 On-chip capacitor product -- -- On-chip capacitor product -- -- On-chip capacitor product -- -- On-chip capacitor product MAX. 5.5 -- Remarks
(MHz) Kyocera Corporation KBR-1000F/Y KBR-2.0MS KBR-4.19MSA KBR-4.19MKS 1.0 2.0 4.19
PBRC 4.19A PBRC 4.19B
33 --
33
KBR-6.0MSA KBR-6.0MKS
6.0
33 --
33
PBRC 6.00A PBRC 6.00B
33 --
33
Ceramic Resonator (TA = -40 to +85 C)
Manufacturer Product name Frequency Oscillator constant (pF) C1 150 -- C2 150 -- Oscillation voltage range (VDD) MIN. 2.3 2.0 MAX. 5.5 -- On-chip capacitor product Remarks
(MHz) TDK CCR1000K2 CCR2.0MC33 FCR4.19MC5 CCR4.19MC3 FCR6.0MC5 CCR6.0MC3 6.0 1.0 2.0 4.19
2.2
62
PD753104, 753106, 753108
Ceramic Resonator (TA = -20 to +80 C)
Manufacturer Product name Frequency Oscillator constant (pF) C1 100 30 -- 3.0 30 -- 4.19 30 -- 5.0 30 30 30 -- 2.2 1.8 -- -- 2.2 1.8 6.0 30 30 2.5 1.8 -- -- 2.5 1.8 On-chip capacitor product -- On-chip capacitor product 30 -- C2 100 30 -- Oscillation voltage range (VDD) MIN. 2.4 1.8 MAX. 5.5 Rd = 5.6 k -- On-chip capacitor product -- On-chip capacitor product -- On-chip capacitor product --
Note
Remarks
(MHz) Murata Mfg. Co., Ltd. CSB1000J CSA2.00MG CST2.00MGW CSA3.00MG CST3.00MGW CSA4.19MG CST4.19MGW CSA5.00MG CSA5.00MGU CST5.00MGW CST5.00MGWU CSA6.00MG CSA6.00MGU CST6.00MGW CST6.00MGWU 1.0 2.0
Note
If using the CSB1000J (1.0-MHz) ceramic resonator manufactured by Murata Mfg. Co., Ltd., a limiting resistor (Rd = 5.6 k) is required (see figure below). A limiting resistor is not required if using the other recommended resonators.
Recommended Main System Clock Circuit Example (using Murata Mfg. Co., Ltd. CSB1000J)
X1 CSB1000J
X2 Rd
C1
C2
VDD
63
PD753104, 753106, 753108
Crystal Resonator
Manufacturer Product name Frequency Oscillator constant (pF) C1 15 15 C2 Oscillation voltage range (VDD) MIN. 1.8 MAX. 5.5 TA = -20 to +70 C Remarks
(MHz) Kinseki HC-49/U 2.0 4.19 6.0 HC-49/U-S 4.19 6.0
2.5 1.8 2.5
5.5 5.5 5.5 TA = -10 to +70 C
Caution The oscillator constant and the oscillation voltage range represent conditions for stable oscillation, but do not guarantee an accurate oscillation frequency. For an application circuit requiring an accurate oscillation frequency, it may be necessary to adjust the oscillation frequency of the resonator in the application circuit, in which case inquiries should be directed to the manufacturer of the resonator.
64
PD753104, 753106, 753108
DC CHARACTERISTICS (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Parameter Output current low Symbol IOL Per pin Total of all pins Input voltage high VIH1 Ports 2, 3, 8, 9 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIH2 Ports 0, 1, 6, RESET 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIH3 Port 5 On-chip pull-up resistor When N-ch open-drain VIH4 Input voltage low VIL1 X1, XT1 Ports 2, 3, 5, 8, 9 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIL2 Ports 0, 1, 6, RESET 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIL3 Output voltage high Output voltage low VOH VOL1 X1, XT1 SCK, SO, ports 2, 3, 6, 8, 9 IOH = -1.0 mA SCK, SO, ports 2, 3, 5, 6, 8, 9 IOL = 15 mA, VDD = 4.5 to 5.5 V IOL = 1.6 mA VOL2 SB0, SB1 N-ch open-drain pull-up resistor 1 k Pins other than X1, XT1 X1, XT1 VIN = 13 V VIN = 0 V Port 5 (When N-ch open-drain) Pins other than X1, XT1, port 5 X1, XT1 Port 5 (When N-ch open-drain) When input instruction is not executed Port 5 (When N-ch open-drain) When input VDD = 5.0 V instruction is executed VDD = 3.0 V Output leakage current high ILOH1 VOUT = VDD SCK, SO/SB0, SB1, ports 2, 3, 6, 8, 9, port 5 (When N-ch open-drain) Port 5 (When N-ch open-drain) 0.4 0.2VDD V V 2.7 VDD 5.5 V 1.8 VDD < 2.7 V 2.7 VDD 5.5 V 1.8 VDD < 2.7 V 0.7VDD 0.9VDD 0.8VDD 0.9VDD 0.7VDD 0.9VDD 0.7VDD 0.9VDD VDD-0.1 0 0 0 0 0 VDD-0.5 0.2 2.0 Test conditions MIN. TYP. MAX. 15 150 VDD VDD VDD VDD VDD VDD 13 13 VDD 0.3VDD 0.1VDD 0.2VDD 0.1VDD 0.1 Unit mA mA V V V V V V V V V V V V V V V V
Input leakage current high
ILIH1 ILIH2 ILIH3
VIN = VDD
3 20 20 -3 -20 -3
A A A A A A
A A A
Input leakage current low
ILIL1 ILIL2 ILIL3
-10 -3
-30 -27 -8 3
A A A
ILOH2 Output leakage current low On-chip pull-up resistor ILOL
VOUT = 13 V VOUT = 0 V
20 -3
RL1
VIN = 0 V
Ports 0 to 3, 6, 8, 9 (Excluding P00 pin) Port 5 (mask option)
50
100
200
k
RL2
15
30
60
k
65
PD753104, 753106, 753108
DC CHARACTERISTICS (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Parameter LCD drive voltage Symbol VLCD VAC0 = 0 Test conditions TA = -40 to +85 C TA = -10 to +85 C VAC0 = 1 VAC current
Note 1 Note 2
MIN. 2.7 2.2 1.8
TYP.
MAX. VDD VDD VDD
Unit V V V
IVAC RLCD1 RLCD2
VAC0 = 1, VDD = 2.0 V 10% 50 5 IO = 1.0 A VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 1.8 V VLCD VDD VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 2.2 V VLCD VDD VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 1.8 V VLCD VDD VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 2.2 V VLCD VDD VDD = 5.0 V 10%
Note 6 Note 7
1 100 10
4 200 20 0.2
A
k k V
LCD split resistor
LCD output voltage VODC deviation Note 3 (common)
0
IO = 5.0 A
0
0.2
V
LCD output voltage VODS deviation Note 3 (segment)
IO = 0.5 A
0
0.2
V
IO = 1.0 A
0
0.2
V
Supply current Note 4
IDD1
6.0 MHz Note 5
1.9 0.4 0.72 0.27 1.5 0.25 0.7 0.23 12 4.5 12 6.0 6.0 8.5 3.0 8.5 3.5 3.5 0.05 0.02
6.0 1.3 2.1 0.8 4.0 0.75 2.0 0.7 35.0 12.0 24.0 18.0 12.0 25 9.0 17 12 7.0 10 5.0 3.0
mA mA mA mA mA mA mA mA
Crystal oscillation VDD = 3.0 V 10% IDD2 C1 = C2 = 22 pF
HALT mode VDD = 5.0 V 10% VDD = 3.0 V 10%
IDD1
4.19 MHz Note 5
VDD = 5.0 V 10% Note 6
Crystal oscillation VDD = 3.0 V 10% Note 7 IDD2 C1 = C2 = 22 pF HALT mode VDD = 5.0 V 10% VDD = 3.0 V 10% IDD3 32.768 kHz Note 8 Low-voltage VDD = 3.0 V 10% Crystal oscillation mode
Note 9
A A A A A A A A A A A A A
VDD = 2.0 V 10% VDD = 3.0 V, TA = 25 C
Low current consump- VDD = 3.0 V 10% tion mode Note 10 IDD4 VDD = 3.0 V, TA = 25 C VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 3.0 V, TA = 25 C
HALT mode Lowvoltage mode
Note 9
Low current VDD = 3.0 V 10% consumption mode Note 10 VDD = 3.0 V, TA = 25 C IDD5 XT1 = 0 V
Note 11
VDD = 5.0 V 10% VDD = 3.0 V 10% TA = 25 C
STOP mode
0.02
66
PD753104, 753106, 753108
Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Clear VAC0 to 0 in the low current consumption mode and STOP mode. When VAC0 is set to 1, the current increases by about 1 A. Either RLCD1 or RLCD2 can be selected by the mask option. The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2). Not including currents flowing in on-chip pull-up resistors or LCD split resistors. Including oscillation of the subsystem clock. When the processor clock control register (PCC) is set to 0011 and the device is operated in the highspeed mode. When PCC is set to 0000 and the device is operated in the low-speed mode. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem clock, with main system clock oscillation stopped. When the sub-oscillator control register (SOS) is set to 0000. When the SOS is set to 0010. When the SOS is set to 00x1, and the sub-oscillator feedback resistor is not used (x : don't care).
67
PD753104, 753106, 753108
AC CHARACTERISTICS (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Parameter CPU clock cycle time
Note 1
Symbol tCY Operating on main system clock
Test conditions VDD = 2.7 to 5.5 V
MIN. 0.67 0.95 114
TYP.
MAX. 64 64
Unit
s s s
(minimum instruction execution time = 1 machine cycle) TI0, TI1, TI2 input frequency TI0, TI1, TI2 input high/low-level width Interrupt input high/ low-level width tTIH, tTIL fTI
Operating on subsystem clock
122
125
VDD = 2.7 to 5.5 V
0 0
1.0 275
MHz kHz
VDD = 2.7 to 5.5 V
0.48 1.8
s s s s s s s
tINTH, tINTL INT0
IM02 = 0 IM02 = 1
Note 2 10 10 10 10
INT1, 2, 4 KR0-KR3 RESET low-level width tRSL
Notes 1.
The cycle time (minimum instruction execution time) of the CPU clock () is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (SCC) and the processor clock control register (PCC). The figure at the right indicates the cycle time tCY versus supply voltage VDD characteristic with the main system clock operating.
Cycle Time tCY [s] 6 5 4 3 64 60
tCY vs VDD (At main system clock operation)
Operation Guaranteed Range
2
2.
2tCY or 128/fx is set by setting the interrupt mode register (IM0).
1
0.5 0 1 2 3 4 5 6 Supply Voltage VDD [V]
68
PD753104, 753106, 753108
SERIAL TRANSFER OPERATION 2-Wire and 3-Wire Serial I/O Modes (SCK...Internal clock output): (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY1 VDD = 2.7 to 5.5 V Test conditions MIN. 1300 3800 SCK high/low-level width SI
Note 1
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
tKL1, tKH1
VDD = 2.7 to 5.5 V
tKCY1/2-50 tKCY1/2-150
setup time
tSIK1
VDD = 2.7 to 5.5 V
150 500
(to SCK) SI
Note 1
hold time
tKSI1
VDD = 2.7 to 5.5 V
400 600
(from SCK) SO
Note 1
output delay time
tKSO1
RL = 1 k, CL = 100 pF
Note 2
VDD = 2.7 to 5.5 V
0 0
250 1000
ns ns
from SCK
Notes 1. 2.
Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and CL are the load resistance and load capacitance of the SO output line.
2-Wire and 3-Wire Serial I/O Modes (SCK...External clock input): (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY2 VDD = 2.7 to 5.5 V Test conditions MIN. 800 3200 SCK high/low-level width SI
Note 1
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
tKL2, tKH2
VDD = 2.7 to 5.5 V
400 1600
setup time
tSIK2
VDD = 2.7 to 5.5 V
100 150
(to SCK) SI
Note 1
hold time
tKSI2
VDD = 2.7 to 5.5 V
400 600
(from SCK) SO
Note 1
output delay time
tKSO2
RL = 1 k, CL = 100 pF
Note 2
VDD = 2.7 to 5.5 V
0 0
300 1000
ns ns
from SCK
Notes 1. 2.
Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and CL are the load resistance and load capacitance of the SO output line.
69
PD753104, 753106, 753108
SBI Mode (SCK...Internal clock output (master)): (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY3 VDD = 2.7 to 5.5 V Test conditions MIN. 1300 3800 SCK high/low-level width SB0, 1 setup time (to SCK) SB0, 1 hold time (from SCK) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSI3 tKSO3 RL = 1 k, CL = 100 pF
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns
tKL3, tKH3
VDD = 2.7 to 5.5 V
tKCY3/2-50 tKCY3/2-150
tSIK3
VDD = 2.7 to 5.5 V
150 500 tKCY3/2 VDD = 2.7 to 5.5 V 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000
ns ns ns ns ns ns
Note
RL and CL are the load resistance and load capacitance of the SB0, 1 output line.
SBI Mode (SCK...External clock input (slave)): (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY4 VDD = 2.7 to 5.5 V Test conditions MIN. 800 3200 SCK high/low-level width SB0, 1 setup time (to SCK) SB0, 1 hold time (from SCK) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSI4 tKSO4 RL = 1 k, CL = 100 pF
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns
tKL4, tKH4
VDD = 2.7 to 5.5 V
400 1600
tSIK4
VDD = 2.7 to 5.5 V
100 150 tKCY4/2 VDD = 2.7 to 5.5 V 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000
ns ns ns ns ns ns
Note
RL and CL are the load resistance and load capacitance of the SB0, 1 output line.
70
PD753104, 753106, 753108
AC Timing Test Point (Excluding X1, XT1 inputs)
VIH (MIN.) VIL (MAX.)
VIH (MIN.) VIL (MAX.)
VOH (MIN.) VOL (MAX.)
VOH (MIN.) VOL (MAX.)
Clock Timing
1/fX tXL tXH
X1 Input
VDD-0.1 V 0.1 V
1/fXT tXTL tXTH
XT1 Input
VDD-0.1 V 0.1 V
TI0, TI1, TI2 Timing
1/fTI tTIL tTIH
TI0, TI1, TI2
71
PD753104, 753106, 753108
Serial Transfer Timing 3-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK tSIK1, 2 tKSI1, 2
SI tKSO1, 2
Input Data
SO
Output Data
2-wire serial I/O mode
tKCY1, 2 tKL1, 2 tKH1, 2
SCK tSIK1, 2 tKSI1, 2
SB0, 1
tKSO1, 2
72
PD753104, 753106, 753108
Serial Transfer Timing Bus release signal transfer
tKCY3, 4 tKL3, 4 SCK tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 tKH3, 4
SB0, 1 tKSO3, 4
Command signal transfer
tKCY3, 4 tKL3, 4 SCK tKSB tSBK tSIK3, 4 tKSI3, 4 tKH3, 4
SB0, 1
tKSO3, 4
Interrupt input timing
tINTL
tINTH
INT0, 1, 2, 4 KR0 to 3
RESET input timing
tRSL
RESET
73
PD753104, 753106, 753108
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = -40 to +85 C)
Parameter Release signal set time Oscillation stabilization wait time Note 1 Symbol tSREL tWAIT Release by RESET Release by interrupt request Test conditions MIN. 0 Note 2 Note 3 TYP. MAX. Unit
s
ms ms
Notes 1. 2. 3.
The oscillation stabillization wait time is the time during which the CPU operation is stopped to prevent unstable operation at the oscillation start. Either 2 17/fX or 215/fX can be selected by the mask option. Depends on the basic interval timer mode register (BTM) settings (see the table below).
BTM3 -- -- -- -- BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 220/fx 217/fx 215/fx 213/fx fx = at 4.19 MHz (approx. 250 ms) (approx. 31.3 ms) (approx. 7.81 ms) (approx. 1.95 ms) Wait time 220/fx 217/fx 215/fx 213/fx fx = at 6.0 MHz (approx. 175 ms) (approx. 21.8 ms) (approx. 5.46 ms) (approx. 1.37 ms)
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retention Mode
VDD tSREL STOP Instruction Execution RESET tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode STOP Mode Operating Mode
Data Retention Mode
VDD tSREL STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT
74
PD753104, 753106, 753108
13. CHARACTERISTIC CURVES (FOR REFERENCE ONLY)
IDD vs VDD (Main System Clock: 6.0-MHz Crystal Resonator)
(TA = 25 C) 10
5.0
PCC = 0011 PCC = 0010 1.0 PCC = 0001 PCC = 0000 0.5 Main system clock HALT mode + 32-kHz oscillation
Supply Current IDD (mA)
0.1
Subsystem clock operation mode (SOS.1 = 0)
0.05 Main system clock STOP mode + 32-kHz oscillation (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 0) Main system clock STOP mode + 32-kHz oscillation (SOS.1 = 1) and subsystem clock HALT mode (SOS.1 = 1)
0.01
0.005
X1
Crystal resonator
X2 XT1
6.0 MHz
XT2 330 k 22 pF
32.768 kHz
Crystal resonator
22 pF
22 pF VDD
22 pF VDD 6
0.001
0
1
2
3
4 Supply Voltage VDD (V)
5
7
8
75
PD753104, 753106, 753108
IDD vs VDD (Main System Clock: 4.19-MHz Crystal Resonator)
10 (TA = 25 C)
5.0
PCC = 0011 1.0 PCC = 0010 PCC = 0001 PCC = 0000 0.5 Main system clock HALT mode + 32-kHz oscillation
Supply Current IDD (mA)
0.1
Subsystem clock operation mode (SOS.1 = 0)
0.05 Subsystem clock HALT mode (SOS.1 = 0) Main system clock STOP mode + 32-kHz oscillation (SOS.1 = 0) Main system clock STOP mode + 32-kHz oscillation and subsystem clock HALT mode (SOS.1 = 1)
0.01
0.005
X1
4.19 MHz
X2 XT1
Crystal resonator
XT2 330 k 22 pF
32.768 kHz
Crystal resonator
22 pF
22 pF VDD
22 pF VDD 6
0.001
0
1
2
3
4
5
7
8
Supply Voltage VDD (V)
76
PD753104, 753106, 753108
IOH vs VDD--VOH (Ports 2, 3, 6, 8 and 9)
(TA = 25 C) 15
10 IOH [mA]
VDD = 5 V VDD = 4 V VDD = 5.5 V VDD = 3 V
VDD = 2.2 V
5
VDD = 1.8 V
0
0
0.5
1.0
1.5 VDD--VOH [V]
2.0
2.5
3.0
IOL vs VOL (Ports 2, 3, 6, 8 and 9)
(TA = 25 C) 40
30
VDD = 5 V VDD = 4 V VDD = 5.5 V VDD = 3 V VDD = 2.2 V
IOL [mA]
20
VDD = 1.8 V
10
0
0
0.5
1.0 VOL [V]
1.5
2.0
77
PD753104, 753106, 753108
14. PACKAGE DRAWINGS 64-PIN PLASTIC QFP (14 x 14 mm)
A B
48 49
33 32 detail of lead end
C
D
S
64 1
17 16
F
G
H
IM
J
K
P
N
L P64GC-80-AB8-3 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 17.6 0.4 14.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.55 0.1 0.1 2.85 MAX. INCHES 0.693 0.016 0.551 +0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031+0.009 -0.008 0.006 +0.004 -0.003 0.004 0.100 0.004 0.004 0.112 MAX.
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
78
M
55
Q
PD753104, 753106, 753108
64-PIN PLASTIC LQFP (12 x 12 mm)
A B
48 49 33 32
detail of lead end
C
D
S
64
1
17 16
F
G P
H
I
M
J K
N
NOTE
L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 14.80.4 12.00.2 12.00.2 14.80.4 1.125 1.125 0.300.10 0.13 0.65 (T.P.) 1.40.2 0.60.2 0.15 +0.10 -0.05 0.10 1.4 0.1250.075 55 1.7 MAX. INCHES 0.5830.016 +0.009 0.472 -0.008 0.472 +0.009 -0.008 0.5830.016 0.044 0.044 +0.004 0.012 -0.005 0.005 0.026 (T.P.) 0.0550.008 +0.008 0.024 -0.009 0.006 +0.004 -0.003 0.004 0.055 0.0050.003 55 0.067 MAX. P64GK-65-8A8-1
Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
M
Q
R
79
PD753104, 753106, 753108
15. RECOMMENDED SOLDERING CONDITIONS
The PD753108 should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document "Semiconductor Device Mounting Technology Manual" (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 15-1. Surface Mounting Type Soldering Conditions (1) PD753104GC-xxx-AB8 : 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
PD753106GC-xxx-AB8 : 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch) PD753108GC-xxx-AB8 : 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
Soldering Method Infrared reflow Soldering Conditions Peak package's surface temperature: 235 C, Reflow time: 30 seconds or less (at 210 C or higher), Number of reflow processes: 3 max. Peak package's surface temperature: 215 C, Reflow time: 40 seconds or less (at 200 C or higher), Number of reflow processes: 3 max. Solder temperature: 260 C or below, Flow time: 10 seconds or less, Number of flow processes: 1, Preheating temperature: 120 C or below (package surface temperature) Pin temperature: 300 C or below, Time: 3 seconds or less (per device side) Symbol IR35-00-3
VPS
VP15-00-3
Wave soldering
WS60-00-1
Partial heating
--
Caution
Use of more than one soldering method should be avoided (except for partial heating).
(2) PD753104GK-xxx-8A8 : 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
PD753106GK-xxx-8A8 : 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch) PD753108GK-xxx-8A8 : 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
Soldering Method Infrared reflow Soldering Conditions Peak package's surface temperature: 235 C, Reflow time: 30 seconds or less (at 210 C or higher), Number of reflow processes: 2 max. Peak package's surface temperature: 215 C, Reflow time: 40 seconds or less (at 200 C or higher), Number of reflow processes: 2 max. Solder temperature: 260 C or below, Flow time: 10 seconds or less, Number of flow processes: 1, Preheating temperature: 120 C or below (package surface temperature) Pin temperature: 300 C or below, Time: 3 seconds or less (per device side) Symbol IR35-00-2
VPS
VP15-00-2
Wave soldering
WS60-00-1
Partial heating
--
Caution Use of more than one soldering method should be avoided (except for partial heating).
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APPENDIX A. PD75308B, 753108 AND 75P3116 FUNCTIONAL LIST
Parameter Program memory
PD75308B
Mask ROM 0000H to 1F7FH (8064 x 8 bits) 000H to 1FFH (512 x 4 bits) 75X Standard
PD753108
Mask ROM 0000H to 1FFFH (8192 x 8 bits)
PD75P3116
One-time PROM 0000H to 3FFFH (16384 x 8 bits)
Data memory
CPU Instruction execution time When main system clock is selected When subsystem clock is selected Stack SBS register
75XL CPU * 0.95, 1.91, 3.81, 15.3 s (during 4.19-MHz operation) * 0.67, 1.33, 2.67, 10.7 s (during 6.0-MHz operation)
0.95, 1.91, 15.3 s (during 4.19-MHz operation) 122 s (32.768-kHz operation)
None
SBS.3 = 1: Mk I mode selection SBS.3 = 0: Mk II mode selection 000H to 1FFH When Mk I mode: 2-byte stack When Mk II mode: 3-byte stack
Stack area Subroutine call instruction stack operation
000H to 0FFH 2-byte stack
Instruction
BRA !addr1 CALLA !addr1 MOVT XA, @BCDE MOVT XA, @BCXA BR BCDE BR BCXA CALL !addr CALLF !faddr
Unavailable
When Mk I mode: unavailable When Mk II mode: available Available
3 machine cycles 2 machine cycles 8 16 8 8 40 Segment selection: 24/28/32 segments (can be changed to CMOS input/output port in 4 timeunit; max. 8)
Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles 8 20 0 4 32 Segment selection: 16/20/24 segments (can be changed to CMOS input/output port in 4 time-unit; max. 8)
I/O port
CMOS input CMOS input/output Bit port output N-ch open-drain input/output Total
LCD controller/driver
Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) On-chip split resistor for LCD driver can be specified by using mask option. Timer 3 channels * Basic interval timer: 1 channel * 8-bit timer/event counter: 1 channel * Watch timer: 1 channel No on-chip split resistor for LCD driver
5 channels * Basic interval timer/watchdog timer: 1 channel * 8-bit timer/event counter: 3 channels (can be used as 16-bit timer/event counter) * Watch timer: 1 channel
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PD753104, 753106, 753108
Parameter Clock output (PCL)
PD75308B
* , 524, 262, 65.5 kHz (Main system clock: during 4.19-MHz operation)
PD753108
PD75P3116
* , 524, 262, 65.5 kHz (Main system clock: during 4.19-MHz operation) * , 750, 375, 93.8 kHz (Main system clock: during 6.0-MHz operation) * 2, 4, 32 kHz (Main system clock: during 4.19-MHz operation or subsystem clock: during 32.768-kHz operation) * 2.93, 5.86, 46.9 kHz (Main system clock: 6.0-MHz operation)
BUZ output (BUZ)
* 2 kHz (Main system clock: during 4.19-MHz operation)
Serial interface
3 modes are available * 3-wire serial I/O mode ... MSB/LSB can be selected for transfer first bit * 2-wire serial I/O mode * SBI mode None Contained
SOS register
Feedback resistor cut flag (SOS.0) Sub-oscillator current cut flag (SOS.1)
None
Contained
Register bank selection register (RBS) Standby release by INT0 Vectored interrupt Supply voltage Operating ambient temperature Package
None Unavailable External: 3, internal: 3 VDD = 2.0 to 6.0 V TA = -40 to +85 C * 80-pin plastic QFP (14 x 20 mm) * 80-pin plastic QFP (14 x 14 mm) * 80-pin plastic TQFP (Fine pitch) (12 x 12 mm)
Yes Available External: 3, internal: 5 VDD = 1.8 to 5.5 V
* 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch) * 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
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PD753104, 753106, 753108
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are provided for system development using the PD753108. In the 75XL Series, the relocatable assembler which is common to the series is used in combination with the device file of each product. Language processor
RA75X relocatable assembler Part number (product name)
Host machine OS PC-9800 Series MS-DOSTM Ver. 3.30 to Ver. 6.2 IBM PC/ATTM and compatible machines Refer to "OS for IBM PC "
Note
Supply media 3.5-inch 2HD 5-inch 2HD
S5A13RA75X S5A10RA75X S7B13RA75X S7B10RA75X
3.5-inch 2HC 5-inch 2HC
Device file
Host machine OS PC-9800 Series MS-DOS Ver. 3.30 to Ver. 6.2 IBM PC/AT and compatible machines Refer to "OS for IBM PC "
Note
Supply media 3.5-inch 2HD 5-inch 2HD
Part number (product name)
S5A13DF753108 S5A10DF753108 S7B13DF753108 S7B10DF753108
3.5-inch 2HC 5-inch 2HC
Note
Ver. 5.00 and later have the task swap function, but it cannot be used for this software.
Remark Operation of the assembler and the device file is guaranteed only on the above host machines and OSs.
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PD753104, 753106, 753108
PROM write tools
Hardware PG-1500 PG-1500 is a PROM programmer which enables you to program single-chip microcontrollers including PROM by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to PG-1500. It also enables you to program typical PROM devices of 256K bits to 4M bits. PROM programmer adapter for the PD75P3116GC. Connect the programmer adapter to PG-1500 for use. PROM programmer adapter for the PD75P3116GK. Connect the programmer adapter to PG-1500 for use. PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500 is controlled on the host machine. Host machine OS PC-9800 Series MS-DOS Ver. 3.30 to Ver. 6.2 Note IBM PC/AT and compatible machines Refer to " OS for IBM PC" 3.5-inch 2HD 5-inch 2HC Supply media 3.5-inch 2HD 5-inch 2HD Part number (product name)
PA-75P3116GC
PA-75P3116GK
Software
PG-1500 controller
S5A13PG1500 S5A10PG1500 S7B13PG1500 S7B10PG1500
Note
Ver. 5.00 and later have the task swap function, but it cannot be used for this software.
Remark Operation of the PG-1500 controller is guaranteed only on the above host machines and OSs.
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PD753104, 753106, 753108
Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the
PD753108.
The system configurations are described as follows.
Hardware IE-75000-R
Note 1
In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X Series and 75XL Series. When developing a PD753108 Subseries, the emulation board (IE-75300-R-EM) and emulation probe (EP-753108GC-R or EP-753108GK-R) that are sold separately must be used with the IE-75000-R. By connecting with the host machine and the PROM programmer, efficient debugging can be made. It contains the emulation board (IE-75000-R-EM) which is connected. In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X Series and 75XL Series. When developing a PD753108 Subseries, the emulation board (IE-75300-R-EM) and emulation probe (EP-753108GC-R or EP-753108GK-R) that are sold separately must be used with the IE-75001-R. It can debug the system efficiently by connecting the host machine and PROM programmer. Emulation board for evaluating the application systems that use a PD753108 Subseries. It must be used with the IE-75000-R or IE-75001-R. Emulation probe for the PD753108GC. It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the 64-pin conversion socket EV-9200GC-64 which facilitates connection to a target system. Emulation probe for the PD753108GK. It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the 64-pin conversion adapter TGK-064SBW which facilitates connection to a target system. Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronics interface and controls the IE-75000-R or IE-75001-R on a host machine. Host machine OS PC-9800 Series MS-DOS Ver. 3.30 to Ver. 6.2 Note 3 IBM PC/AT and compatible machines Refer to "OS for IBM PC " 3.5-inch 2HC 5-inch 2HC Supply media 3.5-inch 2HD 5-inch 2HD Part No. (product name)
IE-75001-R
IE-75300-R-EM
EP-753108GC-R
EV-9200GC-64 EP-753108GK-R
TGK-064SBW Software
Note 2
IE control program
S5A13IE75X S5A10IE75X S7B13IE75X S7B10IE75X
Notes 1. 2. 3.
Maintenance product. This is a product of TOKYO ELETECH CORPORATION (Tokyo 03-5295-1661). For purchasing, contact an NEC sales representative. Ver. 5.00 and later have the task swap function, but it cannot be used for this software.
Remarks 1. Operation of the IE control program is guaranteed only on the above host machines and OSs. 2. The PD753104, 753106, 753108 and 75P3116 are commonly referred to as the PD753108 Subseries.
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PD753104, 753106, 753108
OS for IBM PC The following IBM PC OS's are supported.
OS PC DOSTM Version Ver. 3.1 to Ver. 6.3 J6.1/V Note to J6.3/V Ver. 5.0 to Ver. 6.22 5.0/V Note to 6.2/V Note J5.02/V Note
Note
MS-DOS
IBM DOSTM
Note Only the English mode is supported. Caution Ver. 5.0 and later have the task swap function, but it cannot be used for this software.
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PD753104, 753106, 753108
APPENDIX C. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
Device Related Documents
Document No. Document Name English Japanese U10086J U11369J U10890J IEM-5600 U10453J
PD753104, 753106, 753108 Data Sheet PD75P3116 Data Sheet PD753108 User's Manual PD753108 Instruction Application Table
75XL Series Selection Guide
U10086E (This document) U11369E U10890E -- U10453E
Development Tool Related Documents
Document No. Document Name English Hardware IE-75000-R/IE-75001-R User's Manual IE-75300-R-EM User's Manual EP-753108GC/GK-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual PG-1500 Controller User's Manual Operation Language PC-9800 Series (MS-DOS) base IBM PC Series (PC DOS) base EEU-1416 U11354E EEU-1495 EEU-1335 EEU-1346 EEU-1363 EEU-1291 Japanese EEU-846 U11354J EEU-968 U11940J EEU-731 EEU-730 EEU-704
U10540E
EEU-5008
Other Related Documents
Document No. Document Name English IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcomputer Product Series Guide C10943X C10535E C11531E C10983E -- MEI-1202 -- C10535J C11531J C10983J MEM-539 C11893J U11416J Japanese
Caution
The above related documents are subject to change without notice. For design purpose, etc., be sure to use the latest documents.
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PD753104, 753106, 753108
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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PD753104, 753106, 753108
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96. 8
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PD753104, 753106, 753108
MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96. 5
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