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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA 8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Performance Silicon-Gate CMOS The MC74HC299 is identical in pinout to the LS299. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC299 features a multiplexed parallel input/output data port to achieve full 8-bit handling in a 20 pin package. Due to the large output drive capability and the 3-state feature, this device is ideally suited for interface with bus lines in a bus-oriented system. Two Mode-Select inputs and two Output Enable inputs are used to choose the mode of operation as listed in the Function Table. Synchronous parallel loading is accomplished by taking both Mode-Select lines, S1 and S2, high. This places the outputs in the high-impedance state, which permits data applied to the data port to be clocked into the register. Reading out of the register can be accomplished when the outputs are enabled. The active-low asynchronous Reset overrides all other inputs. * Output Drive Capability: 15 LSTTL Loads for QA through QH 10 LSTTL Loads for QA and QH * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2 to 6 V * Low Input Current: 1 A * High Noise Immunity Characteristic of CMOS Devices * In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 398 FETs or 99.5 Equivalent Gates 20 MC74HC299 N SUFFIX PLASTIC PACKAGE CASE 738-03 1 20 1 DW SUFFIX SOIC PACKAGE CASE 751D-04 ORDERING INFORMATION MC74HCXXXN MC74HCXXXDW Plastic SOIC PIN ASSIGNMENT S1 OE1 OE2 PG/QG PE/QE PC/QC PA/QA QA RESET 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC S2 SH QH PH/QH PF/QF PD/QD PB/QB CLOCK SA LOGIC DIAGRAM 7 13 6 14 5 15 4 16 8 17 GND SERIAL DATA INPUTS SA (SHIFT RIGHT) 11 SH (SHIFT LEFT) 18 CLOCK 12 RESET MODE S1 SELECT S2 OUTPUT OE1 ENABLES OE2 9 1 19 2 3 PA/QA PB/QB PC/QC PD/QD PE/QE PF/QF PG/QG PH/QH QA QH 3-STATE PARALLEL DATA PORT (INPUTS/OUTPUTS) SERIAL DATA OUTPUTS PIN 20 = VCC PIN 10 = GND 10/95 (c) Motorola, Inc. 1995 3-1 REV 6 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I III I I I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I III I I I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I III I I I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I II IIII I I I I II IIIIIIIIIIIIIIIIIIIIIII III I III I I I I IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III I III I I II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIII I IIIIIIIIIIIIIIIIIIIIIII III III I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III III I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). Vin = VCC or GND 6.0 8 80 160 A Iout = 0 A NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIIIII I I I III IIIIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* MOTOROLA DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) RECOMMENDED OPERATING CONDITIONS MC74HC299 Symbol VIH Symbol VCC Vin, Vout TA Symbol VOH VCC Vin VOL Vout Iin Tstg TL ICC Iout ICC PD Iin IOZ VIL tr, tf Maximum Quiescent Supply Current (per Package) Maximum Three-State Leakage Current (QA thru QH) Maximum Input Leakage Current Maximum Low-Level Output Voltage Minimum High-Level Output Voltage Maximum Low-Level Input Voltage Parameter Minimum High-Level Input Voltage Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Storage Temperature Power Dissipation in Still Air DC Supply Current, VCC and GND Pins DC Output Current, per Pin DC Input Current, per Pin DC Output Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Supply Voltage (Referenced to GND) Input Rise and Fall Time (Figure 1) Operating Temperature, All Package Types DC Input Voltage, Output Voltage (Referenced to GND) DC Supply Voltage (Referenced to GND) Parameter Parameter Vin = VCC or GND Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL Vin = VIH or VIL |Iout| |Iout| Vin = VIH or VIL Vin = VIH or VIL |Iout| |Iout| Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Test Conditions Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Plastic DIP SOIC Package v v v v VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V v 6.0 mA (P/Q) v 7.8 mA (P/Q) |Iout| v 4.0 mA (Q) |Iout| v 5.2 mA (Q) v 6.0 mA (P/Q) v 7.8 mA (P/Q) |Iout| v 4.0 mA (Q) |Iout| v 5.2 mA (Q) - 0.5 to VCC + 0.5 - 1.5 to VCC + 1.5 3-2 - 65 to + 150 - 0.5 to + 7.0 - 55 Min 2.0 Value 0 0 0 0 75 35 20 260 750 500 VCC + 125 1000 500 400 Max 6.0 Unit Unit mW mA mA mA _C _C _C VCC V ns V V V V V 6.0 6.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit - 55 to 25_C 85_C 125_C 1.5 1.5 1.5 3.15 3.15 3.15 4.2 4.2 4.2 0.5 0.1 0.26 0.26 0.26 0.26 3.98 5.48 3.98 5.48 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. v High-Speed CMOS Logic Data DL129 -- Rev 6 5.0 1.0 0.33 0.33 0.33 0.33 3.84 5.34 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2 v v 1.0 0.40 0.40 0.40 0.40 3.70 5.20 3.70 5.20 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2 10 v Unit V A A V V V IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). High-Speed CMOS Logic Data DL129 -- Rev 6 Symbol tPLH, tPHL tPLH, tPHL tTLH, tTHL tTLH, tTHL tPZL, tPZH tPLZ, tPHZ tPHL tPHL fmax CPD Cout Cin Maximum Three-State Output Capacitance (Output in High-Impedance State), QA thru QH Maximum Input Capacitance Maximum Output Transition Time, QA or QH (Figures 1 and 5) Maximum Output Transition Time, QA thru QH (Figures 1 and 5) Maximum Propagation Delay, Reset to QA thru QH (Figures 2 and 5) Maximum Propagation Delay, Reset to QA or QH (Figures 2 and 5) Maximum Propagation Delay, Clock to QA thru QH (Figures 1 and 5) Maximum Propagation Delay, Clock to QA or QH (Figures 1 and 5) Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 5) Parameter * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Power Dissipation Capacitance (Per Package)*, Outputs Enabled Maximum Propagation Delay, OE1, OE2, S1, or S2 to QA thru QH (Figures 3 and 6) Maximum Propagation Delay, OE1, OE2, S1, or S2 to QA thru QH (Figures 3 and 6) 3-3 VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- -- - 55 to 25_C Typical @ 25C, VCC = 5.0 V 150 30 26 150 30 26 190 38 32 175 35 30 160 32 27 170 34 29 5.0 25 29 15 10 75 15 13 60 12 10 Guaranteed Limit 190 38 33 190 38 33 240 48 41 220 44 37 200 40 34 215 43 37 240 4.0 20 24 15 10 95 19 16 75 15 13 225 45 38 225 45 38 285 57 48 265 53 45 240 48 41 255 51 43 110 22 19 3.4 17 20 15 10 90 18 15 v 85_C v 125_C MC74HC299 MOTOROLA MHz Unit pF pF pF ns ns ns ns ns ns ns ns IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). MOTOROLA TIMING REQUIREMENTS (Input tr = tf = 6 ns) MC74HC299 Symbol trec tf, tf tsu tsu tw tw th th Maximum Input Rise and Fall Times (Figure 1) Minimum Pulse Width, Reset (Figure 2) Minimum Pulse Width, Clock (Figure 1) Minimum Recovery Time, Reset Inactive to Clock (Figure 2) Minimum Hold Time, Clock to Data Inputs, SA, SH, PA thru PH (Figure 4) Minimum Hold Time, Clock to Mode Select S1 or S2 (Figure 4) Minimum Setup Time, Data Inputs SA, SH, PA thru PH to Clock (Figure 4) Minimum Setup Time, Mode Select S1 or S2 to Clock (Figure 4) Parameter 3-4 VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - 55 to 25_C 1000 500 400 120 24 20 100 20 17 100 20 17 80 16 14 80 16 14 50 10 9 5 5 5 Guaranteed Limit v 85_C v 125_C High-Speed CMOS Logic Data DL129 -- Rev 6 1000 500 400 100 20 17 100 20 17 150 30 26 125 25 21 125 25 21 65 13 11 5 5 5 1000 500 400 120 24 20 120 24 20 180 36 31 150 30 26 150 30 26 75 15 13 5 5 5 Unit ns ns ns ns ns ns ns ns MC74HC299 FUNCTION TABLE Inputs Mode Select Mode Reset Reset L L L H H H H H H H S2 X L H L L L H H H H S1 L X H H H H L L L H Output Enables OE1 L L X H X L H X L X OE2 L L X X H L X H L X Clock X X X Serial Inputs DA X X X D D D X X X X DH X X X X X X D D D X PA/QA L L PB/QB L L PC/QC L L PD/QD PE/QE PF/QF L L PG/QG L L PH/QH L L QA L L L D D D QB QB QB PA PA PA PA QH L L L QG QG QG D D D PH PH PH PH Response L L L L QA through QH = Z Shift Right Shift Right: QA through QH = Z; DA FA; FA FB; etc. Shift Right: QA through QH = Z; DA FA; FA FB; etc. Shift Right: DA FA = QA; FA FB = QB; etc. Shift Left Shift Left: QA through QH = Z; DH FH; FH FG; etc. Shift Left: QA through QH = Z; DH FH; FH FG; etc. Shift Left: DH FH = QH; FH FG = QG; etc. Parallel Load Hold Parallel Load: PN Hold: QA through QH = Z; FN = FN Hold: QA through QH = Z; FN = FN Hold: QN = QN FN H H H L L L L L L H X L X H L X X X X X X X X X Z = high impedance D = data on serial input F = flip-flop (see Logic Diagram) When one or both output controls are high the eight input/output terminals are disabled to the high impedance state, however, sequential operation or clearing of the register is not affected. PIN DESCRIPTIONS DATA INPUTS SA (Pin 11) Serial data input (Shift Right). Data on this input is shifted into the shift register on the rising edge of Clock when S2 is low and S1 is high (shift right mode). SH (Pin 18) Serial data input (Shift Left). Data on this input is shifted into the shift register on the rising edge of Clock when S2 is high and S1 is low (shift left mode). PA through PH (Pins 7, 13, 6, 14, 5, 15, 4, 16) Parallel data port inputs. Data on these pins can be parallel loaded into the shift register on the rising edge of Clock when both S1 and S2 are high. For any other combination of S1 and S2, these pins serve as the outputs of the shift register. CONTROL INPUTS Clock (Pin 12) Clock input. A low-to-high transition on this pin shifts the data at each stage to the next stage (shift right or left mode) or loads the data at the parallel data inputs into the shift register (parallel load mode). OE1, OE2 (Pins 2, 3) Active-low output enables. When both OE1 and OE2 are low, the Outputs QA through QH are enabled. When one or both output enables are high, the outputs are forced to the high-impedance state; however, sequential operation or clearing of the register is not affected. Reset (Pin 9) Active-low reset. A low on this pin resets all stages of the register to a low level. The reset operation is asynchronous. S1, S2 (Pins 1, 19) Mode select inputs. The levels present at these pins determine the shift register's mode of operation: S1 = S2 = Low. Hold. S1 = Low, S2 High. Shift left. S1 = High, S2 Low. Shift right. S1 = S2 = High. Parallel load. OUTPUTS QA, QH (Pins 8, 17) Serial data outputs. These are the outputs of the first and last stages of the shift register, respectively. These outputs are not 3-state outputs and have standard drive capabilities. QA through QH (Pins 7, 13, 6, 14, 5, 15, 4, 16) Parallel data port outputs. Shifted data is present at these pins when OE1 and OE2 are low. For all other combinations of OE1 and OE2 these outputs are in the high-impedance state. High-Speed CMOS Logic Data DL129 -- Rev 6 3-5 MOTOROLA MC74HC299 SWITCHING WAVEFORMS tr CLOCK 90% 50% 10% tw 1/fmax tPLH QA, QH, QA-QH 90% 50% 10% tTLH tTHL tPHL QA, QH, QA-QH tf VCC RESET GND tPHL 50% trec CLOCK 50% VCC GND 50% GND tw VCC Figure 1. Figure 2. S1 OR S2 VCC OE1 OR OE2 50% GND tPZL 50% 10% QA-QH 50% tPZH tPHZ 90% VOH HIGH IMPEDANCE tPLZ HIGH IMPEDANCE VOL QA-QH 50% 50% tPZH tPHZ 90% S2 OR S1 50% VCC GND VCC GND tPZL tPLZ 10% HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE Figure 3a. Figure 3b. TEST POINT OUTPUT VCC GND DEVICE UNDER TEST VALID MODE SELECT OR DATA 50% tsu CLOCK th VCC 50% GND CL* * Includes all probe and jig capacitance Figure 4. TEST POINT OUTPUT DEVICE UNDER TEST 1 k Figure 5. Test Circuit CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. * Includes all probe and jig capacitance Figure 6. Test Circuit MOTOROLA 3-6 High-Speed CMOS Logic Data DL129 -- Rev 6 MC74HC299 EXPANDED LOGIC DIAGRAM 11 SR H CLK CLK Q D FA Q R 8 QA SA DEMUX O CLOCK 12 CLK LD SL 7 PA/QA CLK RESET 9 R SR H DEMUX O LD SL CLK CLK Q D FB Q R 13 PB/QB SR H SR H DEMUX O A B O C D SR H LD SL CLK CLK Q D FC Q R 6 PC/QC DEMUX O LD SL CLK CLK Q D FD Q R 14 PD/QD SR LD SL H DEMUX O LD SL DETAIL OF DEMULTILPLEXER CLK CLK Q D FE Q R 5 PE/QE A S1 1 B SR H DEMUX O LD SL CLK CLK Q D FF Q R 15 PF/QF S2 19 C D SR H DEMUX O LD SL CLK CLK Q D FG Q R 4 PG/QG SR OE1 OE2 2 3 H DEMUX O LD SL CLK CLK Q D FH Q R 16 PH/QH SH 18 17 QH High-Speed CMOS Logic Data DL129 -- Rev 6 3-7 MOTOROLA MC74HC299 OUTLINE DIMENSIONS -A- 20 11 N SUFFIX PLASTIC PACKAGE CASE 738-03 ISSUE E B 1 10 C L NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 -T- SEATING PLANE K M E G F D 20 PL N J 0.25 (0.010) M 20 PL 0.25 (0.010) TA M M TB M DIM A B C D E F G J K L M N -A- 20 11 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE E 10X -B- 1 10 P 0.010 (0.25) M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 20X D M 0.010 (0.25) TA S B J S F R X 45 _ C -T- 18X SEATING PLANE G K M Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA CODELINE 3-8 *MC74HC299/D* MC74HC299/D High-Speed CMOS Logic Data DL129 -- Rev 6 |
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