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INTEGRATED CIRCUITS
DATA SHEET
FAMILY SPECIFICATIONS HCMOS family characteristics
March 1988 File under Integrated Circuits, IC06
Philips Semiconductors
HCMOS family characteristics
GENERAL These family specifications cover the common electrical ratings and characteristics of the entire HCMOS 74HC/HCT/HCU family, unless otherwise specified in the individual device data sheet. INTRODUCTION The 74HC/HCT/HCU high-speed Si-gate CMOS logic family combines the low power advantages of the HE4000B family with the high speed and drive capability of the low power Schottky TTL (LSTTL). The family will have the same pin-out as the 74 series and provide the same circuit functions. In these families are included several HE4000B family circuits which do not have TTL counterparts, and some special circuits. The basic family of buffered devices, designated as XX74HCXXXXX, will operate at CMOS input logic levels for high noise immunity, negligible typical quiescent supply and input current. It is operated from a power supply of 2 to 6 V.
FAMILY SPECIFICATIONS
A subset of the family, designated as XX74HCTXXXXX, with the same features and functions as the "HC-types", will operate at standard TTL power supply voltage (5 V 10%) and logic input levels (0.8 to 2.0 V) for use as pin-to-pin compatible CMOS replacements to reduce power consumption without loss of speed. These types are also suitable for converted switching from TTL to CMOS. Another subset, the XX74HCUXXXXX, consists of single-stage unbuffered CMOS compatible devices for application in RC or crystal controlled oscillators and other types of feedback circuits which operate in the linear mode. HANDLING MOS DEVICES Inputs and outputs are protected against electrostatic effects in a wide variety of device-handling situations. However, to be totally safe, it is desirable to take handling precautions into account (see also "HANDLING PRECAUTIONS").
RECOMMENDED OPERATING CONDITIONS FOR 74HC/HCT 74HC SYMBOL PARAMETER min. typ. VCC VI VO Tamb Tamb tr, tf DC supply voltage DC input voltage range DC output voltage range 2.0 0 0 5.0 max. 6.0 VCC VCC +85 +125 1000 6.0 500 400 Note 1. For analog switches, e.g. "4016", "4051 series", "4351 series", "4066" and "4067", the specified maximum operating supply voltage is 10 V. 6.0 500 ns min. typ. max. 4.5 0 0 -40 -40 5.0 5.5 VCC VCC +85 +125 V V V C C see DC and AC CHAR. per device VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 74HCT UNIT CONDITIONS
operating ambient temperature range -40 operating ambient temperature range -40 input rise and fall times except for Schmitt-trigger inputs
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HCMOS family characteristics
RECOMMENDED OPERATING CONDITIONS FOR 74HCU
FAMILY SPECIFICATIONS
74HCU SYMBOL VCC VI VO Tamb Tamb PARAMETER min. typ. max. DC supply voltage DC input voltage range DC output voltage range operating ambient temperature range operating ambient temperature range 2.0 0 0 -40 -40 5.0 6.0 VCC VCC +85 V V V C see DC and AC CHAR. per device UNIT CONDITIONS
+125 C
RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltages are referenced to GND (ground = 0 V) SYMBOL VCC IIK IOK IO PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current standard outputs bus driver outputs ICC; IGND DC VCC or GND current for types with: standard outputs bus driver outputs Tstg Ptot storage temperature range power dissipation per package plastic DIL plastic mini-pack (SO) Note 1. For analog switches, e.g. "4016", "4051 series", "4351 series", "4066" and "4067", the specified maximum operating supply voltage is 11 V. 750 500 mW mW -65 50 70 +150 mA mA C for temperature range: -40 to +125 C 74HC/HCT/HCU above +70 C: derate linearly with 12 mW/K above +70 C: derate linearly with 8 mW/K 25 35 mA mA MIN. MAX. -0.5 +7 20 20 UNIT CONDITIONS V mA mA for VI < -0.5 or VI > VCC + 0.5 V for VO < -0.5 or VO > VCC + 0.5 V for -0.5 V < VO < VCC + 0.5 V
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HCMOS family characteristics
DC CHARACTERISTICS FOR 74HC Voltages are referenced to GND (ground = 0 V) Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to +85
FAMILY SPECIFICATIONS
TEST CONDITIONS UNIT V CC (V) V 2.0 4.5 6.0 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 3.7 5.2 V V V V 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 4.5 6.0 0.1 0.1 0.1 0.4 0.4 0.4 0.4 1.0 A V V V 2.0 4.5 6.0 4.5 6.0 4.5 6.0 6.0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIH or VIL VCC or GND VIH or VIL VO = VCC or GND -IO = 20 A -IO = 20 A -IO = 20 A -IO = 4.0 mA -IO = 5.2 mA -IO = 6.0 mA -IO = 7.8 mA IO = 20 A IO = 20 A IO = 20 A IO = 4.0 mA IO = 5.2 mA IO = 6.0 mA IO = 7.8 mA
-40 to +125 max.
VI
OTHER
min. typ. max. min. max. min. VIH HIGH level input voltage 1.5 4.2 VIL LOW level input voltage 1.2 3.2 0.8 2.1 2.8 VOH HIGH level output voltage all outputs HIGH level output voltage standard outputs HIGH level output voltage bus driver outputs LOW level output voltage all outputs LOW level output voltage standard outputs LOW level output voltage bus driver outputs input leakage current 1.9 4.4 5.9 2.0 4.5 6.0 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 3.84 5.34 0.1 0.1 0.1 0.1 0.1 0.1 0.33 0.33 0.33 0.33 1.0 1.5 3.15 4.2 0.5 1.35 1.8 1.5 3.15 4.2 3.15 2.4
VOH
3.98 4.32 5.48 5.81 3.98 4.32 5.48 5.81 0 0 0
VOH
VOL
VOL
0.15 0.26 0.16 0.26 0.15 0.26 0.16 0.26 0.1
VOL
II
IOZ
3-state OFF-state current quiescent supply current SSI flip-flops MSI LSI
0.5
5.0
10.0
A
6.0
ICC
2.0 4.0 8.0 50.0
20.0 40.0 80.0 500
40.0 80.0 160.0 1000
A
6.0 6.0 6.0 6.0
VCC IO = 0 or IO = 0 GND IO = 0 IO = 0
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HCMOS family characteristics
DC CHARACTERISTICS FOR 74HCT Voltages are referenced to GND (ground = 0 V) Tamb (C) 74HCT SYMBOL PARAMETER +25
FAMILY SPECIFICATIONS
TEST CONDITIONS UNIT VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIH or VIL
VCC or GND
-40 to +85 -40 to +125
VI
OTHER
min. typ. max. min. max. min. max. VIH
HIGH level input voltage LOW level input voltage HIGH level output voltage all outputs HIGH level output voltage standard outputs HIGH level output voltage bus driver outputs LOW level output voltage all outputs LOW level output voltage standard outputs LOW level output voltage bus driver outputs
2.0
1.6
2.0
2.0
V
VIL
1.2
0.8
0.8
0.8
V
VOH
4.4
4.5
4.4
4.4
V
-IO = 20 A
VOH
3.98
4.32
3.84
3.7
V
4.5
-IO = 4.0 mA
VOH
3.98
4.32
3.84
3.7
V
4.5
-IO = 6.0 mA
VOL
0
0.1
0.1
0.1
V
4.5
IO = 20 A
VOL
0.15
0.26
0.33
0.4
V
4.5
IO = 4.0 mA
VOL
0.16
0.26
0.33
0.4
V
4.5
IO = 6.0 mA
II
input leakage current
3-state OFF-state current
0.1
1.0
1.0
A
5.5
IOZ
0.5
5.0
10.0
A
5.5
VIH or VIL
VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0
ICC
quiescent supply current SSI flip-flops MSI LSI 2.0 4.0 8.0 50.0 20.0 40.0 80.0 500 40.0 80.0
160.0
A
5.5 5.5 5.5 5.5
VCC or GND
IO = 0 IO = 0 IO = 0 IO = 0
1000
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HCMOS family characteristics
FAMILY SPECIFICATIONS
Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85 -40 to +125 UNIT
TEST CONDITIONS VCC (V) 4.5 to 5.5
VI
OTHER
min. typ. max. min. max. min. max. ICC
additional quiescent supply current per input pin for unit load coefficient is 1 (note 1)
100
360
450
490
A
VCC other inputs at -2.1 V VCC or GND; IO = 0
Note 1. The additional quiescent supply current per input is determined by the ICC unit load, which has to be multiplied by the unit load coefficient as given in the individual data sheets. For dual supply systems the theoretical worst-case (VI = 2.4 V; VCC = 5.5 V) specification is: ICC = 0.65 mA (typical) and 1.8 mA (maximum) across temperature.
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HCMOS family characteristics
DC CHARACTERISTICS FOR 74HCU Voltages are referenced to GND (ground = 0 V) Tamb (C) 74HCU SYMBOL PARAMETER +25 -40 to +85
FAMILY SPECIFICATIONS
TEST CONDITIONS UNIT V CC (V) V 2.0 4.5 6.0 0.3 0.9 1.2 1.8 4.0 5.5 3.7 5.2 V V V 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 0.2 0.5 0.5 0.4 0.4 1.0 A V V 2.0 4.5 6.0 4.5 6.0 6.0 VIH or VIL VCC or GND VIH or VIL VCC or GND VCC or GND VCC or GND IO = 0 -IO = 20 A -IO = 20 A -IO = 20 A -IO = 4.0 mA -IO = 5.2 mA IO = 20 A IO = 20 A IO = 20 A IO = 4.0 mA IO = 5.2 mA
-40 to +125
VI
OTHER
min. typ. max. min. max. min. max. VIH HIGH level input voltage 1.7 3.6 4.8 VIL LOW level input voltage 1.4 2.6 3.4 0.6 1.9 2.6 VOH HIGH level output voltage 1.8 4.0 5.5 VOH HIGH level output voltage LOW level output voltage 2.0 4.5 6.0 0.3 0.9 1.2 1.8 4.0 5.5 3.84 5.34 0.2 0.5 0.5 0.2 0.5 0.5 0.33 0.33 1.0 1.7 3.6 4.8 0.3 0.9 1.2 1.7 3.6 4.8
3.98 4.32 5.48 5.81 0 0 0
VOL
VOL
LOW level output voltage input leakage current
0.15 0.26 0.16 0.26 0.1
II
ICC
quiescent supply current SSI
2.0
20.0
40.0
A
6.0
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HCMOS family characteristics
AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to +85
FAMILY SPECIFICATIONS
TEST CONDITIONS UNIT VCC (V) 2.0 4.5 6.0 ns 2.0 4.5 6.0 Figs 3 and 4 WAVEFORMS
-40 to +125 max. 110 22 19 90 18 15
min. typ. max. min. max. min. tTHL/ tTLH output transition time standard outputs 19 7 6 tTHL/ tTLH output transition time bus driver outputs 14 5 4 AC CHARACTERISTICS FOR 74HCU GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCU SYMBOL PARAMETER +25 -40 to +85 75 15 13 60 12 10 95 19 16 75 15 13
ns
Figs 3 and 4
TEST CONDITIONS UNIT VCC (V) 2.0 4.5 6.0 WAVEFORMS
-40 to +125 max. 110 22 19
min. typ. max. min. max. min. tTHL/ tTLH output transition time 19 7 6 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85 75 15 13 95 19 16
ns
Fig.1
TEST CONDITIONS UNIT VCC (V) WAVEFORMS
-40 to +125 max. 22 18
min. typ. max. min. max. min. tTHL/ tTLH tTHL/ tTLH output transition time standard outputs output transition time bus driver outputs 7 5 15 12 19 15
ns ns
4.5 4.5
Figs 8 and 9 Figs 8 and 9
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HCU TYPES AC waveforms 74HCU
tr 90% INPUT 10% tPHL 90% OUTPUT tTHL 50% 10% tTLH tPLH 50% tf
FAMILY SPECIFICATIONS
handbook, halfpage
VCC
GND
MGK564
Fig.1 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.
Test circuit for 74HCU
handbook, halfpage
VCC VI D.U.T RT CL 50 pF VO
PULSE GENERATOR
MGK565
CL RT
= =
load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values). termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.2 Test circuit.
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HCMOS family characteristics
HC TYPES AC waveforms 74HC
FAMILY SPECIFICATIONS
handbook, halfpage
tr 90%
tf VCC
INPUT 10% tPHL 90% OUTPUT tTHL
50% GND tPLH 50% 10% tTLH
MGK564
Fig.3 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.
AC waveforms 74HC
handbook, full pagewidth
tr 90% CLOCK INPUT 10 % tWH 50%
1/fmax tf VCC
GND tWL th th VCC
DATA INPUT
50% GND tsu tTLH 90% 50% 10% trem tPLH tPHL VCC 50% GND
MGK569
tsu
tTHL
OUTPUT
SET, RESET, PRESET INPUT
(1) In Fig.4 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals (SET, RESET and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual active levels of the forcing signals are specified in the individual device data sheet. (2) For AC measurements: tr = tf = 6 ns; when measuring fmax, there is no constraint on tr, tf with 50% duty factor.
Fig.4
Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for sequential logic ICs.
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HCMOS family characteristics
Test circuit for 74HC
FAMILY SPECIFICATIONS
handbook, halfpage
VCC VI D.U.T RT CL 50 pF VO
PULSE GENERATOR
MGK565
CL RT
= =
load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values). termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.5 Test circuit.
AC waveforms 74HC (continued)
handbook, full pagewidth
tf 90% OUTPUT ENABLE 50% 10% tPLZ OUTPUT LOW-to-OFF OFF-to-LOW tPHZ OUTPUT HIGH-to-OFF OFF-to-HIGH outputs enabled 90%
tr VCC
GND tPZL 50% 10% tPZH 50%
MGK562
outputs disabled
outputs enabled
Fig.6 Propagation delays of 3-state outputs.
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HCMOS family characteristics
Test circuit for 74HC
FAMILY SPECIFICATIONS
handbook, full pagewidth
VCC VI D.U.T RT CL 50 pF
MGK563
VCC VO RL = 1 k
PULSE GENERATOR
Switch position TEST tPZH tPZL tPHZ tPLZ Note 1. For open-drain N-channel outputs tPLZ and tPZL are applicable. SWITCH GND VCC GND VCC
CL RT
= =
load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values). termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.7 Test circuit for 3-state outputs.
HCT TYPES AC waveforms 74HCT
handbook, halfpage
tr 90%
tf 3V
INPUT 10% tPHL 90% OUTPUT tTHL
1.3 V GND tPLH 1.3 V 10% tTLH
MGK567
Fig.8 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.
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HCMOS family characteristics
AC waveforms 74HCT
handbook, full pagewidth
FAMILY SPECIFICATIONS
tr 90% CLOCK INPUT 10% tWH 1.3 V
1/fmax tf 3V
GND tWL th th 3V
DATA INPUT
1.3 V GND tsu tTLH 90% 1.3 V 10% trem tPLH tPHL 3V 1.3 V GND
MGK568
tsu
tTHL
OUTPUT
SET, RESET, PRESET INPUT
(1) In Fig.9 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals (SET, RESET and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual active levels of the forcing signals are specified in the individual device data sheet. (2) For AC measurements: tr = tf = 6 ns; when measuring fmax, there is no constraint on tr, tf with 50% duty factor.
Fig.9
Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for sequential logic ICs.
Test circuit for 74HCT
handbook, halfpage
VCC VI D.U.T RT CL 50 pF VO
PULSE GENERATOR
MGK565
CL RT
= =
load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values). termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.10 Test circuit.
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HCMOS family characteristics
AC waveforms 74HCT (continued)
FAMILY SPECIFICATIONS
handbook, full pagewidth
tf 90% OUTPUT ENABLE 1.3 V 10% tPLZ OUTPUT LOW-to-OFF OFF-to-LOW tPHZ OUTPUT HIGH-to-OFF OFF-to-HIGH outputs enabled 90%
tr
tPZL 1.3 V 10% tPZH 1.3 V
MGK566
outputs disabled
outputs enabled
Fig.11 Propagation delays of 3-state outputs.
Test circuit for 74HCT
handbook, full pagewidth
VCC VI D.U.T RT CL 50 pF
MGK563
VCC VO RL = 1 k
PULSE GENERATOR
Switch position TEST tPZH tPZL tPHZ tPLZ Note 1. For open-drain N-channel outputs tPLZ and tPZL are applicable. SWITCH GND VCC GND VCC
CL RT
= =
load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values). termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.12 Test circuit for 3-state outputs.
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HCMOS family characteristics
DATA SHEET SPECIFICATION GUIDE INTRODUCTION The 74HCMOS data sheets have been designed for ease-of-use. A minimum of cross-referencing for more information is needed. TYPICAL PROPAGATION DELAY AND FREQUENCY The typical propagation delays listed at the top of the data sheets are the average of tPLH and tPHL for the longest data path through the device with a 15 pF load. For clocked devices, the maximum frequency of operation is also given. The typical operating frequency is the maximum device operating frequency with a 50% duty factor and no constraints on tr and tf. LOGIC SYMBOLS Two logic symbols are given for each device - the conventional one (Logic Symbol) which explicitly shows the internal logic (except for complex logic) and the IEC Logic Symbol as developed by the IEC (International Electrotechnical Commission). The IEC has been developing a very powerful symbolic language that can show the relationship of each input of a digital logic current to each output without explicitly showing the internal logic. Internationally, Working Group 2 of IEC Technical Committee TC-3 has prepared a new document (Publication 617-12) which supersedes Publication 117-15, published in 1972. RATINGS The "RATINGS" table (Limiting values in accordance with the Absolute Maximum System - IEC134) lists the maximum limits to which the device can be subjected without damage. This doesn't imply that the device will function at these extreme conditions, only that, when these conditions are removed and the device operated within the Recommended Operating Conditions, it will still be functional and its useful life won't have been shortened. The maximum rated supply voltage of 7 V is well below the typical breakdown voltage of 18 V. RECOMMENDED OPERATING CONDITIONS The "RECOMMENDED OPERATING CONDITIONS" table lists the operating ambient temperature and the March 1988 15
FAMILY SPECIFICATIONS
conditions under which the limits in the "DC CHARACTERISTICS" and "AC CHARACTERISTICS" tables will be met. The table should not be seen as a set of limits guaranteed by the manufacturer, but as the conditions used to test the devices and guarantee that they will then meet the limits in the DC and AC CHARACTERISTICS tables. DC CHARACTERISTICS The "DC CHARACTERISTICS" table reflects the DC limits used during testing. The values published are guaranteed. The threshold values of VIH and VIL can be tested by the user. If VIH and VIL are applied to the inputs, the output voltages will be those published in the "DC CHARACTERISTICS" table. There is a tendency, by some, to use the published VIH and VIL thresholds to test a device for functionality in a "function-table exercizer" mode. This frequently causes problems because of the noise present at the test head of automated test equipment with cables up to 1 metre. Parametric tests, such as those used for the output levels under the VIH and VIL conditions are done fairly slowly, in the order of milliseconds, so that there is no noise at the inputs when the outputs are measured. But in functionality testing, the outputs are measured much faster, so there can be noise on the inputs, before the device has assumed its final and correct output state. Thus, never use VIH and VIL to test the functionality of any HCMOS device type; instead, use input voltages of VCC (for the HIGH state) and 0 V (for the LOW state). In no way does this imply that the devices are noise-sensitive in the final system. In the data sheets, it may appear strange that the typical VIL is higher than the maximum VIL. However, this is because VILmax is the maximum VIL (guaranteed) for all devices that will be recognized as a logic LOW. However, typically a higher VIL will also be recognized as a logic LOW. Conversely, the typical VIH is lower than its minimum guaranteed level. For 74HCMOS, unlike TTL, no output HIGH short-circuit current is specified. The use of this current, for example, to calculate propagation delays with capacitive loads, is covered by the HCMOS graphs showing the output drive capability and those showing the dependence of propagation delay on load capacitance. The quiescent supply current ICC is the leakage current of all the reversed-biased diodes and the OFF-state MOS transistors. It is measured with the inputs at VCC or GND and is typically a few nA.
Philips Semiconductors
HCMOS family characteristics
AC CHARACTERISTICS The "AC CHARACTERISTICS" table lists the guaranteed limits when a device is tested under the conditions given in the AC Test Circuits and Waveforms section. TEST CIRCUITS Good high-frequency wiring practices should be used in test circuits. Capacitor leads should be as short as possible to minimize ripples on the output waveform transitions and undershoot. Generous ground metal (preferably a ground-plane) should be used for the same reasons. A VCC decoupling capacitor should be provided at the test socket, also with short leads. Input signals should have rise and fall times of 6 ns, a signal swing of 0 V to VCC for 74HC and 0 V to 3 V for 74HCT; a 1.0 MHz square wave is recommended for most propagation delay tests. The repetition rate must be increased for testing fmax. Two pulse generators are usually required for testing such parameters as set-up time, hold time and removal time. fmax is also tested with 6 ns input rise and fall times, with a 50% duty factor, but for typical fmax as high as 60 MHz, there are no constraints on rise and fall times.
FAMILY SPECIFICATIONS
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DEFINITIONS OF SYMBOLS AND TERMS USED IN HCMOS DATA SHEETS Currents Positive current is defined as conventional current flow into a device. Negative current is defined as conventional current flow out of a device. ICC ICC IGND II IIK IO Quiescent power supply current; the current flowing into the VCC supply terminal. Additional quiescent supply current per input pin at a specified input voltage and VCC. Quiescent power supply current; the current flowing into the GND terminal. Input leakage current; the current flowing into a device at a specified input voltage and VCC. Input diode current; the current flowing into a device at a specified input voltage. Output source or sink current: the current flowing into a device at a specified output voltage. Output diode current; the current flowing into a device at a specified output voltage. OFF-state output current; the leakage current flowing into the output of a 3-state device in the OFF-state, when the output is connected to VCC or GND. Analog switch leakage current; the current flowing into an analog switch at a specified voltage across the switch and VCC. VT+ VT- VOL VIL
FAMILY SPECIFICATIONS
LOW level input voltage; the range of input voltages that represents a logic LOW level in the system. HIGH level output voltage; the range of voltages at an output terminal with a specified output loading and supply voltage. Device inputs are conditioned to establish a HIGH level at the output. LOW level output voltage; the range of voltages at an output terminal with a specified output loading and supply voltage. Device inputs are conditioned to establish a LOW level at the output. Trigger threshold voltage; positive-going signal. Trigger threshold voltage; negative-going signal.
VOH
Analog terms RON ON-resistance; the effective ON-state resistance of an analog switch, at a specified voltage across the switch and output load. ON-resistance; the difference in ON-resistance between any two switches of an analog device at a specified voltage across the switch and output load.
IOK IOZ
RON
IS
Capacitances CI CI/O Input capacitance; the capacitance measured at a terminal connected to an input of a device. Input/Output capacitance; the capacitance measured at a terminal connected to an I/O-pin (e.g. a transceiver). Output load capacitance; the capacitance connected to an output terminal including jig and probe capacitance. Power dissipation capacitance; the capacitance used to determine the dynamic power dissipation per logic function, when no extra load is provided to the device. Switch capacitance; the capacitance of a terminal to a switch of an analog device.
Voltages All voltages are referenced to GND (ground), which is typically 0 V. GND Supply voltage; for a device with a single negative power supply, the most negative power supply, used as the reference level for other voltages; typically ground. Supply voltage; the most positive potential on the device. Supply voltage; one of two (GND and VEE) negative power supplies. Hysteresis voltage; difference between the trigger levels, when applying a positive and a negative-going input signal. HIGH level input voltage; the range of input voltages that represents a logic HIGH level in the system. 17
CL
VCC VEE VH
CPD
CS
VIH
March 1988
Philips Semiconductors
HCMOS family characteristics
AC switching parameters fi Input frequency; for combinatorial logic devices the maximum number of inputs and outputs switching in accordance with the device function table. For sequential logic devices the clock frequency using alternate HIGH and LOW for data input or using the toggle mode, whichever is applicable. Output frequency; each output. Maximum clock frequency; clock input waveforms should have a 50% duty factor and be such as to cause the outputs to be switching from 10%VCC to 90%VCC in accordance with the device function table. Hold time; the interval immediately following the active transition of the timing pulse (usually the clock pulse) or following the transition of the control input to its latching level, during which interval the data to be recognized must be maintained at the input to ensure their continued recognition. A negative hold time indicates that the correct logic level may be released prior to the timing pulse and still be recognized. Clock input rise and fall times; 10% and 90% values. Propagation delay; the time between the specified reference points, normally the 50% points for 74HC and 74HCU devices on the input and output waveforms and the 1.3 V points for the 74HCT devices, with the output changing from the defined HIGH level to the defined LOW level. Propagation delay; the time between the specified reference points, normally the 50% points for 74HC and 74HCU devices on the input and output waveforms and the 1.3 V point for the 74HCT devices, with the output changing from the defined LOW level to the defined HIGH level. 3-state output disable time; the time between the specified reference points, normally the 50% points for the 74HC and 74HCU devices and the 1.3 V points for the 74HCT devices on the output enable input voltage waveform and a point representing 10% of the output swing on the output voltage waveform of a 3-state device, with the output changing from a HIGH level (VOH) to a high impedance OFF-state (Z). 18 trem tPZH tPLZ
FAMILY SPECIFICATIONS
fo fmax
3-state output disable time; the time between the specified reference points, normally the 50% points for the 74HC devices and the 1.3 V points for the 74HCT devices on the output enable input voltage waveform and a point representing 10% of the output swing on the output voltage waveform of a 3-state device, with the output changing from a LOW level (VOL) to a high impedance OFF-state (Z). 3-state output enable time; the time between the specified reference points, normally the 50% points for the 74HC devices and 1.3 V points for the 74HCT devices on the output enable input voltage waveform and the 50% point on the output voltage waveform of a 3-state device, with the output changing from a high impedance OFF-state (Z) to a HIGH level (VOH). 3-state output enable time; the time between the specified reference points, normally the 50% points for the 74HC devices and the 1.3 V points for the 74HCT devices on the output enable input voltage waveform and the 50% point on the output voltage waveform of a 3-state device, with the output changing from a high impedance OFF-state (Z) to a LOW level (VOL). Removal time; the time between the end of an overriding asynchronous input, typically a clear or reset input, and the earliest permissible beginning of a synchronous control input, typically a clock input, normally measured at the 50% points for 74HC devices and the 1.3 V points for the 74HCT devices on both input voltage waveforms. Set-up time; the interval immediately preceding the active transition of the timing pulse (usually the clock pulse) or preceding the transition of the control input to its latching level, during which interval the data to be recognized must be maintained at the input to ensure their recognition. A negative set-up time indicates that the correct logic level may be initiated sometime after the active transition of the timing pulse and still be recognized.
th
tPZL
t r, tf tPHL
tPLH
tsu
tPHZ
March 1988
Philips Semiconductors
HCMOS family characteristics
tTHL Output transition time; the time between two specified reference points on a waveform, normally 90% and 10% points, that is changing from HIGH-to-LOW. Output transition time; the time between two specified reference points on a waveform, normally 10% and 90% points, that is changing from LOW-to-HIGH. Pulse width; the time between the 50% amplitude points on the leading and trailing edges of a pulse for 74HC and 74HCU devices and at the 1.3 V points for 74HCT devices.
FAMILY SPECIFICATIONS
tTHL
tW
March 1988
19

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