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| ILX511 2048-pixel CCD Linear Image Sensor (B/W) Description The ILX511 is a rectangular reduction type CCD linear image sensor designed for bar code POS hand scanner and optical measuring equipment use. A built-in timing generator and clock-drivers ensure single 5 V power supply for easy use. Features * Number of effective pixels: * Pixel size: * * * * * 22 pin DIP (Plastic) 2048 pixels 14 m x 200 m (14 m pitch) Single 5 V power supply Ultra-high sensitivity Built-in timing generator and clock-drivers Built-in sample-and-hold circuit Maximum clock frequency: 2MHz GND Block Diagram Readout gate pulse generator NC 13 Mode selector CCD analog shift register Pin Configuration (Top View) VDD 15 Readout gate 10 Clock plse generator/ Sample-and-hold pulse generator VOUT GND GND SHSW CLK VDD NC NC VDD 1 2 3 4 5 6 7 8 9 22 1 21 20 VDD VDD VDD GND 17 Clock-drivers GND 16 VDD 20 VDD 21 19 GND 18 VGG VDD 17 GND 16 GND Internal Structure Output amplifier S/H circuit 15 VDD 14 NC 13 NC 2048 12 GND ROG 11 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. --1-- VOUT 1 VGG 18 NC 10 E94108-TE GND 2 GND 3 VDD 6 NC 22 7 NC 8 VDD 9 CLK 5 NC SHSW GND NC 14 4 19 S2046 S2047 S2048 D33 D32 S1 S2 S3 D13 D14 D34 D35 * Operating temperature * Storage temperature D36 D37 6 -10 to +60 -30 to +80 V C C D38 Absolute Maximum Ratings * Supply voltage VDD ROG 12 11 ILX511 Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Symbol VOUT GND GND SHSW CLK VDD NC NC VDD NC ROG GND NC NC VDD GND GND VGG GND VDD VDD VDD Description Signal output GND GND Switch (with S/H or without S/H) Clock pulse input 5V power supply NC NC 5V power supply NC Readout gate pulse input GND NC NC 5V power supply GND GND Output circuit gate bias GND 5V power supply 5V power supply 5V power supply Mode Description Mode in Use With S/H Without S/H Recommended Voltage Item VDD Min. 4.5 Typ. 5.0 Max. 5.5 Unit V Pin 4 (SHSW) GND VDD Input Clock Voltage Condition (Note) Item VIH VIL Min. 4.5 0 Typ. 5.0 -- Max. 5.5 0.5 Unit V V Note) This is applied to the all pulses applied externally. ( CLK, ROG) Item Input capacity of CLK pin Symbol C CLK Min. -- Typ. 10 Max. -- Unit pF --2-- ILX511 Electro-optical Characteristics (Ta = 25 C, VDD = 5 V, Clock frequency: 1 MHz, Light source = 3200 K, IR cut filter: CM-500S (t = 1.0 mm), Without S/H mode) Item Sensitivity 1 Sensitivity 2 Sensitivity nonuniformity Saturation output voltage Dark voltage average Dark signal nonuniformity Image lag Dynamic range Saturation exposure 5 V current consumption Total transfer efficiency Output impedance Offset level Symbol R1 R2 PRNU VSAT VDRK DSNU IL DR SE I VDD TTE ZO VOS Min. 150 -- -- 0.6 -- -- -- -- -- -- 92.0 -- -- Typ. 200 1800 5.0 0.8 3.0 6.0 1 267 0.004 5.0 98.0 250 2.8 Max. 250 -- 10.0 -- 6.0 12.0 -- -- -- 10.0 -- -- -- Unit V/(lx * s) V/(lx * s) % V mV mV % -- lx * s mA % V Remarks Note 1 Note 2 Note 3 -- Note 4 Note 4 Note 5 Note 6 Note 7 -- -- -- Note 8 Note) 1. For the sensitivity test light is applied with a uniform intensity of illumination. 2. Light source: LED = 660nm 3. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1. (VMAX-VMIN)/2 x 100 (%) VAVE PRNU = 4. 5. 6. 7. 8. The maximum output of all the valid pixels is set to VMAX, the minimum output to VMIN and the average output to VAVE. Integration time is 10ms. Typical value is used for clock pulse and readout pulse. VOUT = 500 mV. DR = VSAT/VDRK. When optical integration time is shorter, the dynamic range sets wider because dark voltage is in proportion to optical integration time. SE = VSAT/R1 Vos is defined as indicated below. D30 VOUT D31 D32 S1 Vos GND --3-- Clock Timing Diagram (Without S/H mode) 5 ROG 0 1 2 3 5 CLK 0 D10 D11 D12 D13 D14 D31 D32 D1 D2 D3 D4 D5 S1 S2 S3 D30 S4 --4-- Optical black (18 pixels) Effective picture elements signal (2048 pixels) 1-line output period (2086 pixels) Without S/H mode (4pin AE VDD) VOUT S2045 S2046 S2047 S2048 D33 Dummy signal (32 pixels) Dummy signal (6 pixels) 2088 or more clock pulses are required. D34 D35 D36 D37 D38 2086 1 ILX511 Clock Timing Diagram (With S/H mode) 5 ROG 0 0 1 2 3 5 CLK 0 D5 D0 D1 D2 D3 D4 D9 2086 D12 D13 D30 D11 D10 D31 D32 S4 S3 S2 S1 VOUT Optical black (18 pixels) Effective picture elements signal (2048 pixels) 1-line output period (2087 pixels) Dummy signal (6 pixels) Dummy signal (33 pixels) 2088 or more clock pulses are required. S2045 S2046 S2047 S2048 --5-- D33 D34 D35 D36 D37 D38 1 ILX511 ILX511 CLK Timing (For all modes) t1 CLK t2 t3 t4 Item CLK pulse rise/fall time CLK pulse duty (Note 1) Note 1) 100 x t4 / (t3 + t4) Symbol t1, t2 -- Min. 0 40 Typ. 10 50 Max. 100 60 Unit ns % ROG, CLK Timing ROG t6 t7 t8 CLK t5 t9 Item ROG, CLK pulse timing 1 ROG, CLK pulse timing 2 ROG pulse rise/fall time ROG pulse period Symbol t5 t9 t6, t8 t7 Min. 0 1000 0 3000 Typ. 3000 3000 10 5000 Max. -- -- -- -- Unit ns --6-- ILX511 CLK, VOUT Timing (Note 1) (Note 3) CLK t10 t11 Vout Vout (Note 2) t12 Item CLK-VOUT 1 CLK-VOUT 2 CLK-VOUT (with S/H) Symbol t10 t11 t12 Min. 40 55 10 Typ. 115 120 165 Max. 280 205 240 Unit ns Note 1) Note 2) Note 3) * fck = 1MHz, CLK pulse duty = 50 %, CLK pulse rise/fall time = 10 ns Output waveform when internal S/H is in use. indicates the correspondence of clock pulse and data period. --7-- ILX511 Spectral sensitivity (Typ.) (Ta = 25C) 1.0 0.8 Relative sensitivity 0.6 0.4 0.2 0 400 500 600 700 Wavelength (nm) 800 900 1000 MTF of main scanning direction (Typ.) 0 1.0 10.0 0.8 Spatial frequency (cycles/mm) 7.1 14.3 21.4 28.6 35.7 Dark voltage rate vs. Ambient temperature (Typ.) H-MTF 0.6 Dark voltage rate 0 0.2 0.4 0.6 0.8 1 0.4 1.00 0.2 0 Normalized spatial frequency =560nm 0.10 0 10 20 30 40 50 60 Ta-Ambient temperature (C) --8-- ILX511 Output voltage rate vs. Integration time (Typ.) 5 2.0 Current consumption rate vs. Clock frequency (Typ.) 1 Current consumption rate 1 10 int-Integration time (ms) 50 1.5 Output voltag rate 1.0 0.5 0.1 0 0 0.5 1.0 Clock frequency (MHz) 1.5 2.0 Offset level vs. VDD (Typ.) 3.2 3.2 Offset level vs. Ambient temperature (Typ.) VOS-Offset level (V) 2.8 VOS-Offset level (V) 4.75 5 VDD (V) 5.25 5.5 3.0 3.0 2.8 2.6 2.6 2.4 4.5 2.4 0 20 40 60 Ta-Ambient temperature (C) --9-- ILX511 Application Circuit (Without S/H mode (Note)) 10/16V 5V 22 21 20 19 + 18 17 16 15 14 13 12 VDD GND VDD VDD VDD GND NC VGG NC 10 SHSW GND VDD 1 Output signal 2 3 4 5 6 7 8 9 11 fROG VOUT GND GND fCLK VDD NC NC NC GND + 3K 2SA1175 CLK ROG 0.01 22/10V Note) This circuit diagram is the case when internal S/H is not used. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party and other right due to same. --10-- ILX511 Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling, be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates use cartons treated for the prevention of static charges. 2) Notes on handling CCD Cer-DIP package The following points should be observed when handling and installing this package. a) (1) Compressive strength: 39N/surface (Do not apply any load more than 0.7 mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm Upper ceramic layer 39N 29N 29N 0.9Nm Lower ceramic layer (1) Low-melting glass (2) (3) (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack because the upper and lower ceramic layers are shielded by low-melting glass. (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with a soldering iron. (3) Rapid cooling or heating. (4) Applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80 C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount image sensors, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. --11-- ILX511 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface blow it off with an air blower. (For dirt stuck through static electricity, ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. 7) Make sure the input pulse should not be -1 V or below. 8) Normal output signal is not obtained immediately after device switch on. Use the output signal added 22500 pulses or above to CLK clock pulse. --12-- ILX511 Package Outline Unit : mm 22pin DIP (400mil) 6.46 0.8 22 41.6 0.5 28.672 (14m x 2048Pixels) 12 5.0 0.5 H 1 No.1 Pixel 11 40.2 1. The height from the bottom to the sensor surface is 2.45 0.3mm. 2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5. 4.0 0.5 2.54 0.51 0.3 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT Cer-DIP TIN PLATING 42 ALLOY 5.2g --13-- 3.65 4.45 0.5 M 0.25 V (AT STAND OFF) 10.16 9.0 10.0 0.5 0 to 9 |
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