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| Agilent HCPL-0738 High Speed CMOS Optocoupler Data Sheet Features * 15 ns typical pulse width distortion * 40 ns maximum prop. delay skew Description The HCPL-0738 is a dual-channel 15 MBd CMOS optocoupler in SOIC-8 package. The HCPL-0738 optocoupler utilizes the latest CMOS IC technology to achieve outstanding performance with very low power consumption. Basic building blocks of HCPL-0738 are high speed LEDs and CMOS detector ICs. * 20 ns typical prop. delay Agilent also offers the same performance in the single channel version, HCPL-0708. Each detector incorporates an integrated photodiode, a high speed transimpedance amplifier, and a voltage comparator with an output driver. * High speed: 15 MBd * + 5 V CMOS compatibility * 10 kV/S minimum common mode rejection * -40 to 100C temperature range * Safety and regulatory approvals -UL recognized (2500 V rms for 1 minute per UL 1577) -CSA component acceptance notice #5. -VDE 0884 (TUV) approved for HCPL-0738 Option 060 Applications * PDP (plasma display panel) * Digital field bus isolation: DeviceNet, SDS, Profibus * Multiplexed data transmission * Computer peripheral interface * Microprocessor system interface * DC/DC converter Functional Diagram Truth Table ANODE 1 1 8 VDD CATHODE 1 2 7 VO 1 LED OFF ON VO, Output H L CATHODE 2 3 6 VO 2 Note: A 0.1 F bypass capacitor must be connected between pins 5 and 8. ANODE 2 4 5 GND CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Selection Guide Small Outline SO-8 HCPL-0738 Ordering Information Specify Part Number followed by Option Number (if desired). Example HCPL-0738 -060 = VDE0884 Option HCPL-0738 -500 = Tape and Reel Packaging Option No Option Code contains 100 units per tube. Option 500 contains 1500 units per reel. Option data sheets available. Contact Agilent Technologies sales representative or authorized distributor. Package Outline Drawing HCPL-0738 Outline Drawing (Small Outline SO-8 Package) 8 7 6 XXX YWW 5 5.994 0.203 (0.236 0.008) TYPE NUMBER (LAST 3 DIGITS) 3.937 0.127 (0.155 0.005) PIN 1 ONE 0.405 0.076 (0.015 0.003) 2 3 4 1.270 BSG (0.050) DATE CODE *5.080 0.127 (0.205 0.005) 7 45 x 0.432 (0.017) 3.175 0.127 (0.125 0.005) 1.524 (0.060) 0 - 7 0.228 0.025 (0.009 0.001) 0.202 0.102 (0.008 0.004) 0.305 MIN. (0.012) *TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH) 5.207 0.254 (0.205 0.010) DIMENSIONS IN MILLIMETERS AND (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX. Solder Reflow Temperature Profile 300 PREHEATING RATE 3C + 1C/-0.5C/SEC. REFLOW HEATING RATE 2.5C 0.5C/SEC. PEAK TEMP. 245C PEAK TEMP. 240C PEAK TEMP. 230C 2.5C 0.5C/SEC. 160C 150C 140C 3C + 1C/-0.5C 30 SEC. 30 SEC. SOLDERING TIME 200C TEMPERATURE (C) 200 100 PREHEATING TIME 150C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 0 50 100 150 200 250 TIME (SECONDS) 2 Regulatory Information The HCPL-0738 has been approved by the following organizations: UL Recognized under UL 1577, component recognition program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA88324. TUV Approved according to VDE 0884/06.92, Certificate R9650938. Insulation and Safety Related Specifications (approval pending) Parameter Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol L(I01) L(I02) Value 4.9 4.8 0.08 CTI 175 IIIa Units mm mm mm Volts Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Insulation thickness between emitter and detector; also known as distance through insulation. DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. All Agilent data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit Absolute Maximum Ratings Parameter Storage Temperature Ambient Operating Temperature Supply Voltage Output Voltage Average Forward Input Current Average Output Current Lead Solder Temperature Solder Reflow Temperature Profile Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltages Input Current (ON) 3 board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There Symbol Minimum Maximum TS -55 125 TA -40 100 VDD 0 6.0 VO -0.5 VDD + 0.5 IF -- 20 IO -- 2 260C for 10 seconds, 1.6 mm below seating plane See Solder Reflow Thermal Profile section Units C C Volts Volts mA mA Symbol TA VDD IF Minimum -40 4.5 10 Maximum 100 5.5 16 Units C V mA Electrical Specifications Over recommended temperature (TA = -40C to +100C) and 4.5 V VDD 5.5 V. All typical specifications are at TA = 25C, V DD = +5 V. Parameter Input Forward Voltage Input Reverse Breakdown Voltage Logic High Output Voltage Logic Low Output Voltage Input Threshold Current Logic Low Output Supply Current Logic High Output Supply Current Symbol VF BVR VOH VOL ITH IDDL IDDH Min. 1.3 5 4.0 Typ. 1.5 Max. 1.8 Units V V V V mA mA mA Test Conditions IF = 12 mA IR = 10 A IF = 0, IO = -20 A IF = 12 mA, IO = 20 A IOL = 20 A IF = 12 mA IF = 0 mA Fig. 1 Notes 5 0.01 4.5 10 8 0.1 8.2 18.0 15.0 2 4 3 Switching Specifications Over recommended temperature (TA = -40C to +100C) and 4.5 V VDD 5.5 V. All typical specifications are at TA = 25C, V DD = +5 V. Parameter Propagation Delay Time to Logic Low Output Propagation Delay Time to Logic High Output Pulse Width Pulse Width Distortion Propagation Delay Skew Output Rise Time (10% - 90%) Output Fall Time (90% - 10%) Common Mode Transient Immunity at Logic High Output Common Mode Transient Immunity at Logic Low Output Symbol tPHL tPLH PW |PWD| tPSK tR tF |CMH| |CML| 10 10 20 25 15 15 Min. 20 11 100 0 Typ. 35 20 Max. 60 60 Units ns ns ns ns ns ns ns kV/S kV/S Test Conditions IF = 12 mA, CL = 15 pF CMOS Signal Levels IF = 12 mA, CL = 15 pF CMOS Signal Levels IF = 12 mA, CL = 15 pF CMOS Signal Levels IF = 12 mA, CL = 15 pF CMOS Signal Levels IF = 0 mA, CL = 15 pF CMOS Signal Levels IF = 12 mA, CL = 15 pF CMOS Signal Levels VCM = 1000 V, TA = 25C, IF = 0 mA VCM = 1000 V, TA = 25C, IF = 12 mA Fig. 5 5 Notes 1 1 15 30 40 5 2 3 4 5 4 Package Characteristics All typicals at T A = 25C. Parameter Input-Output Insulation Symbol I I-O Min. Typ. Max. 1 Units A Test Conditions 45% RH, t = 5 s VI-O = 3 kV DC, TA = 25C RH 50%, t = 1 min., TA = 25C VI-O = 500 V DC f = 1 MHz, TA = 25C Input-Output Momentary Withstand Voltage Input-Output Resistance Input-Output Capacitance VISO RI-O CI-O 2500 1012 0.6 V rms pF Notes: 1. t PHL propagation delay is measured from the 50% level on the rising edge of the input pulse to the 2.5 V level of the falling edge of the VO signal. t PLH propagation delay is measured from the 50% level on the falling edge of the input pulse to the 2.5 V level of the rising edge of the VO signal. 2. PWD is defined as |tPHL - t PLH|. 3. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 4. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 5. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state. IDDH - LOGIC HIGH OUTPUT SUPPLY CURRENT - mA Ith - INPUT THRESHOLD CURRENT - mA 1000 8 7 6 5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 Ith1 Ith2 VDD = 5.0 V IOL = 20 A 10.0 VDD = 5.0 V 9.5 9.0 8.5 Iddh 8.0 7.5 7.0 6.5 6.0 -40 -20 0 20 40 60 80 100 IF - FORWARD CURRENT - mA TA = 25C 100 10 1.0 0.1 0.01 0.001 1.1 IF + VF - 1.2 1.3 1.4 1.5 1.6 VF - FORWARD VOLTAGE - V TA - TEMPERATURE - C TA - TEMPERATURE - C Figure 1. Typical input diode forward characteristic. Figure 2. Typical input threshold current vs. temperature. Figure 3. Typical logic high O/P supply current vs. temperature. IDDL - LOGIC LOW SUPPLY CURRENT - mA 11.6 VDD = 5.0 V tp - PROPAGATION DELAY - ns 50 45 40 35 30 25 20 15 PWD CH 1 10 5 0 VDD = 5.0 V TA = 25 C 5 6 7 8 9 10 11 12 13 14 Tplh CH 1 Tplh CH 2 PWD CH 2 Tphl CH 2 Tphl CH 1 11.4 11.2 11.0 10.8 10.6 10.4 10.2 10.0 9.8 9.6 -40 Iddl -20 0 20 40 60 80 100 TA - TEMPERATURE - C IF - PULSE INPUT CURRENT - mA Figure 4. Typical logic low O/P supply current vs. temperature. Figure 5. Typical switching speed vs. pulse input current. 5 Application Information Bypassing and PC Board Layout The HCPL-0738 optocoupler is extremely easy to use. No external interface circuitry is required because the HCPL-0738 uses high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. As shown in Figure 6, the only external component required for proper operation is the bypass capacitor. Capacitor values should be between 0.01 F and 0.1 F. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. VI1 GND 1 GND 1 VI2 1 2 3 4 8 C 7 6 5 GND 2 VDD VO 1 VO 2 Figure 6. Recommended printed circuit board layout. Propagation Delay, Pulse-Width Distortion, and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the XXX YWW input signal to propagate to the output, causing the output to change from high to low (see Figure 7). Pulse-width distortion (PWD) results when tPLH and t PHL differ in value. PWD is defined as the difference between t PLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of 6 the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same supply voltage, output load, and operating temperature). As illustrated in Figure 8, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, t PSK can determine the maximum parallel data transmission rate. Figure 8 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 7 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The tPSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulse-width distortion and propagation delay skew over the recommended temperature, and power supply ranges. VI 50% INPUTS DATA VO 2.5 V, CMOS tPSK CLOCK VI 50% DATA OUTPUTS tPSK VO 2.5 V, CMOS CLOCK tPSK Figure 7. Propagation delay skew waveform. Figure 8. Parallel data transmission example. 7 www.agilent.com/semiconductors For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (408) 654-8675 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6271 2451 India, Australia, New Zealand: (+65) 6271 2394 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6271 2194 Malaysia, Singapore: (+65) 6271 2054 Taiwan: (+65) 6271 2654 Data subject to change. Copyright (c) 2002 Agilent Technologies, Inc. Obsoletes 5988-4962EN May 3, 2002 5988-6493EN |
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