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GAL20LV8ZD
Low Voltage, Zero Power E2CMOS PLD Generic Array LogicTM Features
* 3.3V LOW VOLTAGE, ZERO POWER OPERATION -- JEDEC Compatible 3.3V Interface Standard -- Interfaces with Standard 5V TTL Devices -- 50A Typical Standby Current (100A Max.) -- 45mA Typical Active Current (55mA Max.) -- Dedicated Power-down Pin * HIGH PERFORMANCE E2CMOS TECHNOLOGY -- TTL Compatible Balanced 8 mA Output Drive -- 15 ns Maximum Propagation Delay -- Fmax = 62.5 MHz -- 10 ns Maximum from Clock Input to Data Output -- UltraMOS(R) Advanced CMOS Technology * E CELL TECHNOLOGY -- Reconfigurable Logic -- Reprogrammable Cells -- 100% Tested/100% Yields -- High Speed Electrical Erasure (<100ms) -- 20 Year Data Retention * EIGHT OUTPUT LOGIC MACROCELLS -- Maximum Flexibility for Complex Logic Designs -- Programmable Output Polarity * PRELOAD AND POWER-ON RESET OF ALL REGISTERS -- 100% Functional Testability * APPLICATIONS INCLUDE: -- Glue Logic for 3.3V Systems -- Ideal for Mixed 3.3V and 5V Systems * ELECTRONIC SIGNATURE FOR IDENTIFICATION
2
Functional Block Diagram
I/CLK I I IMUX
CLK
8 OLMC I 8 DPP OLMC
I/O/Q
I/O/Q
PROGRAMMABLE AND-ARRAY (64 X 40)
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8 OLMC
I/O/Q
I
8
OLMC
I/O/Q
I 8 OLMC I 8 OLMC
OE
I/O/Q
I I
I/O/Q
I IMUX I/OE
Description
The GAL20LV8ZD, at 100 A standby current and 15ns propagation delay provides the highest speed low-voltage PLD available in the market. The GAL20LV8ZD is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. The GAL20LV8ZD utilizes a dedicated power-down pin (DPP) to put the device into standby mode. It has 19 inputs available to the AND array and is capable of interfacing with both 3.3V and standard 5V devices. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
Pin Configuration
PLCC
I/CLK Vcc NC I/O/Q
I
4 DPP I I NC I I I 11 12
I I
I
2
28
I
5
26 25
I/O/Q I/O/Q
7
GAL20LV8ZD Top View
23
I/O/Q NC
9
21
I/O/Q I/O/Q
14
NC GND
16
I/OE I
19 18
I/O/Q
I/O/Q
Copyright (c) 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
December 1997
20lv8zd_03
1
Specifications GAL20LV8ZD
GAL20LV8ZD Ordering Information
Commercial Grade Specifications
Tpd (ns)
15 25
Tsu (ns)
12 15
Tco (ns)
10 15
Icc (mA)
55 55
Isb (A)
100 100
Ordering #
GAL20LV8ZD-15QJ GAL20LV8ZD-25QJ
Package
28-Lead PLCC 28-Lead PLCC
Part Number Description
XXXXXXXX _ XX X XX
Device Name GAL20LV8ZD (Zero Power DPP) Speed (ns) Active Power Q = Quarter Power
Grade Blank = Commercial Package J = PLCC
2
Specifications GAL20LV8ZD
Output Logic Macrocell (OLMC)
The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. There are three global OLMC configuration modes possible: simple, complex, and registered. Details of each of these modes is illustrated in the following pages. Two global bits, SYN and AC0, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC1 bit of each of the macrocells controls the input/output configuration. These two global and 16 individual architecture bits define all possible configurations in a GAL20LV8ZD. The information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits.
Compiler Support for OLMC
Software compilers support the three different global OLMC modes as different device types. Most compilers also have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 2 and pin 16 are permanently configured as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. In complex mode pin 2 and pin 16 become dedicated inputs and use the feedback paths of pin 26 and pin 18 respectively. Because of this feedback path usage, pin 26 and pin 18 do not have the feedback option in this mode. In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins ( pins 21 and 23) will not have the feedback option as these pins are always configured as dedicated combinatorial output. When using the standard GAL20V8 JEDEC fuse pattern generated by the logic compilers for the GAL20LV8ZD, special attention must be given to pin 5 (DPP) to make sure that it is not used as one of the functional inputs.
3
Specifications GAL20LV8ZD
Registered Mode
In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. Architecture configurations available in this mode are similar to the common 20R8 and 20RP4 devices with various permutations of polarity, I/O and register placement. All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or I/ O. Up to eight registers or up to eight I/Os are possible in this mode. Dedicated input or output functions can be implemented as subsets of the I/O function. Registered outputs have eight product terms per output. I/Os have seven product terms per output. Pin 5 is used as dedicated power-down pin on GAL20LV8ZD. It cannot be used as functional input. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page.
CLK
Registered Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this output configuration. - Pin 2 controls common CLK for the registered outputs. - Pin 16 controls common OE for the registered outputs. - Pin 2 & Pin 16 are permanently configured as CLK & OE for registered output configuration.
D
Q Q
XOR
OE
Combinatorial Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this output configuration. - Pin 2 & Pin 16 are permanently configured as CLK & OE for registered output configuration.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
4
Specifications GAL20LV8ZD
Registered Mode Logic Diagram
PLCC Package Pinout
2
2640
0
4
8
12
16
20
24
28
32
36
PTD
3
0000
27
OLMC
XOR-2560 AC1-2632
26
0280
4
0320
OLMC
25
XOR-2561 AC1-2633
0600
5
Power Management Control
0640
OLMC
24
XOR-2562 AC1-2634
0920
6
0960
OLMC
23
XOR-2563 AC1-2635
1240
7
1280
OLMC
XOR-2564 AC1-2636
21
1560
9
1600
OLMC
XOR-2565 AC1-2637
20
1880
10
1920
OLMC
XOR-2566 AC1-2638
19
2200
11
2240
OLMC
XOR-2567 AC1-2639
18
2520
12 13
17
OE
2703
16
64-USER ELECTRONIC SIGNATURE FUSES 2568, 2569, .... .... 2630, 2631 Byte7 Byte6 .... .... Byte1 Byte0 MSB LSB
SYN-2704 AC0-2705
5
Specifications GAL20LV8ZD
Complex Mode
In the Complex mode, macrocells are configured as output only or I/O functions. Architecture configurations available in this mode are similar to the common 20L8 and 20P8 devices with programmable polarity in each macrocell. Up to six I/Os are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the I/O function. The two outer most macrocells (pins 18 & 26) do not have input capability. Designs requiring eight I/Os can be implemented in the Registered mode. All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins 2 and 16 are always available as data inputs into the AND array. Pin 5 is used as dedicated power-down pin on GAL20LV8ZD. It cannot be used as functional input. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page.
Combinatorial I/O Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1 has no effect on this mode. - Pin 19 through Pin 25 are configured to this function.
XOR
Combinatorial Output Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1 has no effect on this mode. - Pin 18 and Pin 26 are configured to this function.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
6
Specifications GAL20LV8ZD
Complex Mode Logic Diagram
PLCC Package Pinout
2
2640
0
4
8
12
16
20
24
28
32
36
PTD
3
0000
27
OLMC
0280
26
4
0320
XOR-2560 AC1-2632
OLMC
25
XOR-2561 AC1-2633
0600
5
Power Management Control
0640
OLMC
24
XOR-2562 AC1-2634
0920
6
0960
OLMC
1240
23
7
1280
XOR-2563 AC1-2635
OLMC
1560
21
9
1600
XOR-2564 AC1-2636
OLMC
XOR-2565 AC1-2637
20
1880
10
1920
OLMC
XOR-2566 AC1-2638
19
2200
11
2240
OLMC
2520
18
12 13
XOR-2567 AC1-2639
17 16
2703
64-USER ELECTRONIC SIGNATURE FUSES 2568, 2569, .... .... 2630, 2631 Byte7 Byte6 .... .... Byte1 Byte0 MSB LSB
SYN-2704 AC0-2705
7
Specifications GAL20LV8ZD
Simple Mode
In the Simple mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common 14L8 and 16P6 devices with many permutations of generic output polarity or input choices. All outputs in the simple mode have a maximum of eight product terms that can control the logic. In addition, each output has programmable polarity. Pins 2 and 16 are always available as data inputs into the AND array. The center two macrocells (pins 21 & 23) cannot be used in the input configuration. Pin 5 is used as dedicated power-down pin on GAL20LV8ZD. It cannot be used as functional input. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram.
Vcc
Combinatorial Output with Feedback Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - All OLMC except pins 21 & 23 can be configured to this function.
XOR
Combinatorial Output Configuration for Simple Mode
Vcc
XOR
- SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - Pins 21 & 23 are permanently configured to this function.
Dedicated Input Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this configuration. - All OLMC except pins 21 & 23 can be configured to this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
8
Specifications GAL20LV8ZD
Simple Mode Logic Diagram
PLCC Package Pinouts
2
2640
0
4
8
12
16
20
24
28
32
36
PTD
3
0000
27
OLMC
XOR-2560 AC1-2632
26
0280
4
0320
OLMC
XOR-2561 AC1-2633
25
0600
5
Power Management Control
0640
OLMC
XOR-2562 AC1-2634
24
0920
6
0960
OLMC
XOR-2563 AC1-2635
23
1240
7
1280
OLMC
XOR-2564 AC1-2636
21
1560
9
1600
OLMC
XOR-2565 AC1-2637
20
1880
10
1920
OLMC
XOR-2566 AC1-2638
19
2200
11
2240
OLMC
XOR-2567 AC1-2639
18
2520
12
17
13
16
2703
64-USER ELECTRONIC SIGNATURE FUSES 2568, 2569, .... .... 2630, 2631 Byte7 Byte6 .... .... Byte1 Byte0 MSB LSB
SYN-2704 AC0-2705
9
Specifications GAL20LV8ZD
Absolute Maximum Ratings(1)
Supply voltage VCC .................................... -0.5 to +5.6V Input voltage applied ................................. -0.5 to +5.6V Off-state output voltage applied ................ -0.5 to +5.6V Storage Temperature ................................. -65 to 150C Ambient Temperature with Power Applied ......................................... -55 to 125C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
Recommended Operating Conditions
Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75C Supply voltage (VCC) with Respect to Ground ......................... +3.0 to +3.6V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current 0V VIN VIL (MAX.) (VCC-0.2)V VIN VCC VCC VIN 5.25V CONDITION MIN.
Vss - 0.5
TYP.2 -- -- -- -- -- -- -- -- -- -- -- -- --
MAX. 0.8 5.25
UNITS V V A A mA V V V V V mA mA mA
VIL VIH IIL IIH VOL VOH
2.0 -- -- -- -- -- 2.4 Vcc-0.45 Vcc-0.2 -- -- VCC = 3.3V VOUT = GND TA = 25C -30
-10
10 1 0.5 0.2 -- -- -- 8 -8 -130
Output Low Voltage
IOL = MAX. Vin = VIL or VIH IOL = 0.5 mA Vin = VIL or VIH
Output High Voltage
IOH = MAX. Vin = VIL or VIH IOH = -0.5 mA Vin = VIL or VIH IOH = -100A Vin = VIL or VIH
IOL IOH IOS1
Low Level Output Current High Level Output Current Output Short Circuit Current
COMMERCIAL ISB Stand-by Power
Supply Current
VIL = GND VIH = Vcc Outputs Open
ZD -15/-25
--
50
100
A
ICC
Operating Power Supply Current
VIL = 0.5V VIH = 3.0V ftoggle = 15 MHz Outputs Open
ZD -15/-25
--
45
55
mA
1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2) Typical values are at Vcc = 3.3V and TA = 25 C
10
Specifications GAL20LV8ZD
AC Switching Characteristics
Over Recommended Operating Conditions
COM PARAM TEST COND.1 COM
DESCRIPTION Input or I/O to Combinatorial Output Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Fdbk before Clk Hold Time, Input or Fdbk after Clk Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled OE to Output Enabled Input or I/O to Output Disabled OE to Output Disabled 3 2 --
-15
-25 UNITS ns ns ns ns ns MHz
MIN. MAX. MIN. MAX. 15 10 8 -- -- -- 3 2 -- 15 0 33.3 25 15 10 -- -- --
tpd tco tcf2 tsu th
A A -- -- -- A
12 0 45.5
fmax3
A A
50 62.5
-- --
40 41.6
-- --
MHz MHz
twh twl ten tdis
-- -- B B C C
8 8 -- -- -- --
-- -- 17 16 18 17
12 12 -- -- -- --
-- -- 25 20 25 20
ns ns ns ns ns ns
1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section.
Capacitance (TA = 25C, f = 1.0 MHz)
SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance TYPICAL 8 8 UNITS pF pF TEST CONDITIONS VCC = 3.3V, VI = 0V VCC = 3.3V, VI/O = 0V
11
Specifications GAL20LV8ZD
Dedicated Power-Down Pin Specications
Over Recommended Operating Conditions
COM PARAMETER COM
TEST COND1. -- --
DESCRIPTION DPP Pulse Duration High DPP Pulse Duration Low 40 30
-15 MIN. MAX. -- --
-25 MIN. MAX. 40 40 -- -- UNITS ns ns
twhd twld tivdh tgvdh tcvdh tdhix tdhgx tdhcx tixdl tgxdl tcxdl tdliv tdlgv tdlcv tdlov
ACTIVE TO STANDBY -- -- -- -- -- -- Valid Input before DPP High Valid OE before DPP High Valid Clock before DPP High Input Don't Care after DPP High OE Don't Care after DPP High Clock Don't Care after DPP High 0 0 0 -- -- -- -- -- -- 15 15 15 0 0 0 -- -- -- -- -- -- 25 25 25 ns ns ns ns ns ns
STANDBY TO ACTIVE -- -- -- -- -- -- A Input Don't Care before DPP Low OE Don't Care before DPP Low Clock Don't Care before DPP Low DPP Low to Valid Input DPP Low to Valid OE DPP Low to Valid Clock DPP Low to Valid Output -- -- -- 20 20 30 5 0 0 0 -- -- -- 45 -- -- -- 25 25 35 5 0 0 0 -- -- -- 45 ns ns ns ns ns ns ns
1) Refer to Switching Test Conditions section.
Dedicated Power-Down Pin Timing Waveforms
DPP tivdh INPUT or I/O FEEDBACK tgvdh OE tcvdh CLK
tc o
tpd,ten,tdis
tdhix
tixdl
tdliv
tdhgx tgxdl
tdlgv
tdhcx
tcxdl
tdlcv
tdlov
OUTPUT
12
Specifications GAL20LV8ZD
Switching Waveforms
INPUT or I/O FEEDBACK
INPUT or I/O FEEDBACK VALID INPUT
VALID INPUT
tsu
CLK
th
tpd
COMBINATIONAL OUTPUT
tco
REGISTERED OUTPUT
Combinatorial Output
1/fmax (external fdbk)
INPUT or I/O FEEDBACK
Registered Output
tdis
COMBINATIONAL OUTPUT
ten
OE
tdis
Input or I/O to Output Enable/Disable
REGISTERED OUTPUT
ten
OE to Output Enable/Disable
twh
CLK 1/fmax (w/o fb)
twl
CLK 1/fmax (internal fdbk)
tcf
REGISTERED FEEDBACK
tsu
Clock Width
fmax with Feedback
13
Specifications GAL20LV8ZD
fmax Descriptions
CL K
LOGIC ARR AY
R EG I S T E R
CLK
LOGIC ARRAY
ts u
tc o
REGISTER
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured tsu and tco.
CLK
tcf tpd
fmax with Internal Feedback 1/(tsu+tcf)
LOGIC ARRAY REGISTER
tsu + th
fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Switching Test Conditions
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 2ns 10% - 90% 1.5V 1.5V See Figure
Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd.
+3.3V
R1
3-state levels are measured 0.5V from steady-state active level. 3-state to active transitions are measured at (Voh - 0.5) V and (Vol + 0.5) V. Output Load Conditions (see figure) Test Condition A B C Active High Active Low Active High Active Low R1 270 270 270 270 270 R2 220 220 220 220 220 CL 35pF 35pF 35pF 5pF 5pF
FROM OUTPUT (O/Q) UNDER TEST
TEST POINT
R2
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
14
Specifications GAL20LV8ZD
Electronic Signature
An electronic signature word is provided in every GAL20LV8ZD device. It contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter checksum.
Output Register Preload
When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because, in system operation, certain events occur that may throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. The GAL20LV8ZD devices includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically.
Security Cell
A security cell is provided in the GAL20LV8ZD devices to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The electronic signature data is always available to the user, regardless of the state of this security cell.
Input Buffers
GAL20LV8ZD devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices.
Device Programming
GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers. Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle.
Dedicated Power-Down Pin
The GAL20LV8ZD uses pin 5 as the dedicated power-down signal to put the device in to the power-down state. DPP is an active high signal where a logic high driven on this signal puts the device into power-down state. Input pin 5 cannot be used as a logic function input on this device.
15
Specifications GAL20LV8ZD
Power-Up Reset
Vcc (min.)
Vcc
tsu
CLK
twl tpr
INTERNAL REGISTER Q - OUTPUT
Internal Register Reset to Logic "0"
FEEDBACK/EXTERNAL OUTPUT REGISTER
Device Pin Reset to Logic "1"
Circuitry within the GAL20LV8ZD provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 10s MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown below. Because of the
asynchronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the GAL20LV8ZD. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements.
Input/Output Equivalent Schematic
PIN
Feedback
PIN
Vcc
Vcc
ESD Protection Circuit
Vcc
Tri-State Control
Vcc
PIN
Data Output
PIN
ESD Protection Circuit
Feedback (To Input Buffer)
Typical Input
Typical Output
16
Specifications GAL20LV8ZD
Typical AC and DC Characteristics
Normalized Tpd vs Vcc
1.2 1.2
Normalized Tco vs Vcc
1.2
Normalized Tsu vs Vcc
Normalized Tpd
Normalized Tco
1.1
Normalized Tsu
PT H->L PT L->H
1
RISE 1.1 FALL
PT H->L
1.1
PT L->H
1
1
0.9
0.9
0.9
0.8 3.00 3.15 3.30 3.45 3.60
0.8 3.00
3.15
3.30
3.45
3.60
0.8 3.00
3.15
3.30
3.45
3.60
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs Temp
1.3 1.3
Normalized Tco vs Temp
1.4
Normalized Tsu vs Temp
Normalized Tpd
Normalized Tsu
1.2 1.1 1 0.9 0.8 0.7
Normalized Tco
PT H->L PT L->H
1.2 1.1 1 0.9 0.8 0.7
RISE FALL
1.3 1.2 1.1 1 0.9 0.8 0.7
PT H->L PT L->H
0
-55
-25
0
25
50
75
100
125
-55
-25
25
50
75
100
125
0
100
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd vs # of Outputs Switching
0 0
Delta Tco vs # of Outputs Switching
Delta Tpd (ns)
Delta Tco (ns)
-0.25
-0.1 -0.2 -0.3 -0.4 -0.5
-0.5
RISE
-0.75
RISE FALL
FALL
-1 1 2 3 4 5 6 7 8
1
2
3
4
5
6
7
8
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output Loading
12 10 12
Delta Tco vs Output Loading
RISE
10
RISE FALL
Delta Tpd (ns)
Delta Tco (ns)
8 6 4 2 0 -2 0 50
FALL
8 6 4 2 0 -2 -4 0 50
100
150
200
250
300
100
150
200
250
300
Output Loading (pF)
Output Loading (pF)
17
125
-55
-25
25
50
75
Specifications GAL20LV8ZD
Typical AC and DC Characteristics
Vol vs Iol
1.5 1.25 3 2.5
Voh vs Ioh
3 2.975
Voh vs Ioh
Voh (V)
0.75 0.5 0.25 0 0.00 20.00 40.00 60.00 80.00
1.5 1 0.5 0 0.00
Voh (V)
10.00 20.00 30.00 40.00 50.00
Vol (V)
1
2
2.95 2.925 2.9 2.875 2.85 0.00
1.00
2.00
3.00
4.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
1.30 1.20 1.10 1.00 0.90 0.80 0.70 3.00 1.2 1.15 1.1 1.05 1 0.95 0.9 3.15 3.30 3.45 3.60 -55
Normalized Icc vs Temp
2.00 1.75 1.50 1.25 1.00 0.75 -25 0 25 50 75 100 125 0
Normalized Icc vs Freq.
Normalized Icc
Normalized Icc
Normalized Icc
25
50
75
100
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Delta Icc vs Vin (1 input)
4 0 10 20 30
Input Clamp (Vik)
Delta Icc (mA)
3
Iik (mA)
0.50 1.00 1.50 2.00 2.50 3.00 3.50
40 50 60 70 80 90
2
1
0 0.00
100 -1.50 -1.20 -0.90 -0.60 -0.30 0.00
Vin (V)
Vik (V)
18

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