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August 2004 rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer
ASM4SSTVF32852
Features
Differential clock signals. Supports SSTL_2 class II specifications on inputs and outputs. Low voltage operation. VDD = 2.3V to 2.7V.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held at a logic "Low" level during power-up. In the DDR DIMM application, RESETB is specified to be asynchronous with respect to CLK/CLKB. Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state, the register will be cleared and the outputs will be driven to a logic "Low" level quickly relative to the time to disable the differential input receivers. This ensures there are no "glitches" on any output. However, when coming out of low power standby state, the register will become active quickly relative to the time taken to enable the differential input receivers. When the data inputs are at a logic level "Low" and the clock is stable during the "Low-to-High" transition of RESETB until the input receivers are fully enabled, the design ensures that the outputs will remain at a logic "Low" level.
Available in 114 ball BGA package. Industrial temperature range also available.
Product Description
The 24-Bit to 48-Bit ASM4SSTVF32852 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels except for the LVCMOS RESETB input. Data flow from D to Q is controlled by the differential clock (CLK/CLKB) and a control signal (RESETB). The positive edge of CLK is used to trigger the data flow, and CLKB is used to maintain sufficient noise margins, whereas the RESETB, an LVCMOS asynchronous signal is intended for use at the time of power-up only. The ASM4SSTVF32852 supports a low power standby mode of operation. A logic "Low" level at RESETB, assures that all internal registers and outputs (Q) are reset to a logic "Low" state, and that all input receivers, data (D) buffers, and clock (CLK/CLKB) are switched off. Please note that RESETB must always be supported with a LVCMOS levels at a valid logic state since VREF may not be stable during power-up.
Applications

DDR Memory Modules. Provides complete DDR DIMM logic solution with ASM5CVF857, ASM4SSTVF16857 and ASM4SSTVF16859. SSTL_2 compatible data registers.
Alliance Semiconductor 2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.
August 2004 rev 2.0 Block Diagram
ASM4SSTVF32852
CLK CLKB
RESETB
R CLK
Q1A
D1 VREF
D1
Q1B
To 23 Other Channels
Pin Configurations
1 A B C D E F G H J K L M N P R T U V W 2 3 4 5 6
114-Pin Ball BGA
DDR 24-Bit to 48-Bit Registered Buffer
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August 2004 rev 2.0 Pin Description
Pin # R1, P1, N1, N2, M1, L2, L1, K1, K2, J2, J1, H1, G1, G2, F1, F2, E1, D1, D2, C1, C2, B1, A1, A2 R6, P6, N6,N5,M6, L5, L6, K6, K5, J5, J6, H6, G6, G5, F6, F5, E6, D6, D5, C6, C5, B6, A6, A5 E2, B3, D3, G3, J3, L3, M3, P3, B4, D4, G4, J4, L4, M4, P4, E5 B2, M2, P2, C3, E3, F3, H3, K3, N3, C4, E4, F4, H4, K4, N4, B5, M5, P5 W4, V4, U4, W5, W6, V5, T4, V6, U6, U5, T6, T5, W3, V3, U3, W2, W1, V2, T3, V1, U1, U2, T1, T2 A3 A4 H2, H5, R2, R5 R3 R4 Pin Name Type
ASM4SSTVF32852
Description
Q (24:1)A
O
Data output.
Q (24:1)B
O
Data output.
GND
P
Ground.
VDDQ
P
Output supply voltage, 2,5V nominal.
D(24:1) CLK CLKB VDD RESETB VREF
I I I P I I
Data input. Positive master clock input. Negative master clock input. Core supply voltage, 2.5V nominal. Reset (Active Low). Input reference, 1.25V nominal.
DDR 24-Bit to 48-Bit Registered Buffer
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August 2004 rev 2.0 Pin Configuration Assignments
1 A B C D E F G H J K L M N P R T U V W Q2A Q3A Q5A Q7A Q8A Q10A Q12A Q13A Q14A Q17A Q18A Q20A Q22A Q23A Q24A D2 D4 D5 D8 2 Q1A VDDQ Q4A Q6A GND Q9A Q11A VDD Q15A Q16A Q19A VDDQ Q21A VDDQ VDD D1 D3 D7 D9 3 CLK GND VDDQ GND VDDQ VDDQ GND VDDQ GND VDDQ GND GND VDDQ GND RESETB D6 D10 D11 D12 4 CLKB GND VDDQ GND VDDQ VDDQ GND VDDQ GND VDDQ GND GND VDDQ GND VREF D18 D22 D23 D24 5 Q1B VDDQ Q4B Q6B GND Q9B Q11B VDD Q15B Q16B Q19B VDDQ Q21B VDDQ VDD D13 D15 D19 D21
ASM4SSTVF32852
6 Q2B Q3B Q5B Q7B Q8B Q10B Q12B Q13B Q14B Q17B Q18B Q20B Q22B Q23B Q24B D14 D16 D17 D20
DDR 24-Bit to 48-Bit Registered Buffer
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August 2004 rev 2.0 Truth Table1
Inputs RESET# L H H H CLK X or floating L or H CLK# X or floating L or H D X or floating H L X
ASM4SSTVF32852
Q Outputs Q L H L Q0
2
Note: 1. H=High signal level, L=Low signal level, = transition from low to high, = transition from high to low, X = don't care 2. Output level before the indicated steady state input conditions were established.
Absolute Maximum Ratings
Parameter Storage Temperature Supply Voltage Input Voltage1 Output Voltage1,2 Input Clamp Current Output Clamp Current Continuous Output Current VDD, VDDQ or GND current/pin Package Thermal Impedance3 Min -65 -0.5 -0.5 -0.5 50 50 50 100 55 Max +150 3.6 VDD + 0.5 VDD + 0.5 Unit C V V V mA mA mA mA C/W
Note: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level V0 > VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51. These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability.
DDR 24-Bit to 48-Bit Registered Buffer
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August 2004 rev 2.0 Recommended Operating Conditions
Guaranteed by design. Not 100% tested in production. Parameter VDD VDDQ VREF VTT VI VIH(DC) VIH(AC) VIL(DC) VIL(AC) VIH VIL VICR VID VIX IOH IOl TA Supply voltage Output supply voltage Reference voltage Termination voltage Input voltage DC input high voltage AC input high voltage DC input low voltage AC input low voltage Input high voltage level RESETB Input low voltage level Common mode input range Differential input voltage CLK CLKB 0.97 0.36 (VDDQ/2) - 0.2 1.7 Data Inputs Description Min 2.3 2.3 1.15 VREF - 0.04 0 VREF + 0.15 VREF + 0.31 Typ 2.5 2.5 1.25 VREF
ASM4SSTVF32852
Max 2.7 2.7 1.35 VREF + 0.04 VDDQ
Unit V V V V V V V
VREF - 0.15 VREF - 0.31
V V V
0.7 1.53
V V V
Cross-point voltage of differential clock pair High-level output current Low-level output current Operating free-air temperature
(VDDQ/2) +0.2 -19 19
V mA mA C
0
70
DDR 24-Bit to 48-Bit Registered Buffer
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August 2004 rev 2.0 DC Electrical Characteristics
TA = 0C to 70C, VDD = 2.5 0.2V, and VDDQ = 2.50.2V (unless otherwise stated) Guaranteed by design. Not 100% production tested. Symbol
VIK
ASM4SSTVF32852
Parameter
II = -18 mA
Test conditions
VDDQ
2.3 V 2.3 V to 2.7 V 2.3 V 2.3 V to 2.7 V 2.3 V 2.7 V
Min
Typ
Max
-1.2
Units
V V V
IOH = -100 A VOH IOH = -16 mA IOL = 100 A VOL IOL = 16 mA II All inputs Standby (static) IDD Operating (static) VI = VIH(AC) or VIL(AC) , RESETB = VDD RESETB = VDD, VI = VIH(AC) or VIL(AC) , CLK and CLKB switching 50% duty cycle RESETB = VDD, VI = VIH(AC) or VIL(AC), CLK and CLKB = switching 50% duty cycle; One data input switching at half clock frequency, 50% duty cycle IOH = -20 mA IO = 0 VI = VDD or GND
VDD - 0.2 2.05 0.2 0.20 5
V V A
RESETB = GND
0.01
A
40
mA
Dynamic operating (clock only) IDDD Dynamic operating (per each data input)
2.5V
35
A/clock MHz
/clock 7 MHz/data input
rOH
Output high
2.3 V to 2.7 V
12
rOL
Output low
IOL = 20 mA
2.3 V to 2.7 V
10
|rOH - rOL| rO(D) each separate bit Data inputs Ci CLK & CLKB VI = VREF 350 mV, VICR = 1.25 V, VI(PP) = 360 mV 2.5 V 2.5 3.5 pF 2.5 V 2.5 3.5 pF IO = 20 mA, T A = 25 C 2.5 V 4
DDR 24-Bit to 48-Bit Registered Buffer
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August 2004 rev 2.0 Timing Requirements
(Over recommended operating free-air temperature range, unless otherwise noted).
ASM4SSTVF32852
Symbol
Parameters
VDD = 2.5V0.2V Min Max 200 1.9 2.7 4.5
Unit
fCLOCK TPD TRST tS
Clock frequency Clock to output time Reset to output time Setup time, fast slew rate 2,4 Setup time, slow slew rate 3,4 Data before CLK, CLKB 0.5 0.7 Data after CLK, CLKB 0.3 0.5 1
MHz ns ns ns ns
th
Hold time, fast slew rate 2,4 Hold time, slow slew rate 3,4
ns ns
tSL
Output slew rate
4
V/ns
Note: 1. Guaranteed by design, not 100% tested in production. 2. For data signal input slew rate >= 1V/ns 3. For data signal input slew rate >= 0.5 V/ns and < 1V/ns 4. CLK,CLKB signals input slew rates are >=1V/ns
Switching Characteristics
(Over recommended operating free-air temperature range unless otherwise noted.)
Symbol
From (input)
To (output)
VDD = 2.5 V 0.2 V Min Typ - Max - 2.7 - 4.5
Units
fmax tPD tphl CLK, CLKB RESETB Q Q
200 1.9 -
MHz ns ns
DDR 24-Bit to 48-Bit Registered Buffer
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August 2004 rev 2.0
ASM4SSTVF32852
Parameter Measurement Information (VDD = 2.5 V 0.2V)
VTT RL = 50 From output under test Test point CL = 30 pF1 Load circuit
1
CL includes probe and jig capacitance.
Voltage and Current Waveforms
In the following waveforms, note that all input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Zo = 50 , input slew rate = 1 V/ns 20% (unless otherwise specified). The outputs are measured one at a time with one transition per measurement. VTT = VREF = VDDQ/2. VIH = VREF + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. VIL = VREF - 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. tPLH and tPHL are the same as tpd.
Input active and inactive times LVCMOS RESETB VDD 0V tinact 10%
1
Input
IDD
1
VDD/2
VDD /2 tact 90% or GND, and I O = 0 mA.
IDDH IDDL
IDD tested with clock and data inputs held at V
DD
Pulse duration
tw Input
Setup and hold times
VREF
VREF
VIH VIL
VI(pp) Timing input ts Input VREF VICR th VREF VIH VIL
DDR 24-Bit to 48-Bit Registered Buffer
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August 2004 rev 2.0 Propagation delay times
VI(pp) Timing input VICR tPLH VTT VICR tPHL VTT
ASM4SSTVF32852
VOH VOL
Output
LVCMOS RESETB Input VDD/2 tPHL Output VTT
VIH VIL VOH VOL
DDR 24-Bit to 48-Bit Registered Buffer
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August 2004 rev 2.0 Package Dimensions 114-Pin Ball BGA
ASM4SSTVF32852
C A1 T b (REF)
Numeric Designations for Horizontal Grid 4 3 2 1 A B C D Alpha Designations for Vertical Grid (Letters I, O, Q & S are not used)
D
d (TYP)
-e-
TYP
E
h (TYP) c (REF) -eTYP
D 16.00 BSC
E 5.50 BSC
T Min/Max 1.30/1.50
e 0.80 BSC
BALL GRID HORIZ 6 VERT 19 TOTAL 114
d 0.46
h Min/Max 0.31/0.41
REF. DIMENSIONS b 0.80 c 0.75
DDR 24-Bit to 48-Bit Registered Buffer
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August 2004 rev 2.0 Ordering Codes
ASM4SSTVF32852
Ordering Number
Marking
Package Type
Quantity per reel
Temperature
ASM4SSTVF32852-114BT ASM4SSTVF32852-114BR ASM4ISSTVF32852-114BT ASM4ISSTVF32852-114BR
AS4SSTVF32852B AS4SSTVF32852B AS4ISSTVF32852B AS4ISSTVF32852B
114-pin Ball, BGA, tray/tube 114-pin Ball, BGA, tape and reel 114-pin Ball, BGA, tray/tube 114-pin Ball, BGA, tape and reel 2500 2500
0C to 70C 0C to 70C -40C to +85C -40C to +85C
DDR 24-Bit to 48-Bit Registered Buffer
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August 2004 rev 2.0
ASM4SSTVF32852
Alliance Semiconductor Corporation 2595, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com
Copyright y Alliance Semiconductor All Rights Reserved Advance Information Part Number: ASM4SSTVF32852 Document Version: v1.1
(c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
DDR 24-Bit to 48-Bit Registered Buffer
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