View AD9617_184182.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a
FEATURES Usable Closed-Loop Gain Range: 1 to 40 Low Distortion: -67 dBc (2nd) at 20 MHz Small Signal Bandwidth: 190 MHz (AV = +3) Large Signal Bandwidth: 150 MHz at 4 V p-p Settling Time: 10 ns to 0.1%; 14 ns to 0.02% Overdrive and Output Short Circuit Protected Fast Overdrive Recovery DC Nonlinearity 10 ppm APPLICATIONS Driving Flash Converters D/A Current-to-Voltage Converters IF, Radar Processors Baseband and Video Communications Photodiode, CCD Preamps
Low Distortion, Precision, Wide Bandwidth Op Amp AD9617
PIN CONFIGURATION
NC 1 -INPUT 2 +INPUT 3 -VS 4
AD9617
8
*
7 +VS 6 OUTPUT 5
**
NC = NO CONNECT *OPTIONAL +VS **OPTIONAL -VS NOTE: FOR BEST SETTLING TIME AND DISTORTION PERFORMANCE, USE OPTIONAL SUPPLY CONNECTIONS. PERFORMANCE INDICATED IN SPECIFICATIONS IS BASED ON SUPPLY CONNECTIONS TO THESE PINS.
GENERAL DESCRIPTION
The AD9617 is a current feedback amplifier which utilizes a proprietary architecture to produce superior distortion and dc precision. It achieves this along with fast settling, very fast slew rate, wide bandwidth (both small signal and large signal) and exceptional signal fidelity. The device achieves -67 dBc 2nd harmonic distortion at 20 MHz while maintaining 190 MHz small signal and 150 MHz large signal bandwidths. These attributes position the AD9617 as an ideal choice for driving flash ADCs and buffering the latest generation of DACs. Optimized for applications requiring gain between 1 to 15, the AD9617 is unity gain stable without external compensation.
The AD9617 offers outstanding performance in high fidelity, wide bandwidth applications in instrumentation ranging from network and spectrum analyzers to oscilloscopes, and in military systems such as radar, SIGINT and ESM systems. The superior slew rate, low overshoot and fast settling of the AD9617 allow the device to be used in pulse applications such as communications receivers and high speed ATE. Most monolithic op amps suffer in these precision pulse applications due to slew rate limiting. The AD9617J operates over the range of 0C to +70C and is available in either an 8-lead plastic DIP or an 8-1ead plastic small outline package (SOIC).
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD9617-SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltages ( VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . Vs Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3 V Continuous Output Current2 . . . . . . . . . . . . . . . . . . . . . 70 mA Operating Temperature Ranges AD9617JN/JR . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Storage Temperature AD9617JN/JR . . . . . . . . . . . . . . . . . . . . . -65C to +125C Junction Temperature3 AD9617JN/JR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Lead Soldering Temperature (10 Seconds) . . . . . . . . . +300C
NOTES 1 Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Output is short circuit protected to ground, but not to supplies. Continuous short circuit to ground may affect device reliability. 3 Typical thermal impedances (part soldered onto board): Plastic DIP: JA = 140C/W; JC = 30C/W. SOIC Package: JA = 155C/W; JC = 40C/W.
DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, A = +3;
V
VS =
5 V; RF = 400
; RLOAD = 100
)
Units
Parameter Input Offset Voltage Input Offset Voltage TC 2 Input Bias Current2 Inverting Noninverting Input Bias Current TC2 Noninverting Inverting Input Resistance Noninverting Input Capacitance Noninverting Common-Mode Input Range3 Common-Mode Rejection Ratio 4 Power Supply Rejection Ratio Open Loop Gain TO Nonlinearity Output Voltage Range Output Impedance Output Current (50 Load)
1, 2
Conditions
Test Temp Level +25C I Full IV +25C I +25C I Full Full IV IV
AD9617JN/JR AD9617AQ/SQ* Min Typ Max Min Typ Max -1.1 -4 -50 -25 -50 -50 +0.5 +2.2 -1.1 +3 +25 -4 0 +5 +30 +50 60 1.4 1.7 44 48 48 1.5 1.5 1.8 48 51 51 1.4 1.7 44 48 48 +50 +35 -50 -25 +0.5 +2.2 +3 +25 0 +5 +30 +50 60 1.5 1.5 1.8 48 51 51 +50 +35 +125 +150
AD9617BQ/TQ* Min Typ Max +0.0 -4 -25 -15 -50 -50
+0.5 +1.35 mV +3 +25 V/C 0 +5 +30 +50 60 +25 +20 +125 +150 A A nA/C nA/C k pF V V dB dB dB k ppm V mA mA
+125 -50 +150 -50
+25C V +25C Full +25C +25C +25C +25C V II II II II II V IV II V II II
T = TMAX T = TMIN to +25C T = TMIN to TMAX T = TMIN to +25C VS = 5% At DC At DC At DC T = +25C to TMAX T = TMIN
1.4 1.7 44 48 48
1.5 1.5 1.8 48 51 51 500 10 +3.8 0.07
500 10 3.4 3.8 0.07 60 50
500 10 3.4 3.8 0.07 60 50
3.4 60 50
NOTES *Pending obsoletion: last-time buy October 25, 1999. 1 Measured with respect to the inverting input. 2 Typical is defined as the mean of the distribution. 3 Measured in voltage follower configuration. 4 Measured with V IN = +0.25 V. Specifications subject to change without notice.
-2-
REV. B
AD9617 AC ELECTRICAL CHARACTERISTICS
Parameter FREQUENCY DOMAIN Bandwidth (-3 dB) Small Signal Large Signal Bandwidth Variation vs. AV Amplitude of Peaking (<50 MHz) Conditions
(Unless otherwise noted, AV = +3;
VS =
5 V; RF = 400
; RLOAD = 100
)
Units
Test Temp Level
AD9617JN/JR AD9617AQ/SQ* Min Typ Max Min Typ Max
AD9617BQ/TQ* Min Typ Max
VOUT 2 V p-p VOUT = 4 V p-p AV = -1 to 15 T = TMIN to +25C T = TMAX Amplitude of Peaking (>50 MHz) T = TMIN to +25C T = TMAX Amplitude of Roll-Off (<60 MHz) Phase Nonlinearity DC to 75 MHz 2nd Harmonic Distortion 2 V p-p; 4.3 MHz 2 V p-p; 20 MHz 2 V p-p; 60 MHz 3rd Harmonic Distortion 2 V p-p; 4.3 MHz 2 V p-p; 20 MHz 2 V p-p; 60 MHz Input Noise Voltage 10 MHz Inverting Input Noise Current 10 MHz Average Equivalent Integrated Input Noise Voltage 0.1 MHz to 200 MHz TIME DOMAIN Slew Rate Rise/Fall Time VOUT = 2 V Step VOUT = 4 V Step VOUT = 4 V Step Overshoot Settling Time To 0.1% To 0.02% To 0.1% To 0.02% 2x Overdrive Recovery to 2 mV of Final Value Propagation Delay Differential Gain1 Differential Phase1 VOUT = 4 V Step
Full Full +25C Full +25C Full Full Full Full Full Full +25C +25C
II IV V II II II II II V IV IV II IV IV II V V
135
190 150 40 0 0 0 0 0.1 0.5 -86 -67 -51 -83 -69 -54 1.2 29 55 1400 2.0 2.4 2.4 3 10 14 11 16 50 2 <0. 01 0.01
145 115
-78 -59 -43 -75 -61 -46
190 150 40 0 0 0 0 0.1 0.5 -86 -67 -51 -83 -69 -54 1.2 29 55
145 115 0.3 0.6 0.8 1.0 0.6 -78 -59 -43 -75 -61 -46
190 150 40 0 0 0 0 0.1 0.5 -86 -67 -51 -83 -69 -54 1.2 29 55
0.3 0.6 0.8 1.0 0.6 -78 -59 -43 -75 -61 -46
MHz MHz MHz dB dB dB dB dB Degree dBc dBc dBc dBc dBc dBc nV/Hz pA/Hz V, rms V/s
+25C V Full Full Full Full Full Full Full +25C +25C Full Full IV IV IV IV IV IV IV IV IV V V V V
1100 1400 2.0 2.4 2.4 3 10 14 11 16 50 2 <0. 01 0.01 2.5 3.3 3.5 14 15 23 16 24
1100
1400 2.0 2.4 2.4 3 10 14 11 16 50 2 <0 .01 0.01 2.5 3.3 3.5 14 15 23 16 24
T = +25C to TMAX T = TMIN VOUT = 2 V Step VOUT = 2 V Step VOUT = 2 V Step VOUT = 4 V Step VOUT = 4 V Step VIN = 1.7 V Step
ns ns ns % ns ns ns ns ns ns % Degree
POWER SUPPLY REQUIREMENTS Quiescent Current +IS -IS
NOTES *Pending obsoletion: last-time buy October 25, 1999. 1 Frequency = 4.3 MHz; R L = 150 ; AV = +3. Specifications subject to change without notice.
Full Full
II II
34 34
48 48
34 34
48 48
34 34
48 48
mA mA
REV. B
-3-
AD9617
EXPLANATION OF TEST LEVELS Test Level DIE CONNECTIONS
+VS
I - 100% production tested. II - 100% production tested at +25C and sample tested at specified temperatures. AC testing of J grade devices done on sample basis. III - Sample tested only. IV - Parameter is guaranteed by design and characterization testing. V - Parameter is a typical value only. VI - All devices are 100% production tested at +25C. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices.
+VS -INPUT TOP VIEW (Not to Scale) OUTPUT +INPUT
-VS DIE SIZE = 53 67
-VS 15 mils
ORDERING GUIDE
Model AD9617JN AD9617JR AD9617JR-REEL
Temperature Range 0C to +70C 0C to +70C 0C to +70C
Package Description Plastic DIP SOIC 13" Tape and Reel
Package Option N-8 SO-8 SO-8
-4-
REV. B
AD9617 Typical Performance Characteristics (A = +3;
V
3 2 1 0 AV = +5 AV = +1 180 135
VS =
5 V; RF = 400 V, unless otherwise noted)
10 15
PHASE - Degrees
90 45 0 -45 -90 -135 -180
20 25 30
MAGNITUDE - dB
-1 -2 -3 -4 -5 -6 -7 AV = +20 0 40 80 120 FREQUENCY - MHz 160
dB
35 40 45 50 55 PSRR CMRR
200
60 100
1k
10k 100k 1M FREQUENCY - Hz
10M
100M
Figure 1. Noninverting Frequency Response
Figure 4. CMRR and PSRR
3 2 1 AV = -1 MAGNITUDE - dB 0 -1 -2 -3 -4 -5 AV = -20 -6 -7 0 40 80 120 160 AV = -5
180 135
SETTLING PERCENTAGE - %
0.1 0.08 TEST CIRCUIT 100 6pF
PHASE - Degrees
90 45 0 -45 -90
0.06 0.04 0.02 0 -0.02 -0.04
-135 -180
VOUT = 4V STEP -0.06 -0.08
200
-0.1 0 8 16 TIME - s 24 32 40
FREQUENCY - MHz
Figure 2. Inverting Frequency Response
Figure 5. Settling Time
120 GAIN 105 90 75 PHASE 60 45 30 15 0 10k TEST CIRCUIT
0 30 60 90 120 150 180 210 240 100k 1M 10M FREQUENCY - Hz 100M 1G SETTLING PERCENTAGE - %
RELATIVE PHASE - Degrees
0.1 0.08 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 VOUT = 4V STEP -0.08 -0.1 0 2 4 TIME - s 6 8 10 TEST CIRCUIT 100 6pF
GAIN - dB
100
Figure 3. Open Loop Transimpedance Gain [T(s) Relative to 1 ]
Figure 6. Long Term Settling Time
REV. B
-5-
AD9617
40 VOUT = 2V p-p = 2ND HARMONIC = 3RD HARMONIC
50
50
50
INTERCEPT - +dBm
60
-dBc
40
TEST CIRCUIT
50
70 100 80 LOAD 500 LOAD
30
90
100 0 2 4 6 8 10 20 FREQUENCY - MHz 40 60 100
20 0 30 60 90 FREQUENCY - MHz 120 150
Figure 7. Harmonic Distortion
Figure 10. Intermodulation Distortion (IMD)
3 2 1 0
MAGNITUDE - dB
180 RL = 100 RL = 500 135
PHASE - Degrees
2.5 2.0 1.5 AV = +3
90 45 0 -45 -90 -135
ANALOG INPUT - Volts
1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 AV = -3 10ns/DIV TEST CIRCUIT 100 6pF
-1 -2 -3 -4 RL = 50 -5 -6 -7 0 40 80 120 FREQUENCY - MHz 160
-180
200
Figure 8. Frequency Response vs. RLOAD
Figure 11. Large Signal Pulse Response
115
7
AV = +3
100 pA/ Hz (INVERTING) 85
pA/ Hz
6
ANALOG INPUT - Volts
5
nV/ Hz
1.0 0.5 0 -0.5 -1.0 TEST CIRCUIT 100 6pF
70 nV/ Hz 55
4
3
40
2
AV = -3
25 100 1k 10k FREQUENCY - MHz 1 100k
10ns/DIV
Figure 9. Equivalent Input Noise
Figure 12. Small Signal Pulse Response
-6-
REV. B
AD9617
THEORY OF OPERATION
The AD9617 has been designed to combine the key attributes of traditional "low frequency" precision amplifiers with exceptional high frequency characteristics that are independent of closedloop gain. Previous "high frequency" closed-loop amplifiers have low open loop gain relative to precision amplifiers. This results in relatively poor dc nonlinearity and precision, as well as excessive high frequency distortion due to open loop gain roll-off. Operational amplifiers use two basic types of feedback correction, each with advantages and disadvantages. Voltage feedback topologies exhibit an essentially constant gain bandwidth product. This forces the closed-loop bandwidth to vary inversely with closed-loop gain. Moreover, this type design typically slew rate limits in a way that causes the large signal bandwidth to be much lower than its small signal characteristics. A newer approach is to use current feedback to realize better dynamic performance. This architecture provides two key attributes over voltage feedback configurations: (1) avoids slew rate limiting and therefore large signal bandwidth can approach small signal performance; and (2) low bandwidth variation versus gain settings, due to the inherently low open loop inverting input resistance (RS). The AD9617 uses a new current feedback topology that overcomes these limitations and combines the positive attributes of both current feedback and voltage feedback designs. These devices achieve excellent high frequency dynamics (slew, BW and distortion) along with excellent low frequency linearity and good dc precision.
DC GAIN CHARACTERISTICS
The major difference lies in the front end architecture. A voltage feedback amplifier has symmetrical high resistance (buffered) inputs. A current feedback amplifier has a high noninverting resistance (buffered) input and a low inverting (buffer output) input resistance. The feedback mechanics can be easily developed using current feedback and transresistance open loop gain T(s) to describe the I/O relationship. (See typical specification chart.) DC closed-loop gain for the AD9617 can be calculated using the following equations:
G=
G=
V O -RF / RI V I 1 + 1 / LG
V O 1 + RF / RI VN 1 + 1 / LG
inverting
(1)
noninverting
(2)
where
RS ( RF + RS RI ) 1 LG T ( s )( RS RI )
(3)
Because the noninverting input buffer is not ideal, input resistance RS (at dc) is gain dependent and is typically higher for noninverting operation than for inverting operation. RS will approach the same value ( 7 ) for both at input frequencies above 50 MHz. Below the open loop corner frequency, the noninverting RS can be approximated as:
RS ( noninverting ) 7 + T (s) T = 7+ O AO AO
(4)
dc
where: AO = Open Loop Voltage Gain
G x 600
A simplified equivalent schematic is shown below. When operating the device in the inverting mode, the input signal error current (IE) is amplified by the open loop transimpedance gain (TO). The output signal generated is equal to TO x IE. Negative feedback is applied through RF such that the device operates at a gain (G) equal to -RF/RI. Noninverting operation is similar, with the input signal applied to the high impedance buffer (noninverting) input. As before, an output (buffer) error current (IE) is generated at the low impedance inverting input. The signal generated at the output is fed back to the inverting input such that the external gain is (l + RF/ RI). The feedback mechanics are identical to the voltage feedback topology when exact equations are used.
Inverting RS below the open loop corner frequency can be approximated as:
RS ( inverting ) 7 + T (s ) T = 7+ O AO AO
(5)
dc
where: AO = 40,000. The AD9617 approaches this condition. With TO = 1 x 106 , RL = 500 and RS = 25 (dc), a gain error no greater than 0.05% typically results for G = -1 and 0.15% for G = -40. Moreover, the architecture linearizes the open loop gain over its operating voltage range and temperature resulting in 16 bits of linearity.
RL = 100
+
VN LS TO RS RI VI CI IE VO CC ERROR RELATIVE TO FS 0.0002%/DIVISION 0%
-
RF -2 -1 0 VOUT - Volts 1 2
Figure 13. Equivalent Circuit
Figure 14. DC Nonlinearity vs. VOUT
REV. B
-7-
AD9617
AC GAIN CHARACTERISTICS
Closed-loop bandwidth at high frequencies is determined primarily by the roll-off of T(s). But circuit layout is critical to minimize external parasitics which can degrade performance by causing premature peaking and/or reduced bandwidth. The inverting and noninverting dynamic characteristics are similar. When driving the noninverting input, the inverting input capacitance (CI ) will cause the noninverting closed-loop bandwidth to be higher than the inverting bandwidth for gains less than two (2). In the remaining cases, inverting and noninverting responses are nearly identical. For best overall dynamic performance, the value of the feedback resistor (RF) should be 400 ohms. Although bandwidth reduces as closed-loop gain increases, the change is relatively small due to low equivalent series input impedance, ZS. (See typical performance charts.) The simplified equations governing the device's dynamic performance are shown below. Closed-Loop Gain vs. Frequency: (noninverting operation)
1+ s RF RI RS RI
specified BW, the following equations can be used to approximate RF and RI for any gain from l to 15. RF = 424 8 G (+ for inverting and - for noninverting)
RI RI 424 - 8 G G -1 424 + 8 G G -1
(8)
(noninverting) (inverting)
(9) (10)
G = Closed Loop Gain.
Bandwidth Reduction
The closed loop bandwidth can be reduced by increasing RF. Equations 6 and 7 can be used to determine the closed loop bandwidth for any value RF. Do not connect a feedback capacitor across RF, as this will degrade dynamic performance and possibly induce oscillation.
DC Precision and Noise
VO VI
1 +
+1
Output offset voltage results from both input bias currents and input offset voltage. These input errors are multiplied by the noise gain term (1 + RF/RI) and algebraically summed at the output as shown below. (6)
R R V O = V IO x 1 + F IBn x RN x 1 + F IBi x RF RI RI
(11)
where:
= RF x CC = 0.9 ns (RF = 400 ) (7)
V O Slew Rate x e -/ RF KCC RF KCC
S where: K = 1 + R I
R
Increasing Bandwidth at Low Gains
Since the inputs are asymmetrical, IBi and IBn do not correlate. Canceling their output effects by making RN = RF RI will not reduce output offset errors, as it would for voltage feedback amplifiers. Typically, IBn is 5 A and VIO is +0.5 mV (I sigma = 0.3 mV), which means that the dc output error can be reduced by making RN 100 . Note that the offset drift will not change significantly because the IBn TC is relatively small. (See specification table.)
RF RI RN IBi IBn VOUT
By reducing RF, wider bandwidth and faster pulse response can be attained beyond the specified values, although increased overshoot, settling time and possible ac peaking may result. As a rule of thumb, overshoot and bandwidth will increase by 1% and 8%, respectively, for a 5% reduction in RF at gains of 10. Lower gains will increase these sensitivities. Equations 6 and 7 are simplified and do not accurately model the second order (open loop) frequency response term which is the primary contributor to overshoot, peaking and nonlinear bandwidth expansion. (See Open Loop Bode Plots.) The user should exercise caution when selecting RF values much lower than 400 . Note that a feedback resistor must be used in all situations, including those in which the amplifier is used in a noninverting unity gain configuration.
Increasing Bandwidth at High Gains
Figure 15. Output Offset Voltage
10 1.0
IBn 5 A 0.5
IBi/IBn -
VIO 0 0
Closed loop bandwidth can be extended at high closed loop gain by reducing RF. Bandwidth reduction is a result of the feedback current being split between RS and RI. As the gain increases (for a given RF), more feedback current is shunted through RI, which reduces closed loop bandwidth (see Equation 6). To maintain
IBi -5 -0.5
-10 -55 C
25 C
-1.0 125 C
Figure 16. DC Accuracy
-8-
REV. B
VIO - mA
AD9617
The effective noise at the output of the amplifier can be determined by taking the root sum of the squares of Equation 11 and applying the spectral noise values found in the typical graph section. This applies to noise from the op amp only. Note that both the noise figure and equivalent input offset voltages improve as the closed loop gain is increased (by keeping RF fixed and reducing RI with RN = 0 ).
400 RSERIES In CLI RL 500 CL
APPLYING THE AD9617
The superior frequency and time domain specifications of the AD9617 make it an obvious choice for driving flash converters and buffering the outputs of high speed DACs. Its outstanding distortion and noise performance make it well suited as a driver for analog to digital converters (ADCs) with resolutions as high as 16 bits. Typical circuits for inverting and noninverting applications are shown in Figures 20 and 21. Closed-loop gain for noninverting configurations is determined by the value of RI according to the equation:
G =1+ RF RI
+VS 3.3 F 0.1 F 0.1 F
(12)
Figure 17. Capacitive Load Figure
Capacitive Load Considerations
Due to the low inverting input resistance (RS) and output buffer design, the AD9617 can directly handle input and/or output load capacitances of up to 20 pF. See the chart below. A small series resistor can be used at the output of the amplifier and outside of the feedback loop to facilitate driving larger capacitive loads or for obtaining faster settling time. For capacitive loads above 20 pF, RSERIES should be considered.
SETTLING TIME TO 0.02% - ns
35 30 25 20 15 10 5pF VOUT = 4V STEP CL = 0pF VOUT = 4V STEP CLI = 0pF
VIN RIN
AD9617
VOUT
400 RI 0.1 F 0.1 F 3.3 F -VS
4pF/DIV 25pF 10pF 4pF/DIV 30pF INPUT CAPACITANCE - CLI INPUT CAPACITANCE - CL RSERIES = 0
Figure 20. Noninverting Operation
+VS 3.3 F 0.1 F 0.1 F
Figure 18. Input/Output Capacitance Comparisons
25
20
AD9617
15
VOUT
RSERIES -
VIN 10
RI RTERM
400
0.1 F 5 0.1 F 3.3 F 0 -VS 0 20 40 CL - pF 60 80 100
Figure 21. Inverting Operation
Figure 19. Recommended RSERIES vs. CL
REV. B
-9-
AD9617
LAYOUT CONSIDERATIONS
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Small Outline Package (SO-8)
0.198 (5.00) 0.188 (4.74)
8 5 4
0.158 (4.00) 0.150 (3.80) PIN 1
1
0.244 (6.200) 0.228 (5.80)
0.050 (1.27) BSC 0.010 (0.25) 0.004 (0.10) SEATING PLANE 0.069 (1.75) 0.053 (1.35) 0.018 (0.46) 0.014 (0.36)
0.205 (5.20) 0.181 (4.60)
8 0.015 (0.38) 0 0.007 (0.18)
0.045 (1.15) 0.020 (0.50)
Plastic DIP (N-8)
0.430 (10.92) 0.348 (8.84)
8 5
0.280 (7.11) 0.240 (6.10)
1 4
PIN 1 0.100 (2.54) BSC 0.210 (5.33) MAX 0.200 (5.05) 0.125 (3.18) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN
0.325 (8.25) 0.300 (7.62)
0.022 (0.558) 0.070 (1.77) SEATING 0.014 (0.356) 0.045 (1.15) PLANE
0 -15
0.015 (0.381) 0.008 (0.204)
-10-
REV. B
PRINTED IN U.S.A.
C1353b-0-9/99
As with all high performance amplifiers, printed circuit layout is critical in obtaining optimum results with the AD9617. The ground plane in the area of the amplifier should cover as much of the component side of the board as possible. Each power supply trace should be decoupled close to the package with at least a 3.3 F tantalum and a low inductance, 0.1 F ceramic capacitor.
All lead lengths for input, output and the feedback resistor should be kept as short as possible. All gain setting resistors should be chosen for low values of parasitic capacitance and inductance, i.e., microwave resistors and/or carbon resistors. Stripline techniques should be used for lead lengths in excess of one inch. Sockets should be avoided if possible because of their stray inductance and capacitance.

▲Up To Search▲

Price & Availability of AD9617

	To Download AD9617 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .