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INTEGRATED CIRCUITS
SA900 I/Q transmit modulator
Preliminary specification IC17 Data Handbook 1997 Sept 16
Philips Semiconductors
Philips Semiconductors
Preliminary specification
I/Q transmit modulator
DO NOT DISTRIBUTE WITHOUT ECN DATED AFTER Sept 16, 1997
DESCRIPTION
The SA900 is a monolithic high performance, multi-function transmit modulator for use in cellular radio applications, fabricated in QUBiC BiCMOS technology. The SA900 features both analog (AMPS) mode and complex, I/Q digital (NADC IS-136) mode quadrature modulation functions, a PLL synthesizer with VCO, crystal oscillator, programmable prescalers and Gilbert cell multiplier phase detector with programmable charge pump output. The DUALTX output can be used in DUAL mode cellular phone applications with the AMPS and NADC modulation being applied to the I/Q baseband inputs. The DUALTX output also provides 6-bit power control with 40dB of gain control in 0.63dB steps. In addition, buffered crystal oscillator programmable prescaler outputs are provided to support system clock reference needs. Programming of the SA900 functions are realized by a high speed 3-wire serial interface. The SA900 can be programmed into a sleep mode (low current mode providing crystal oscillator and Master Clock functions), a standby mode (providing crystal oscillator, Master Clock, System Clock 1 and Transmit LO buffer functions), and the AMPS mode and the DUAL mode configurations.
SA900
PIN CONFIGURATION
BE Package
LO_2 LO_1 GND GND GND 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 XTAL_2 MCLK DATA Vcc GND CLK1 CLK2 GND CLOCK STROBE CLKSET TXEN Vcc Vcc Vcc Q Q I I
48 47 46 45 44 43 42 1 2 3 4 5 6 7 8 9
41 40 39 38 37 Vcc GND DUALTX GND Vcc AMPSTX GND Vcc GND Vcc Vcc GND
GND TXLO_2 TXLO_1 GND Vcc TANK_1 TANK_2 Vcc PHSOUT
IPEAK 10 GND 11 XTAL_1 12
FEATURES
* VCC = 4.0V * Tx output frequency = 900MHz * Direct modulation of RF * DUAL mode, on-chip PA control * I/Q modulator * Single sideband quadrature LO generation with no external * On-chip crystal oscillator with 3 buffered outputs * AMPS/TACS compatible * On-chip VCO
ORDERING INFORMATION
DESCRIPTION 48-Pin Plastic Low Profile Quad Flat Package (LQFP) adjustments required
SR00636
Figure 1. Pin Configuration
* Selective power-down
- Low power AMPS/TACS mode - Low power dual mode NADC
* 48-Pin TQFP package
APPLICATIONS
* North American Digital Cellular (TDMA IS-136)
TEMPERATURE RANGE -40 to +85C ORDER CODE SA900BE DWG # SOT313-2
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Philips Semiconductors
Preliminary specification
I/Q transmit modulator
SA900
BLOCK DIAGRAM
LO_2 LO_1 I I QQ
TXLO_2 TXLO_1 LPF
TXLO PHASE SHIFT IMAGE REJECT MIXER NETWORK
LPF
VGA
PA
DUALTX
TANK_1 TANK_2 VCO /N 2
VCO
LPF
PA VGA CONTROL BG SE N<0:1> AD SM1 SM2 Y X
AMPSTX
/A8/1 PHS DET
AD BIAS
PHSOUT
AD
IPEAK
/B8/1
AD
6
XTAL_1 XTAL_2 XTAL OSC
/ 3/1
X SM1
/ 2/1
Y SM2
/4/5/1
CONV2
CONTROL LOGIC
SM1
SM2
CLK1
CLK2
MCLK
CLKSET
DATA
CLOCK STROBE TXEN
SR00637
Figure 2. Block Diagram
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Philips Semiconductors
Preliminary specification
I/Q transmit modulator
SA900
PIN DESCRIPTIONS
Pin I I TXLO_1/2 DUALTX Q Q CLK1 MCLK CLK2 AMPSTX VCC GND Data Clock Strobe TXEN CLKSET XTAL1 XTAL2 PHSOUT TANK_1 TANK_2 LO_1/2 IPEAK Non-inverting I Mod Signal Inverting I Mod Signal Second LO Input (differential/single-ended input) RF output (850MHz) digital (DUAL) mode, complex modulated output Non-inverting Q Mod Signal Inverting Q Mod Signal Buffered oscillator output (XO /3//1) Buffered oscillator output (XO /4//5//1) Buffered oscillator output (XO /2//1) RF output (850MHz) AMPS mode +5VDC power supply Ground Serial data input Serial clock input Data strobe input AMPS and Dual Mode transmit enable Program control pin for MCLK prescaler Crystal oscillator base input Crystal oscillator emitter output Phase comparator charge pump output VCO differential tank VCO differential tank Buffered differential TXLO output Phase comparator current programming Description
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Philips Semiconductors
Preliminary specification
I/Q transmit modulator
SA900
GND_LO 1
GND 4
GND 11
GND 16
GND 18
GND_CTRL 25
GND 28
GND 30
GND 33
GND 35
GND 37
GND 39
GND 45
GND
VCC_LO 48
VCC 5
VCC 8
VCC 14
VCC 27
VCC 29
VCC 32
VCC 36
VCC 38
VCC 44
VCC_CTRL 26
VCC
2 50 VCC 50 3
VCC
6
VCC
7
VCC
VCC
0.1/6.4 mA
12
9
VCC 0.1/6.4 mA 13
SR00638
Figure 3. Pin Diagrams
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Philips Semiconductors
Preliminary specification
I/Q transmit modulator
SA900
VCC
VCC 500
15
17
19
20
VCC 500 21 22 23 24
VCC 30 31 34
VCC 600
VCC
40
42 680 680
VCC
41
43
VCC 20 46 47
SR00639
Figure 4. Pin Diagrams (cont.)
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Philips Semiconductors
Preliminary specification
I/Q transmit modulator
SA900
ABSOLUTE MAXIMUM RATINGS
SYMBOL VCC VIN PD TJMAX PMAX TSTG Supply voltage Voltage applied to any other pin Power dissipation, TA = 25C (still air) Maximum operating junction temperature Maximum power input/output Storage temperature range PARAMETER RATING -0.3 to +6 -0.3 to (VCC + 0.3) 600 150 +10 -65 to +150 UNITS V V mW C dBm C
NOTE: 1. Maximum dissipation is determined by the operating ambient temperature and the thermal resistance, JA. 48-pin LQFP: JA = 67C/W
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC TA TJ Supply voltage Operating ambient temperature range Operating junction temperature PARAMETER RATING 3.9 to 5.1 -40 to +85 -40 to +105 UNITS V C C
DC ELECTRICAL CHARACTERISTICS
VCC = +4.0V, TA = 25C; unless otherwise stated. SYMBOL VCC PARAMETER Power supply range Sleep mode ICC Supply current Standby mode AMPS mode DUAL mode I/I Q/Q In-phase differential baseband input Quadraphase differential baseband input DC DC TEST CONDITIONS LIMITS MIN 3.9 3.1 8.2 27.5 64 0.5VCC 0.5VCC VCC 0.5VCC 0 -0.3 0.7VCC 0.3VCC VCC+0.3 V V V V V mA TYP MAX 5.1 UNITS V
CLKSET
Divide by 4/5/1
/4 /5 /1
Input low Input high
VIL VIH
Clock, data, strobe, TXEN Clock, data, strobe, TXEN
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Philips Semiconductors
Preliminary specification
I/Q transmit modulator
SA900
AC ELECTRICAL CHARACTERISTICS
VCC = +4.0V, TA = 25C; TANK_1 = 120MHz @ 0 dBm; XO_REF = 30MHz @ -5 dBm; TxLO2 = -13 dBm, unless otherwise stated. SYMBOL PARAMETER TEST CONDITIONS Input power TXLO_1/2 Transmit LO input (AC couple) (50) TANK_1/2 VCO tank differential inputs PHSOUT IPEAK XTAL 1 XTAL_1 Phase detector charge pump output PHSOUT programming XO transistor base XO divide 3/1, power down SM1=0, 50% duty cycle /3, X=1, /1, X=0 CLK2 XO divide 2/1, power down SM2=0 /2, Y=1, /1, Y=0 XO divide 4/5/1, 50% duty cycle MCLK /4, CLKSET = VCC, /5, CLKSET = 0.5VCC, /1, CLKSET = 0V Serial data clock input, 33% duty cycle CLOCK Serial interface (CMOS levels) DATA, CLOCK, STROBE, TXEN AMPS output, SE=1, AD=0, TXEN=1 (AC couple) VSWR (50) Frequency range Frequency range Output level RSET = 24k, AD=0 RSET = 24k, AD=1 XO frequency External drive Frequency range Output level, 5k || 7pF Frequency range Output level, 5k || 7pF Frequency range Output level, 5k || 7pF Max clock rate Logic LOW Logic HIGH Frequency range VSWR Output level 869 to 894MHz 824 to 849MHz AMPSTX Spurious output 2 to 824MHz 849 to 869MHz 894MHz to 8.49GHz TXLO and harmonics Adjacent channel noise power Alternate channel noise power Broadband noise power DUAL output, SE=1, AD=1, TXEN=1 (with external matching Figure 9) DUALTX @30kHz @60kHz 869 to 894MHz Frequency range VSWR Output level (avg) (I and Q quad, 0dB VGA) Gain flatness 0 820 2:1 +2 1 dBm dB -1.5 0.7VCC 820 2:1 +2 -104 -47 -41 -41 -41 -21 -95 -101 -136 9202 dBm dBm dBc dBc dBc dBc dBc dBc/Hz dBc/Hz dBm/Hz MHz 860 900 901 0.5 200 0.9 101 1501 3.331 0.7 51 0.7 21 0.7 1 300 1.2 30 350 30 1 30 1 120 LIMITS MIN -13 2:1 1040 1401 VCC-0.5 400 1.5 451 5001 451 1.4 451 1.4 451 1.4 101 0.3VCC
1
TYP
MAX -101
UNITS dBm MHz MHz V A mA MHz mVP-P MHz VP-P MHz VP-P MHz VP-P MHz V V MHz
CLK1
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Philips Semiconductors
Preliminary specification
I/Q transmit modulator
SA900
AC ELECTRICAL CHARACTERISTICS (continued)
SYMBOL DUALTX (cont.) Linearity (0dB VGA, I and Q inphase) Carrier suppression (I and Q quadrature) Carrier suppression (I and Q quadrature) Sideband suppression PARAMETER TEST CONDITIONS 3rd order 5th order 7th order VGA = 0dB VGA = -40dB I and Q quadrature 869 to 894MHz 824 to 849MHz Spurious output 2 to 824MHz 849 to 869MHz 894MHz to 8.49GHz TXLO and harmonics Broadband noise (0dB VGA) Adjacent channel noise power Alternate channel noise power Q/Q Baseband quadrature differential input 869 to 894MHz 935 to 960MHz @30kHz @60kHz Max frequency Differential modulation level Differential input impedance Max frequency I/I Baseband inphase differential input Buffered TXLO differential outputs (AC coupled) LO_1/2 _ Differential modulation level Differential input impedance Frequency range VSWR (single-ended) Output impedance Output level Out ut single-ended differential single-ended, 50 differential, 100 50 100 0.61 10 900 2:1 50 100 90 180 mVP-P mVP-P 1040 0.61 101 0.8 0.8 21 1.01 -35 -28 -35 LIMITS MIN -35 TYP -42 -55 -65 -45 -33 -45 -104 -47 -41 -41 -41 -21 -136 -136 -95 -101 0.8 0.8 21 1.01 MAX UNITS dBc dBc dBc dBc dBc dBc dBm dBc dBc dBc dBc dBc dBm/Hz dBm/Hz dBc/Hz dBc/Hz MHz VP-P k MHz VP-P k MHz
NOTES: 1. Guaranteed by design. 2. Needs a different matching component. Max test frequency is 850MHz with test circuit shown in Figure 11.
FUNCTIONAL DESCRIPTION Dual Mode Operation
The SA900 transmit modulator provides direct single sideband quadrature modulation of the difference of the TXLO and VCO frequencies, while providing quadrature LO signals for the I/Q modulator. The quadrature LO signals are modulated with high linearity by the baseband inphase (I) and quadrature (Q) signals. The summed modulator output produces the lower sideband, while rejecting the upper sideband. The I and Q inputs also provide DC biasing for the modulator inputs. The summed output of the modulator goes to a variable gain amplifier (VGA) to control the output level, it has 40.0dB of attenuation control range, with 0.63dB steps. The power control function is programmed by means of a 6-bit word (see Table 3). The VGA output drives the power amp output stage to provide +2dBm average minimum power level (at 0dB power control) into 50, in conjunction with external matching components on DUALTX. The AD (AMPS/DUAL) and the SE (synthesizer enable) bit control the power up/down of the DUAL
mode function. The transition of the TXEN, from low to high turns on the modulator. The falling edge of the TXEN signal disables the synthesizer and modulator. The TXLO is a system supplied LO signal. The SA900 buffers the TXLO signal (LO_1/2) for use with the system synthesizer (such as the SA7025) to form the system LO synthesizer loop. The DUAL mode can also be used for AMPS operation. The AMPS and DUAL mode modulation is generated by the system DSP IC to provide the required I/Q baseband modulation for the SA900. The DUAL output provides low broadband noise output power (so that the receiver sensitivity is not degraded) and high linearity to meet cellular phone system needs. Table 1 provides the VGA power control limits. The SA900 DUALTX output is externally matched with either a shunt inductor to VCC and a series capacitor or a shunt inductor to VCC and a series inductor. This matches the DUALTX output to 50. Values of the matching components are dependent on PCB layout, typical values are shown in Figure 9.
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Philips Semiconductors
Preliminary specification
I/Q transmit modulator
SA900
Table 1. VGA Power Control Limits
VGA 0 1 2 3 4 5 6 7 15 23 31 39 47 55 63 63 Min. 0 -1 -1 -1 -1 -1 -1 -1 -6.6 -6.6 -6.6 -6.6 -6.6 -6.6 -6.6 -43.2 Typ. 0 -.63 -.63 -.63 -.63 -.63 -.63 -.63 -5 -5 -5 -5 -5 -5 -5 -40.4 Max. 0 -.2 -.2 -.2 -.2 -.2 -.2 -.2 -3 -3 -3 -3 -3 -3 -3 -37.2 Relative VGA 0 0 1 2 3 4 5 6 7 15 23 31 39 47 55 0
the AMPS mode (AD=0) to a maximum of 6.4mA for the DUAL mode (AD=1) by way of an external current setting resistor placed from IPEAK to circuit ground. The typical loop filter network is shown in Figure 5. The charge pump current output is programmed by AD + 0 I OUT + 6 @ 1.25V R SET 1.25V R SET
AD + 1
I OUT + 24 @
where RSET is placed between IPEAK and GROUND. The PLL frequency is determined by ( A8 ) 1 B8 () 1
VCO + XO @ N @
where N=6, 7, 8, 9 and A8/1 and B8/1 are controlled by the AD bit (AD=1 A8/1 and B8/1 are divide by 1, AD=0 A8/1 and B8/1 are divide 8).
1. Guaranteed to be monotonic.
Table 2. Data Word Format
Mnemonics A0 A1 A2 A3 PC0 PC1 PC2 PC3 PC4 PC5 N0 N1 AD SE NA SM1 SM2 X Y NA NA NA NA NA Bits 1 (MSB) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (LSB) Function Address bit 0 (1) Address bit 1 (0) Address bit 2 (1) Address bit 4 (1) Power control bit 0 Power control bit 1 Power control bit 2 Power control bit 3 Power control bit 4 Power control bit 5 Divide N bit 0 Divide N bit 1 AMPS/DUAL mode select bit Synthesizer enable bit NA Sleep mode 1 control bit Sleep mode 2 control bit Divide 3/1 control bit Divide 2/1 control bit NA NA NA NA NA
AMPS Mode Operation
The SA900 can be configured to operate in the AMPS mode, where FM modulation is applied to the SA900's VCO. For the AMPS mode, the VCO is configured with the proper synthesizer bandwidth to allow the application of the AMPS modulation to the VCO varactor tuned tank circuit. The modulated VCO signal is input into an image reject mixer along with the TXLO signal, where the upper sideband is rejected. This single sideband modulated signal then drives the AMPS output power amplifier. The PA provides +2dBm power level into 50, with no external matching components required. The AD (AMPS/DUAL) and the SE (synthesizer enable) bit control the power up/down of the AMPS mode function. The transition of the TXEN signal from low to high turns on the modulator. The falling edge of TXEN signal disables the synthesizer and the modulator.
Synthesizer Operation
The SA900 synthesizer is comprised of the differential VCO circuit, with external tank components, the Gilbert cell multiplier phase detector with programmable charge pump current, crystal oscillator and programmable prescalers. The charge pump output drives an external second order loop filter. The output of the loop filter is used to provide the control voltage to the VCO tuning varactor to complete the PLL synthesizer. The synthesized VCO output frequency is mixed with the TXLO signal to generate the transmit LO from the lower sideband (the difference of the VCO and TXLO frequencies). The output of VCO is fed to a programmable /N prescaler with user selectable divides of 6, 7, 8 and 9 (all divides configured to provide 50% duty cycle). The output of the /N divider drives the A8/1 prescaler. The A8/1 divide is selected by the AD control bit (AD=1 for /1, and AD=0 for /8). The output of the divide A8/1 is fed into one input of the phase detector. The reference input for the phase comparator is generated from the crystal oscillator (XO) output from the B8/1 prescaler. The B8/1 divide is selected by the AD control bit (AD=0 for /8, and AD=1 for /1). The phase detector compares the prescaled XO reference phase to the VCO prescaled phase, to generate a charge pump output current proportional to the phase error. The phase detector, a Gilbert cell multiplier type, having a linear output from 0 to (/2 /2). The charge pump peak output current is programmable from 100A for
VCO Operation
The VCO is designed to operate from 90MHz to 140MHz. The VCO tank is configured using a parallel inductor and a dual common cathode tuning varactor diodes. DC blocking capacitors are used to isolate the varactor
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Philips Semiconductors
Preliminary specification
I/Q transmit modulator
SA900
control voltage from the VCO tank DC bias voltages. The VCO tuning voltage is generated from the output of the PLL loop filter. The VCO tank configuration is shown in Figure 6.
AMPS/DUAL Mode
The A/D mode select enables or disables that portion of the circuitry used for either the AMPS or DUAL mode of operation. AD 0 1 Mode AMPS DUAL
Crystal Oscillator (XO) Operation
For cellular radio applications, the SA900 will most likely utilize an external reference TCXO in order to provide the frequency stability necessary to operate to system requirements. The output of the system TCXO can be AC coupled to the XTAL_1 input. However, for applications that do not require such accuracy the XO circuit can be configured as a Colpitts type oscillator with the addition of two external capacitors along with the reference crystal and a trim capacitor as shown in Figure 7.
Synthesizer Enable
The SE bit turns on and off the synthesizer circuitry. SE 0 1 Operation Disabled Enabled
Programmable Clock Outputs
The SA900 generates three buffered XO outputs used for external reference signals. The XO feeds three sets of programmable prescalers, the prescaler outputs are buffered to provide the CLK1, CLK2 and MCLK signals. The CLK1 signal is a selectable divide 3/1 (X=1 divide 3, X=0 divide 1), 50% duty cycle, of the XO reference signal. The CLK2 signal is a selectable divide 2/1 (Y=1 divide 2, Y=0 divide 1), 50% duty cycle, of the XO reference signal. The MCLK signal is a selectable divide 4/5/1 (CLKSET = VCC divide 4, CLKSET = VCC/2 divide 5, and CLKSET = 0V divide 1), 50% duty cycle, of the XO reference signal. MCLK is externally set by means of the tri-level CLKSET input to provide a default master system clock prior to programming the SA900.
Sleep Mode 1
The SM1 bit is used to power down the TXLO buffer, the divide 3/1 prescaler and the CLK1 output buffer. SM1 0 1 Operation Power down Power up (STANDBY)
Sleep Mode 2
The SM2 bit is used to power down the divide 2/1 prescaler and the CLK2. SM2 0 1 Operation Power down Power up (with SM1=1 normal operation)
Programming Operation
The SA900 is configured by means of a 3-wire input (CLOCK, STROBE, DATA) to program the AMPS and DUAL modes, in addition there are two power saving modes of operation, SLEEP and STANDBY. The control logic section of the SA900 is designed using low power CMOS logic. During SLEEP mode only the circuitry required to provide a master clock (MCLK) to the digital portion of the system is enabled. During the STANDBY mode of operation MCLK, CLK1 and the TXLO and buffered LO outputs are powered on, which may be the case when the system is in the receive only mode. In the AMPS or DUAL operational modes all functions of the SA900 are powered on to support receive, transmit and system clock functions. The programming of the SA900 is identical to the programming format of the SA7025 low-voltage 1GHz fractional-N synthesizer, that can be used in conjunction with the SA900 to provide the cellular radio channel selection. The programming data is structured as a 24 bit long serial data word; the word includes 4 address bits (dedicated 1 0 1 1) for chip select. Data bits are shifted in on the leading edge of the clock, with the least significant bit (LSB) first and the most significant bit (MSB) last. Table 2 shows data word format, the 15th and last 5 bits are not used. Figure 8 shows the chip timing diagram.
Divide 3
X 0 1 Operation Divide 1 Divide 3
Divide 2
Y 0 1 Operation Divide 1 Divide 2
Address
A0 1 A1 0 A2 1 A3 1
Divide By N
N0 0 1 0 1 N1 0 0 1 1 Divide 6 7 8 9
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Philips Semiconductors
Preliminary specification
I/Q transmit modulator
SA900
Table 3. Power Control
Attenuation (dB) 0 0.6 1.3 1.9 2.5 3.2 3.8 4.4 5.0 5.7 6.3 * * * 23.3 * * * 39.7 1 1 1 1 1 1 1 0 1 0 0 1 PC0 (0.6dB) 0 1 0 1 0 1 0 1 0 1 0 PC1 (1.3dB) 0 0 1 1 0 0 1 1 0 0 1 PC2 (2.5dB) 0 0 0 0 1 1 1 1 0 0 0 PC3 (5.0dB) 0 0 0 0 0 0 0 0 1 1 1 PC4 (10.0dB) 0 0 0 0 0 0 0 0 0 0 0 PC5 (20.0dB) 0 0 0 0 0 0 0 0 0 0 0
Component Designator R1 R2 C1 C2 C3 RSET
Value DUAL Mode 560 1k 2.2nF No Load 33pF 15k Typical Filter Network
R2
AMPS Mode 560 5.6k 2.7F .27F 6.8nF 75k
PHSOUT R1 C1 C2 C3
VCTRL
SR00640
Figure 5. PLL Loop Filter
(AMPS MODULATION) C1 TANK_1 f VCO [ 120MHz 1 2p L1C C + C3 ) C2 TANK_2 1 1 1 ) ) C2 CVRI C1 *1 C1 = C2 = 33pF C3 = 12pF L1 = 82nH VR1 TOKO KV1470
L1
C3
VCC
+ VR1 VCTRL
SR00641
Figure 6. VCO Tank Configuration
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Philips Semiconductors
Preliminary specification
I/Q transmit modulator
SA900
XTAL_1 C1 XO XTAL_2 C2 CVAR
SR00642
Figure 7. Crystal Oscillator Configuration
TXEN
TRANSMIT ENABLED
DATA
LSB
MSB
CLOCK T1 STROBE T2 T3 T4
SYN_EN 1 1 T1 + T2 + T3 + , T4 + 3CLOCK 3CLOCK
SYNTHESIZER ENABLED
SR00643
Figure 8. Chip Timing Diagram
VCC 100pF L1 L2 34 SA900 TYPICAL VALUES L1 = 39nH L2 = 22nH 50 1000pF OR SA900 1nF
VCC 100pF L3 C1 34 1nF
TYPICAL VALUES L3 = 12nH C1 = 1.5pF
50
SR00644
Figure 9. DUALTX Output Matching
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1997 Sept 16
1 ZO=50 ZO=50 W2 + C246 4.7uF J3 Q2 J4 Q1 2 J5 I2 C314 100pF J6 I1 2 1 Vcc W1 C313 100pF
J8 LO2PS1
Philips Semiconductors
J7 LO2PS2
P1-1,2,3 GND U1 SA900BE 444444444333 876543210987 C241 100PF C305 100pF L304 39nH C301 100pF V L L GV I I QQGV G c OON c 1 2 1 2 N c N c 2 1 Dc Dc D
P1-4,5,6,11,12,13 W3 1 ZO=50 C254 33pF L372 22nH C312 100pF W5 1 ZO=50 2 C249 100pF 2 C247 100pF
I/Q transmit modulator
J1 TXLO2
C306 .010uF
VCO-TUNE P1-15 JP4
1
W4 ZO=50
2
J9 DIGTXRF
R258 1k D1 KV1470 C253 C255 33pF 5.6pF R262 15k R268 NL C267 220pF C243 100pF 111111122222 345678901234 L252 100nH
JMP PHS-OUT P1-14 JP5
J10 AMPSTXRF
JMP
R333 1k C S X L CT T C C MK D L R T A V L GL GC S A OOX L c KNK NL ET CBE 1 c 1 D2 DKT AKEN
1 2 3 4 5 6 7 8 9 10 11 12 GND TXLO2 TXLO1 GND Vcc TANK1 TANK2 Vcc PHS OUT IPEAK GND XTAL1 Vcc GND DUALTX GND Vcc AMPSTX GND Vcc GND Vcc Vcc GND C300 .010uF C242 100pF
36 35 34 33 32 31 30 29 28 27 26 25
R264 1k
Figure 10. SA900 Application Circuit
C370 100pF NL R352 100 C371 100pF C299 NL C288 .010uF L296 NL C295 NL C294 NL C287 .010uF P4 MCLK R293 NL C292 NL L290 NL P3 CLK1 C282 NL C289 NL P2 CLK1 R297 NL P1-7 DATA P1-8 CLOCK P1-9 STROBE R279 R274 0 C283 NL L280 NL C263 .01uF C281 .010uF R260 51 R284 NL
14
C269 33pF
R266 560
C245 .010uF
C265 NL
J18 VCO-REF
JP1 JMP JP2 JMP JP3 JMP
R349 100k
T1-1 KK81
R350 100k
J2 XO-REF
NOTE: VCO-REF circuit is optional L372 is C307 on the PCB C246 combines C240 and C244 on the PCB
P1-10 TXENABLE
SA900
Preliminary specification
SR00645
LO_1 2 ZO=50 1
1997 Sept 16
C315 270pF LO_2 2 ZO=50 I1 I2 Q1 + C246 1000pF 444444444333 876543210987 C241 100PF C305 100pF L304 39nH C301 100pF V L L GV I I QQGV G c OON c 1 2 1 2 N c N c 2 1 Dc Dc D Q2 1 C314 270pF
Philips Semiconductors
Vcc
I/Q transmit modulator
GND
TXLO2 W3 ZO=50 C249 100pF 2
C247 270pF
C306 .010uF
1
1
ZO=50
2
DIGTXRF
TANK-1 C370 100pF SA900
L372 22nH
T1-1 KK81 C371 100pF
C312 100pF
AMPSTX 1 ZO=50 C300 .010uF 2
1 2 3 4 5 6 7 8 9 10 11 12 GND TXLO2 TXLO1 GND Vcc TANK1 TANK2 Vcc PHS OUT IPEAK GND XTAL1 Vcc GND DUALTX GND Vcc AMPSTX GND Vcc GND Vcc Vcc GND
36 35 34 33 32 31 30 29 28 27 26 25
Figure 11. SA900 Test Circuit
15
R300 1K C243 100pF R301 1K R262 24K S C X L CT T C C MKDL R T A V L G L G C SA OOX L c K N K N L ET CB E 1 c 1 D 2 D KTAKEN 111111122222 345678901234 CLOCK1 R303 4.7K R305 4.7K MCLK C263 .01uF C400 7pF C401 7pF R260 51 CLOCK2 R304 4.7K C402 7pF
PHASE OUT
C242 100pF
C245 .010uF
C280 1000pF
DATA CLKSET CLOCK STROBE TXENABLE
XO-REF
SA900
Preliminary specification
SR00646
Philips Semiconductors
Preliminary specification
I/Q transmit modulator
SA900
PERFORMANCE CHARACTERISTICS
-16.00 -16.50 POWER (dBm) -17.00 -17.50 -18.00 -18.50 -19.00 900 VCC = 3.9V VCC = 4.0V VCC = 4.5V POWER (dBm) 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 -0.50 970 FREQUENCY (MHz) 1040 -1.00 820 836 FREQUENCY (MHz) 860 T = +85C T = +27C T = -45C
LO Buffer vs. Frequency (27C, TXLO = -10dBm)
3.00 2.80 2.60 POWER (dBm) 2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 820 836 FREQUENCY (MHz) 860 POWER (dBm) 2.60 VCC = 3.9V VCC = 4.0V VCC = 4.5V 2.80
AMPTX vs. Frequency (VCC = 4.0V, TXLO = -10dBm)
VCC = 4.5V VCC = 3.9V VCC = 4.0V
2.40
2.20
AMPTX vs. Frequency (27C, TXLO = -10dBm)
3.50 3.00 POWER (dBm) 2.50 2.00 1.50 1.00 0.50 0.00 820 836 FREQUENCY (MHz) 850 VCC = -40C VCC = 27C VCC = 85C
2.00
820
836 FREQUENCY (MHz)
850
DUALTX vs. Frequency (TEMP 27C, TXLO = -10dBm)
72 CURRENT (AMPERES) 70 68 66 64 62 60 -40 27 TEMPERATURE (C) 85 VCC = 4.5V VCC = 4.0V VCC = 3.9V
DUALTX vs. Frequency (VCC = 4.0V, TXLO = -10dBm)
-16.00 -16.50 -17.00 POWER (dBm) -17.50 -18.00 -18.50 -19.00 -19.50 -20.00 900 970 FREQUENCY (MHz) 1040 T = +85C T = +27C T = -45C
DUAL ICC vs. Temperature
LO Buffer vs. Frequency (VCC = 4.0V, TXLO = -10dBm) Figure 12. Performance Characteristics 1997 Sept 16 16
SR00647
Philips Semiconductors
Preliminary specification
I/Q transmit modulator
SA900
PERFORMANCE CHARACTERISTICS
-43.00 -43.50 SUPPRESSION (dBc) -44.00 -44.50 -45.00 -45.50 -46.00 -46.50 -47.00 -47.50 820 836 FREQUENCY (MHz) 850 VCC = -40C VCC = 85C VCC = 27C
-44.50 -45.00 -45.50 -46.00 -46.50 -47.00 -47.50 820 836 FREQUENCY (MHz) 850 VCC = 4.5V VCC = 4.0V VCC = 3.9V
SUPPRESSION (dBc)
DUALTX Carrier Suppression vs. Frequency (VCC = 4.0, TXLO = -10dBm Single Sideband Mode, With Respect to Lower Sideband)
DUALTX Sideband Suppression vs. Frequency (Temperature = 27C, TXLO = -10dBm Single Sideband Mode, With Respect to Lower Sideband)
-34.00 -36.00 SUPPRESSION (dBc) -38.00 -40.00 -42.00 -44.00 -46.00 -48.00 820 836 FREQUENCY (MHz) 850 VCC = -85C VCC = -40C VCC = 27C
-32 -33 -34 -35 -36 dBc -37 -38 -39 -40 -41 -42 -40 27 TEMPERATURE (C)
VCC = 3.9V VCC = 4.0V VCC = 4.5V
85
DUALTX Sideband Suppression vs Frequency (VCC = 4.0V, TXLO = -10dBm Single Sideband Mode, With Respect to Lower Sideband)
DUALTX 3rd Order Products vs Temperature (TXLO = -10dBm, f = 836MHz, 0dB VGA I/Q Inphase)
-30.00 VCC = 3.9V VCC = 4.0V VCC = 4.5V
-30.00 -35.00 ATTENUATION (dB) -40.00 -45.00 -50.00 -55.00 -60.00 T = +85C T = +27C T = -45C
-35.00 ATTENUATION (dB)
-40.00
-45.00
-50.00
-55.00
0 2 5 7 10 13 15 18 20 23 25 26 29 33 37 40 44 48 51 55 59 63 VGA 6-BIT WORD VALUE (LSBs)
0 2 5 7 10 13 15 18 20 23 25 26 29 33 37 40 44 48 51 55 59 63 VGA 6-BIT WORD VALUE (LSBs)
DUALTX Carrier Suppression vs VGA Range (27C, f = 836MHz, TXLO = -10dBm)
DUALTX Carrier Suppression vs VGA Range (VCC = 4.0V, f = 836MHz, TXLO = -10dBm)
SR00648
Figure 13. Performance Characteristics
1997 Sept 16
17
Philips Semiconductors
Preliminary specification
I/Q transmit modulator
SA900
PERFORMANCE CHARACTERISTICS
0
-5
-10
ATTENUATION (dB)
-15 27C -20 -40C -25 85C -30
-35
-40
-45 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 VGA 6-BIT WORD VALUE (LSBs) 62
DUALTX VGA Attenuation Profile vs. Temperature (VCC = 4.0V, F = 836MHz)
0
-5
-10 3.9V -15 ATTENUATION (dB) 4.0V -20 4.6V -25
-30
-35
-40
-45 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 VGA 6-BIT WORD VALUE (LSBs) 62
DUALTX VGA Attenuation Profile vs. VCC (T = 27C, F = 836MHz)
SR00649
Figure 14. Performance Characteristics
1997 Sept 16
18
Philips Semiconductors
Preliminary specification
I/Q transmit modulator
SA900
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
1997 Sept 16
19
Philips Semiconductors
Preliminary specification
I/Q transmit modulator
SA900
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. (c) Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A.
Philips Semiconductors
1997 Sept 16 20

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